1 | #ifdef SYSTEMC |
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2 | /* |
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3 | * $Id: Ifetch_queue_transition.cpp 81 2008-04-15 18:40:01Z rosiere $ |
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4 | * |
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5 | * [ Description ] |
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6 | * |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Ifetch_queue.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | namespace core { |
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14 | namespace multi_front_end { |
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15 | namespace front_end { |
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16 | namespace ifetch_unit { |
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17 | namespace ifetch_queue { |
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18 | |
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19 | |
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20 | #undef FUNCTION |
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21 | #define FUNCTION "Ifetch_queue::transition" |
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22 | void Ifetch_queue::transition (void) |
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23 | { |
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24 | log_printf(FUNC,Ifetch_queue,FUNCTION,"Begin"); |
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25 | |
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26 | if (PORT_READ(in_NRESET) == 0) |
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27 | { |
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28 | reg_PTR_READ = 0; |
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29 | reg_PTR_WRITE = 0; |
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30 | |
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31 | for (uint32_t i=0; i<_param->_size_queue; i++) |
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32 | _queue [i]->_state = IFETCH_QUEUE_STATE_EMPTY; |
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33 | } |
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34 | else |
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35 | { |
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36 | // ========================================================== |
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37 | // =====[ ADDRESS ]========================================== |
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38 | // ========================================================== |
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39 | if (PORT_READ(in_ADDRESS_VAL) and internal_ADDRESS_ACK) |
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40 | { |
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41 | // New slot in ifetch_queue is allocated |
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42 | |
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43 | _queue[reg_PTR_WRITE]->_state = IFETCH_QUEUE_STATE_WAIT_RSP; |
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44 | |
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45 | #ifdef STATISTICS |
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46 | (*_sum_transaction_address) ++; |
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47 | #endif |
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48 | |
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49 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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50 | { |
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51 | Tcontrol_t enable = PORT_READ(in_ADDRESS_INSTRUCTION_ENABLE [i]); |
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52 | #ifdef STATISTICS |
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53 | (*_sum_inst_enable) += enable; |
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54 | #endif |
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55 | _queue[reg_PTR_WRITE]->_instruction_enable [i] = enable; |
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56 | } |
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57 | _queue[reg_PTR_WRITE]->_address = PORT_READ(in_ADDRESS_INSTRUCTION_ADDRESS ); |
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58 | _queue[reg_PTR_WRITE]->_inst_ifetch_ptr = (_param->_have_port_instruction_ptr)?PORT_READ(in_ADDRESS_INST_IFETCH_PTR ):0; |
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59 | _queue[reg_PTR_WRITE]->_branch_state = PORT_READ(in_ADDRESS_BRANCH_STATE ); |
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60 | _queue[reg_PTR_WRITE]->_branch_update_prediction_id = (_param->_have_port_branch_update_prediction_id)?PORT_READ(in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID):0; |
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61 | |
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62 | reg_PTR_WRITE = (reg_PTR_WRITE+1)%_param->_size_queue; |
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63 | } |
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64 | |
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65 | // ========================================================== |
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66 | // =====[ DECOD ]============================================ |
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67 | // ========================================================== |
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68 | bool have_instruction_decod = false; |
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69 | bool have_instruction_enable = false; |
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70 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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71 | { |
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72 | if (internal_DECOD_VAL [i] and PORT_READ(in_DECOD_ACK[i])) |
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73 | { |
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74 | have_instruction_decod = true; |
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75 | _queue[reg_PTR_READ]->_instruction_enable [i] = false; |
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76 | } |
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77 | have_instruction_enable |= _queue[reg_PTR_READ]->_instruction_enable [i]; |
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78 | } |
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79 | |
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80 | // Test if all is decoded |
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81 | if (have_instruction_decod and not have_instruction_enable) |
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82 | { |
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83 | // all is decod |
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84 | _queue[reg_PTR_READ]->_state = IFETCH_QUEUE_STATE_EMPTY; |
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85 | reg_PTR_READ = (reg_PTR_READ+1)%_param->_size_queue; |
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86 | } |
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87 | |
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88 | // ========================================================== |
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89 | // =====[ ICACHE_RSP ]======================================= |
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90 | // ========================================================== |
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91 | if (PORT_READ(in_ICACHE_RSP_VAL) and internal_ICACHE_RSP_ACK) |
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92 | { |
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93 | Tpacket_t ptr = (_param->_have_port_queue_ptr)?PORT_READ(in_ICACHE_RSP_PACKET_ID):0; |
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94 | |
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95 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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96 | _queue[ptr]->_instruction [i] = PORT_READ(in_ICACHE_RSP_INSTRUCTION [i]); |
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97 | |
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98 | switch (PORT_READ(in_ICACHE_RSP_ERROR)) |
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99 | { |
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100 | case ICACHE_ERROR_NONE : _queue[ptr]->_exception = EXCEPTION_IFETCH_NONE ; break; |
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101 | case ICACHE_ERROR_BUS_ERROR : _queue[ptr]->_exception = EXCEPTION_IFETCH_BUS_ERROR; break; |
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102 | default : ERRORMORPHEO(FUNCTION,"icache_rsp_error : unknow value."); |
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103 | } |
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104 | |
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105 | switch (_queue[ptr]->_state) |
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106 | { |
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107 | case IFETCH_QUEUE_STATE_WAIT_RSP : _queue[ptr]->_state = IFETCH_QUEUE_STATE_HAVE_RSP; break; |
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108 | case IFETCH_QUEUE_STATE_ERROR_WAIT_RSP : _queue[ptr]->_state = IFETCH_QUEUE_STATE_EMPTY ; break; |
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109 | default : ERRORMORPHEO(FUNCTION,"icache_rsp : invalid ifetch_queue state."); |
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110 | } |
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111 | } |
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112 | |
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113 | // ========================================================== |
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114 | // =====[ EVENT_RESET ]====================================== |
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115 | // ========================================================== |
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116 | if (PORT_READ(in_EVENT_RESET_VAL) and internal_EVENT_RESET_ACK) |
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117 | { |
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118 | // Scan all entry of queue and test the status |
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119 | for (uint32_t i=0; i<_param->_size_queue; i++) |
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120 | switch (_queue[i]->_state) |
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121 | { |
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122 | case IFETCH_QUEUE_STATE_ERROR_WAIT_RSP : break; |
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123 | case IFETCH_QUEUE_STATE_WAIT_RSP : _queue[i]->_state = IFETCH_QUEUE_STATE_ERROR_WAIT_RSP; break; |
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124 | default : _queue[i]->_state = IFETCH_QUEUE_STATE_EMPTY ; break; |
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125 | } |
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126 | |
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127 | // all entry is empty (or wait respons to flush) |
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128 | // reset ptr |
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129 | // 1) reg_PTR_READ = reg_PTR_WRITE = = 0 |
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130 | // 2) reg_PTR_READ = reg_PTR_WRITE |
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131 | // In method 1), the probalitie than the entry pointed by reg_PTR_WRITE is a slot with state "error_wait_rsp" is more importate that the method 2) |
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132 | reg_PTR_READ = reg_PTR_WRITE; |
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133 | } |
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134 | |
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135 | // log_printf(TRACE,Ifetch_queue,FUNCTION,"reg_PTR_WRITE : %d",reg_PTR_WRITE); |
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136 | // log_printf(TRACE,Ifetch_queue,FUNCTION,"reg_PTR_READ : %d",reg_PTR_READ ); |
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137 | // for (uint32_t i=0; i<_param->_size_queue; i++) |
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138 | // { |
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139 | // log_printf(TRACE,Ifetch_queue,FUNCTION,"[%d] %d %.8x %d - %d %d %d", i, _queue [i]->_state, _queue [i]->_address,_queue [i]->_inst_ifetch_ptr,_queue [i]->_branch_state,_queue [i]->_branch_update_prediction_id,_queue [i]->_exception); |
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140 | |
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141 | // for (uint32_t j=0; j<_param->_nb_instruction; j++) |
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142 | // log_printf(TRACE,Ifetch_queue,FUNCTION," * %d %.8x", _queue [i]->_instruction_enable[i], _queue [i]->_instruction[i]); |
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143 | // } |
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144 | |
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145 | #ifdef STATISTICS |
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146 | for (uint32_t i=0; i<_param->_size_queue; i++) |
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147 | switch (_queue[i]->_state) |
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148 | { |
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149 | case IFETCH_QUEUE_STATE_EMPTY : break; |
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150 | case IFETCH_QUEUE_STATE_WAIT_RSP : (*_sum_use_queue_wait_rsp ) ++; break; |
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151 | case IFETCH_QUEUE_STATE_HAVE_RSP : (*_sum_use_queue_have_rsp ) ++; break; |
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152 | case IFETCH_QUEUE_STATE_ERROR_WAIT_RSP : (*_sum_use_queue_error_wait_rsp) ++; break; |
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153 | default : break; |
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154 | } |
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155 | #endif |
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156 | } |
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157 | |
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158 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
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159 | end_cycle (); |
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160 | #endif |
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161 | |
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162 | log_printf(FUNC,Ifetch_queue,FUNCTION,"End"); |
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163 | }; |
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164 | |
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165 | }; // end namespace ifetch_queue |
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166 | }; // end namespace ifetch_unit |
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167 | }; // end namespace front_end |
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168 | }; // end namespace multi_front_end |
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169 | }; // end namespace core |
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170 | |
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171 | }; // end namespace behavioural |
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172 | }; // end namespace morpheo |
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173 | #endif |
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