1 | #ifdef SYSTEMC |
---|
2 | /* |
---|
3 | * $Id: Ifetch_queue_transition.cpp 101 2009-01-15 17:19:08Z rosiere $ |
---|
4 | * |
---|
5 | * [ Description ] |
---|
6 | * |
---|
7 | */ |
---|
8 | |
---|
9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Ifetch_queue.h" |
---|
10 | |
---|
11 | namespace morpheo { |
---|
12 | namespace behavioural { |
---|
13 | namespace core { |
---|
14 | namespace multi_front_end { |
---|
15 | namespace front_end { |
---|
16 | namespace ifetch_unit { |
---|
17 | namespace ifetch_queue { |
---|
18 | |
---|
19 | |
---|
20 | #undef FUNCTION |
---|
21 | #define FUNCTION "Ifetch_queue::transition" |
---|
22 | void Ifetch_queue::transition (void) |
---|
23 | { |
---|
24 | log_begin(Ifetch_queue,FUNCTION); |
---|
25 | |
---|
26 | if (PORT_READ(in_NRESET) == 0) |
---|
27 | { |
---|
28 | reg_PTR_READ = 0; |
---|
29 | reg_PTR_WRITE = 0; |
---|
30 | |
---|
31 | for (uint32_t i=0; i<_param->_size_queue; i++) |
---|
32 | _queue [i]->_state = IFETCH_QUEUE_STATE_EMPTY; |
---|
33 | } |
---|
34 | else |
---|
35 | { |
---|
36 | // ========================================================== |
---|
37 | // =====[ ADDRESS ]========================================== |
---|
38 | // ========================================================== |
---|
39 | if (PORT_READ(in_ADDRESS_VAL) and internal_ADDRESS_ACK) |
---|
40 | { |
---|
41 | // New slot in ifetch_queue is allocated |
---|
42 | |
---|
43 | _queue[reg_PTR_WRITE]->_state = IFETCH_QUEUE_STATE_WAIT_RSP; |
---|
44 | |
---|
45 | #ifdef STATISTICS |
---|
46 | if (usage_is_set(_usage,USE_STATISTICS)) |
---|
47 | (*_sum_transaction_address) ++; |
---|
48 | #endif |
---|
49 | |
---|
50 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
---|
51 | { |
---|
52 | Tcontrol_t enable = PORT_READ(in_ADDRESS_INSTRUCTION_ENABLE [i]); |
---|
53 | #ifdef STATISTICS |
---|
54 | if (usage_is_set(_usage,USE_STATISTICS)) |
---|
55 | (*_sum_inst_enable) += enable; |
---|
56 | #endif |
---|
57 | _queue[reg_PTR_WRITE]->_instruction_enable [i] = enable; |
---|
58 | } |
---|
59 | |
---|
60 | _queue[reg_PTR_WRITE]->_address = PORT_READ(in_ADDRESS_INSTRUCTION_ADDRESS); |
---|
61 | _queue[reg_PTR_WRITE]->_inst_ifetch_ptr = (_param->_have_port_inst_ifetch_ptr)?PORT_READ(in_ADDRESS_INST_IFETCH_PTR ):0; |
---|
62 | _queue[reg_PTR_WRITE]->_branch_state = PORT_READ(in_ADDRESS_BRANCH_STATE); |
---|
63 | _queue[reg_PTR_WRITE]->_branch_update_prediction_id = (_param->_have_port_depth)?PORT_READ(in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID):0; |
---|
64 | |
---|
65 | reg_PTR_WRITE = (reg_PTR_WRITE+1)%_param->_size_queue; |
---|
66 | } |
---|
67 | |
---|
68 | // ========================================================== |
---|
69 | // =====[ DECOD ]============================================ |
---|
70 | // ========================================================== |
---|
71 | bool have_instruction_decod = false; |
---|
72 | bool have_instruction_enable = false; |
---|
73 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
---|
74 | { |
---|
75 | if (internal_DECOD_VAL [i] and PORT_READ(in_DECOD_ACK[i])) |
---|
76 | { |
---|
77 | have_instruction_decod = true; |
---|
78 | _queue[reg_PTR_READ]->_instruction_enable [i] = false; |
---|
79 | } |
---|
80 | have_instruction_enable |= _queue[reg_PTR_READ]->_instruction_enable [i]; |
---|
81 | } |
---|
82 | |
---|
83 | // Test if all is decoded |
---|
84 | if (have_instruction_decod and not have_instruction_enable) |
---|
85 | { |
---|
86 | // all is decod |
---|
87 | _queue[reg_PTR_READ]->_state = IFETCH_QUEUE_STATE_EMPTY; |
---|
88 | reg_PTR_READ = (reg_PTR_READ+1)%_param->_size_queue; |
---|
89 | } |
---|
90 | |
---|
91 | // ========================================================== |
---|
92 | // =====[ ICACHE_RSP ]======================================= |
---|
93 | // ========================================================== |
---|
94 | if (PORT_READ(in_ICACHE_RSP_VAL) and internal_ICACHE_RSP_ACK) |
---|
95 | { |
---|
96 | Tpacket_t ptr = (_param->_have_port_ifetch_queue_ptr)?PORT_READ(in_ICACHE_RSP_PACKET_ID):0; |
---|
97 | |
---|
98 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
---|
99 | _queue[ptr]->_instruction [i] = PORT_READ(in_ICACHE_RSP_INSTRUCTION [i]); |
---|
100 | |
---|
101 | switch (PORT_READ(in_ICACHE_RSP_ERROR)) |
---|
102 | { |
---|
103 | case ICACHE_ERROR_NONE : _queue[ptr]->_exception = EXCEPTION_IFETCH_NONE ; break; |
---|
104 | case ICACHE_ERROR_BUS_ERROR : _queue[ptr]->_exception = EXCEPTION_IFETCH_BUS_ERROR; break; |
---|
105 | default : ERRORMORPHEO(FUNCTION,"icache_rsp_error : unknow value."); |
---|
106 | } |
---|
107 | |
---|
108 | switch (_queue[ptr]->_state) |
---|
109 | { |
---|
110 | case IFETCH_QUEUE_STATE_WAIT_RSP : _queue[ptr]->_state = IFETCH_QUEUE_STATE_HAVE_RSP; break; |
---|
111 | case IFETCH_QUEUE_STATE_ERROR_WAIT_RSP : _queue[ptr]->_state = IFETCH_QUEUE_STATE_EMPTY ; break; |
---|
112 | default : ERRORMORPHEO(FUNCTION,"icache_rsp : invalid ifetch_queue state."); |
---|
113 | } |
---|
114 | } |
---|
115 | |
---|
116 | // ========================================================== |
---|
117 | // =====[ EVENT_RESET ]====================================== |
---|
118 | // ========================================================== |
---|
119 | if (PORT_READ(in_EVENT_RESET_VAL) and internal_EVENT_RESET_ACK) |
---|
120 | { |
---|
121 | // Scan all entry of queue and test the status |
---|
122 | for (uint32_t i=0; i<_param->_size_queue; i++) |
---|
123 | switch (_queue[i]->_state) |
---|
124 | { |
---|
125 | case IFETCH_QUEUE_STATE_ERROR_WAIT_RSP : break; |
---|
126 | case IFETCH_QUEUE_STATE_WAIT_RSP : _queue[i]->_state = IFETCH_QUEUE_STATE_ERROR_WAIT_RSP; break; |
---|
127 | default : _queue[i]->_state = IFETCH_QUEUE_STATE_EMPTY ; break; |
---|
128 | } |
---|
129 | |
---|
130 | // all entry is empty (or wait respons to flush) |
---|
131 | // reset ptr |
---|
132 | // 1) reg_PTR_READ = reg_PTR_WRITE = = 0 |
---|
133 | // 2) reg_PTR_READ = reg_PTR_WRITE |
---|
134 | // In method 1), the probalitie than the entry pointed by reg_PTR_WRITE is a slot with state "error_wait_rsp" is more importate that the method 2) |
---|
135 | reg_PTR_READ = reg_PTR_WRITE; |
---|
136 | } |
---|
137 | |
---|
138 | #if defined(DEBUG) and (DEBUG >= DEBUG_TRACE) |
---|
139 | log_printf(TRACE,Ifetch_queue,FUNCTION," * Dump ifetch_queue"); |
---|
140 | log_printf(TRACE,Ifetch_queue,FUNCTION," * reg_PTR_WRITE : %d",reg_PTR_WRITE); |
---|
141 | log_printf(TRACE,Ifetch_queue,FUNCTION," * reg_PTR_READ : %d",reg_PTR_READ ); |
---|
142 | for (uint32_t i=0; i<_param->_size_queue; i++) |
---|
143 | { |
---|
144 | log_printf(TRACE,Ifetch_queue,FUNCTION," * [%d] 0x%.8x (0x%.8x) %d - %d %d %d - %s", |
---|
145 | i, |
---|
146 | _queue [i]->_address, |
---|
147 | _queue [i]->_address<<2, |
---|
148 | _queue [i]->_inst_ifetch_ptr, |
---|
149 | _queue [i]->_branch_state, |
---|
150 | _queue [i]->_branch_update_prediction_id, |
---|
151 | _queue [i]->_exception, |
---|
152 | toString(_queue [i]->_state).c_str() |
---|
153 | ); |
---|
154 | |
---|
155 | for (uint32_t j=0; j<_param->_nb_instruction; j++) |
---|
156 | log_printf(TRACE,Ifetch_queue,FUNCTION," * %d 0x%.8x", _queue [i]->_instruction_enable[j], _queue [i]->_instruction[j]); |
---|
157 | } |
---|
158 | #endif |
---|
159 | |
---|
160 | #ifdef STATISTICS |
---|
161 | if (usage_is_set(_usage,USE_STATISTICS)) |
---|
162 | for (uint32_t i=0; i<_param->_size_queue; i++) |
---|
163 | switch (_queue[i]->_state) |
---|
164 | { |
---|
165 | case IFETCH_QUEUE_STATE_EMPTY : break; |
---|
166 | case IFETCH_QUEUE_STATE_WAIT_RSP : (*_sum_use_queue_wait_rsp ) ++; break; |
---|
167 | case IFETCH_QUEUE_STATE_HAVE_RSP : (*_sum_use_queue_have_rsp ) ++; break; |
---|
168 | case IFETCH_QUEUE_STATE_ERROR_WAIT_RSP : (*_sum_use_queue_error_wait_rsp) ++; break; |
---|
169 | default : break; |
---|
170 | } |
---|
171 | #endif |
---|
172 | } |
---|
173 | |
---|
174 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
---|
175 | end_cycle (); |
---|
176 | #endif |
---|
177 | |
---|
178 | log_end(Ifetch_queue,FUNCTION); |
---|
179 | }; |
---|
180 | |
---|
181 | }; // end namespace ifetch_queue |
---|
182 | }; // end namespace ifetch_unit |
---|
183 | }; // end namespace front_end |
---|
184 | }; // end namespace multi_front_end |
---|
185 | }; // end namespace core |
---|
186 | |
---|
187 | }; // end namespace behavioural |
---|
188 | }; // end namespace morpheo |
---|
189 | #endif |
---|