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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_vhdl_body.cpp @ 135

Last change on this file since 135 was 135, checked in by rosiere, 15 years ago
1) Add Vhdl component 2) Inhib VHDL Seltest interface
Property svn:keywords set to `Id`
File size: 18.4 KB

Line
1	#ifdef VHDL
2	/*
3	* $Id: Ifetch_queue_vhdl_body.cpp 135 2009-07-17 08:59:05Z rosiere $
4	*
5	* [ Description ]
6	*
7	*/
8
9	#include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Ifetch_queue.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_front_end {
15	namespace front_end {
16	namespace ifetch_unit {
17	namespace ifetch_queue {
18
19
20	#undef FUNCTION
21	#define FUNCTION "Ifetch_queue::vhdl_body"
22	void Ifetch_queue::vhdl_body (Vhdl * & vhdl)
23	{
24	log_printf(FUNC,Ifetch_queue,FUNCTION,"Begin");
25
26	vhdl->set_comment(0,"=========================================");
27	vhdl->set_comment(0,"===== CONSTANT ==========================");
28	vhdl->set_comment(0,"=========================================");
29	vhdl->set_body (0,"");
30	vhdl->set_body (0,"internal_ICACHE_RSP_ACK <= '1';");
31	vhdl->set_body (0,"internal_EVENT_RESET_ACK <= '1';");
32	vhdl->set_body (0,"out_EVENT_RESET_ACK <= '1';");
33	vhdl->set_body (0,"out_ICACHE_RSP_ACK <= '1';");
34	vhdl->set_body (0,"");
35	vhdl->set_comment(0,"---------------------------------------------------------------------------");
36	vhdl->set_comment(0,"TRANSLATION ");
37	vhdl->set_comment(0,"---------------------------------------------------------------------------");
38	vhdl->set_body (0,"TRANSITION : process (in_CLOCK)");
39	vhdl->set_body (0,"variable have_instruction_decod : std_logic;");
40	vhdl->set_body (0,"variable have_instruction_enable : std_logic;");
41	// vhdl->set_body (0,"variable reg_INSTRUCTION_ENABLE_VAR : std_logic;");
42	if (_param->_size_queue>1) {
43	vhdl->set_body (0,"variable var_PTR_READ :"+ std_logic(log2(_param->_size_queue))+";");
44	vhdl->set_body (0,"variable var_PTR_WRITE :"+ std_logic(log2(_param->_size_queue))+";");
45	}
46	// vhdl->set_body (0,"variable var_EMPTY : std_logic;");
47	vhdl->set_body (0,"variable var_STATE : Tstate;");
48	vhdl->set_body (0,"variable var_INSTRUCTION_ENABLE : Tenable;");
49	vhdl->set_body (0,"variable var_ADDRESS : Tadress;");
50	if(_param->_have_port_inst_ifetch_ptr)
51	vhdl->set_body (0,"variable var_INST_IFETCH_PTR : Tinst_ptr;");
52	vhdl->set_body (0,"variable var_BRANCH_STATE : Tbranch_state;");
53	if(_param->_have_port_depth)
54	vhdl->set_body (0,"variable var_BRANCH_UPDATE_PREDICTION_ID : "+std_logic(_param->_size_depth)+";");
55	// vhdl->set_body (0,"variable var_internal_ICACHE_RSP_ACK : std_logic;");
56	if (_param->_have_port_ifetch_queue_ptr)
57	vhdl->set_body (0,"variable var_internal_ICACHE_RSP_PACKET_ID : "+std_logic(_param->_size_ifetch_queue_ptr)+";");
58	vhdl->set_body (0,"variable var_EXCEPTION : Texception;");
59
60
61	vhdl->set_body (0,"begin -- TRANSITION");
62	vhdl->set_body (1,"if (in_CLOCK'event and in_CLOCK = '1')then");
63	vhdl->set_body (0,"");
64	vhdl->set_comment(2,"---------------------------------------------------------------------------");
65	vhdl->set_comment(2,"Reset");
66	vhdl->set_comment(2,"---------------------------------------------------------------------------");
67	vhdl->set_body (2,"if (in_NRESET = '0') then");
68	if (_param->_size_queue>1)
69	{
70	vhdl->set_body (3,"reg_PTR_READ <= "+std_logic_cst( log2(_param->_size_queue), 0)+";");
71	vhdl->set_body (3,"reg_PTR_WRITE <= "+std_logic_cst( log2(_param->_size_queue), 0)+";");
72	}
73	// vhdl->set_body (3,"var_EMPTY := '1';");
74
75	for (uint32_t i=0; i<_param->_size_queue; i++)
76	{
77	vhdl->set_body (3,"reg_STATE("+toString(i)+") <= IFETCH_QUEUE_STATE_EMPTY;");
78	}
79
80	vhdl->set_body (3,"");
81	vhdl->set_body (2,"else");
82	vhdl->set_body (3,"");
83	// std::string write = (_param->_size_queue==1)?"0":"conv_integer(reg_PTR_WRITE)";
84	// vhdl->set_body (3,"var_STATE := reg_STATE ("+write+");");
85	vhdl->set_body (3,"var_STATE := reg_STATE ;");
86	if (_param->_size_queue>1)
87	{
88	vhdl->set_body (3,"var_PTR_READ := reg_PTR_READ;");
89	vhdl->set_body (3,"var_PTR_WRITE := reg_PTR_WRITE;");
90	}
91
92	// if (_param->_size_queue>1)
93	// {
94	// vhdl->set_body (3,"var_EMPTY := reg_EMPTY ;");
95	// }
96	vhdl->set_body (3,"var_INSTRUCTION_ENABLE := reg_INSTRUCTION_ENABLE ;");
97	vhdl->set_body (3,"var_ADDRESS := reg_ADDRESS ;");
98	if(_param->_have_port_inst_ifetch_ptr)
99	vhdl->set_body (3,"var_INST_IFETCH_PTR := reg_INST_IFETCH_PTR ;");
100	if (_param->_have_port_ifetch_queue_ptr)
101	// vhdl->set_body (3,"var_BRANCH_UPDATE_PREDICTION_ID := reg_BRANCH_UPDATE_PREDICTION_ID;");
102	vhdl->set_body (3,"var_BRANCH_STATE := reg_BRANCH_STATE ;");
103	vhdl->set_body (3,"var_EXCEPTION := reg_EXCEPTION ;");
104
105	vhdl->set_comment(3,"---------------------------------------------------------------------------");
106	vhdl->set_comment(3,"ADDRESS ");
107	vhdl->set_comment(3,"---------------------------------------------------------------------------");
108	{
109	std::string reg_ptr_write = (_param->_size_queue==1)?"0":"conv_integer(reg_PTR_WRITE)";
110	vhdl->set_body (3,"if ((in_ADDRESS_VAL and internal_ADDRESS_ACK) = '1') then");
111	vhdl->set_body (3,"var_STATE ("+reg_ptr_write+") := IFETCH_QUEUE_STATE_WAIT_RSP;");
112	for (uint32_t i=0; i<_param->_nb_instruction; i++)
113	vhdl->set_body (3,"var_INSTRUCTION_ENABLE ("+reg_ptr_write+")("+toString(i)+") := in_address_"+toString(i)+"_instruction_enable;");
114
115	vhdl->set_body (3,"var_ADDRESS("+reg_ptr_write+") := in_ADDRESS_INSTRUCTION_ADDRESS;");
116	if(_param->_have_port_inst_ifetch_ptr)
117	{
118	vhdl->set_body (3,"var_INST_IFETCH_PTR("+reg_ptr_write+") := in_ADDRESS_INST_IFETCH_PTR;");
119	}
120	vhdl->set_body (3,"var_BRANCH_STATE("+reg_ptr_write+") := in_ADDRESS_BRANCH_STATE;");
121	if(_param->_have_port_depth)
122	vhdl->set_body (3,"var_BRANCH_UPDATE_PREDICTION_ID := in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID;");
123	if (_param->_size_queue>1)
124	{
125	vhdl->set_body (3,"if (var_PTR_WRITE ="+std_logic_cst( log2(_param->_size_queue),_param->_size_queue-1)+") then");
126	vhdl->set_body (3,"var_PTR_WRITE := "+std_logic_cst( log2(_param->_size_queue), 0)+";");
127	vhdl->set_body (3,"else");
128	if (_param->_size_ifetch_queue_ptr == 1)
129	vhdl->set_body (3,"var_PTR_WRITE := not var_PTR_WRITE;");
130	else
131	vhdl->set_body (3,"var_PTR_WRITE := (var_PTR_WRITE +"+std_logic_cst( log2(_param->_size_queue),1)+");");
132	vhdl->set_body (3,"end if;");
133	}
134	vhdl->set_body (3,"end if;");
135	}
136	vhdl->set_comment(3,"---------------------------------------------------------------------------");
137	vhdl->set_comment(3,"DECOD ");
138	vhdl->set_comment(3,"---------------------------------------------------------------------------");
139
140	// have_instruction_decod <= ((internal_DECOD_0_VAL and in_DECOD_0_ACK) or
141	// (internal_DECOD_1_VAL and in_DECOD_1_ACK) or
142	// (internal_DECOD_2_VAL and in_DECOD_2_ACK) or
143	// (internal_DECOD_3_VAL and in_DECOD_3_ACK));
144	vhdl->set_body (3,"have_instruction_decod := '0';");
145	vhdl->set_body (3,"have_instruction_enable := '0';");
146	std::string reg_ptr_read = (_param->_size_queue==1)?"0":"conv_integer(reg_PTR_READ)";
147	for (uint32_t i=0; i<_param->_nb_instruction; i++)
148	{
149	vhdl->set_body (3,"if ((internal_DECOD_"+toString(i)+"_VAL and in_DECOD_"+toString(i)+"_ACK) = '1') then");
150	vhdl->set_body (4,"have_instruction_decod := '1';");
151	vhdl->set_body (4,"var_INSTRUCTION_ENABLE ("+reg_ptr_read+")("+toString(i)+") := '0';");
152	vhdl->set_body (3,"end if;");
153	vhdl->set_body (4,"have_instruction_enable := have_instruction_enable or var_INSTRUCTION_ENABLE ("+reg_ptr_read+")("+toString(i)+");");
154	}
155	vhdl->set_body (3,"if (have_instruction_decod = '1') then");
156	vhdl->set_body (3,"if (have_instruction_enable = '0') then");
157	vhdl->set_body (4,"var_STATE ("+reg_ptr_read+") := IFETCH_QUEUE_STATE_EMPTY;");
158
159	if(_param->_size_queue>1)
160	{
161	vhdl->set_body (4,"if (var_PTR_READ ="+std_logic_cst( log2(_param->_size_queue),_param->_size_queue-1)+") then");
162	vhdl->set_body (4,"var_PTR_READ := "+std_logic_cst( log2(_param->_size_queue), 0)+"; else");
163	if (_param->_size_ifetch_queue_ptr == 1)
164	vhdl->set_body (4,"var_PTR_READ := not var_PTR_READ;");
165	else
166	vhdl->set_body (4,"var_PTR_READ := var_PTR_READ +"+std_logic_cst( log2(_param->_size_queue),1)+";");
167	vhdl->set_body (4,"end if;");
168	}
169	vhdl->set_body (3,"end if;");
170	vhdl->set_body (3,"end if;");
171
172	vhdl->set_comment(3,"---------------------------------------------------------------------------");
173	vhdl->set_comment(3,"ICACHE_RSP ");
174	vhdl->set_comment(3,"---------------------------------------------------------------------------");
175	{ std::string address;
176	if (_param->_have_port_ifetch_queue_ptr)
177	{
178	address="conv_integer(var_internal_ICACHE_RSP_PACKET_ID)";
179	}
180	else
181	{
182	address="0";
183	}
184	vhdl->set_body (3,"if ((in_ICACHE_RSP_VAL and internal_ICACHE_RSP_ACK)= '1') then");
185	if (_param->_have_port_ifetch_queue_ptr)
186	{
187	vhdl->set_body(4,"var_internal_ICACHE_RSP_PACKET_ID := in_ICACHE_RSP_PACKET_ID;");
188	}
189	for (uint32_t i=0; i<_param->_nb_instruction; i++)
190	vhdl->set_body(3,"reg_DATA("+address+")("+toString(i)+") <= in_ICACHE_RSP_"+toString(i)+"_INSTRUCTION ;");
191
192	vhdl->set_body(4,"if (in_ICACHE_RSP_ERROR = ICACHE_ERROR_NONE) then");
193	vhdl->set_body(5,"var_EXCEPTION("+address+") := EXCEPTION_IFETCH_NONE;");
194	vhdl->set_body(4,"else if (in_ICACHE_RSP_ERROR = ICACHE_ERROR_BUS_ERROR) then");
195	vhdl->set_body(5,"var_EXCEPTION("+address+") := EXCEPTION_IFETCH_BUS_ERROR;");
196	vhdl->set_body (4,"end if;");
197	vhdl->set_body (4,"end if;");
198	vhdl->set_body(4,"if (var_STATE("+address+") = IFETCH_QUEUE_STATE_WAIT_RSP) then");
199	vhdl->set_body(5," var_STATE("+address+") := IFETCH_QUEUE_STATE_HAVE_RSP;");
200	vhdl->set_body(4,"else if var_STATE("+address+") = IFETCH_QUEUE_STATE_ERROR_WAIT_RSP then");
201	vhdl->set_body(5," var_STATE("+address+") := IFETCH_QUEUE_STATE_EMPTY;");
202	vhdl->set_body (4,"end if;");
203	vhdl->set_body (4,"end if;");
204	vhdl->set_body (3,"end if;");
205	}
206
207	vhdl->set_comment(3,"---------------------------------------------------------------------------");
208	vhdl->set_comment(3,"EVENT_RESET");
209	vhdl->set_comment(3,"---------------------------------------------------------------------------");
210	vhdl->set_body (3,"if ((in_EVENT_RESET_VAL and internal_EVENT_RESET_ACK) = '1' ) then");
211	for (uint32_t i=0; i<_param->_size_queue; i++) {
212	vhdl->set_body(4,"if (var_STATE("+toString(i)+") = IFETCH_QUEUE_STATE_ERROR_WAIT_RSP) then ");
213	vhdl->set_body(4,"var_STATE("+toString(i)+") := IFETCH_QUEUE_STATE_ERROR_WAIT_RSP;");
214	vhdl->set_body(4,"else if var_STATE("+toString(i)+") = IFETCH_QUEUE_STATE_WAIT_RSP then ");
215	vhdl->set_body(4,"var_STATE("+toString(i)+") := IFETCH_QUEUE_STATE_ERROR_WAIT_RSP;");
216	vhdl->set_body(4,"else var_STATE("+toString(i)+") := IFETCH_QUEUE_STATE_EMPTY;");
217	if (_param->_size_queue>1)
218	vhdl->set_body(5,"var_PTR_READ := var_PTR_WRITE;");
219	// else
220	// vhdl->set_body(5,"reg_EMPTY <= '1';");
221
222	vhdl->set_body(4,"end if;");
223	vhdl->set_body(4,"end if;");
224	}
225	//vhdl->set_body (3,"end if;");
226	vhdl->set_body (3,"end if;");
227
228	vhdl->set_comment(3,"---------------------------------------------------------------------------");
229	vhdl->set_comment(3,"WRITE Register");
230	vhdl->set_comment(3,"---------------------------------------------------------------------------");
231	{
232	if (_param->_size_queue>1) {
233	vhdl->set_body (3,"reg_PTR_READ <= var_PTR_READ;");
234	vhdl->set_body (3,"reg_PTR_WRITE <= var_PTR_WRITE;");
235	}
236	// vhdl->set_body (3,"reg_EMPTY <= var_EMPTY;");
237	std::string reg_ptr_write = (_param->_size_queue==1)?"0":"conv_integer(reg_PTR_WRITE)";
238	// vhdl->set_body (3,"reg_STATE ("+reg_ptr_write+") <= var_STATE;");
239	vhdl->set_body (3,"reg_STATE <= var_STATE;");
240	for (uint32_t i=0; i<_param->_nb_instruction; i++)
241	vhdl->set_body (3,"reg_INSTRUCTION_ENABLE("+reg_ptr_write+")("+toString(i)+") <= var_INSTRUCTION_ENABLE("+reg_ptr_write+")("+toString(i)+");");
242	// vhdl->set_body (3,"reg_ADDRESS ("+reg_ptr_write+") <= var_ADDRESS;");
243	vhdl->set_body (3,"reg_ADDRESS <= var_ADDRESS;");
244	if(_param->_have_port_inst_ifetch_ptr)
245	// vhdl->set_body (3,"reg_INST_IFETCH_PTR ("+reg_ptr_write+") <= var_INST_IFETCH_PTR;");
246	vhdl->set_body (3,"reg_INST_IFETCH_PTR <= var_INST_IFETCH_PTR;");
247	// vhdl->set_body (3,"reg_BRANCH_STATE ("+reg_ptr_write+") <= var_BRANCH_STATE;");
248	vhdl->set_body (3,"reg_BRANCH_STATE <= var_BRANCH_STATE;");
249	if(_param->_have_port_depth)
250	vhdl->set_body (3,"reg_BRANCH_UPDATE_PREDICTION_ID("+reg_ptr_write+") <= var_BRANCH_UPDATE_PREDICTION_ID;");
251	if (_param->_size_queue>1)
252	vhdl->set_body (3,"reg_PTR_WRITE <= var_PTR_WRITE;");
253
254	std::string reg_ptr_read = (_param->_size_queue==1)?"0":"conv_integer(reg_PTR_READ)";
255	for (uint32_t i=0; i<_param->_nb_instruction; i++)
256	vhdl->set_body (3,"reg_INSTRUCTION_ENABLE("+reg_ptr_read+") ("+toString(i)+") <= var_INSTRUCTION_ENABLE("+reg_ptr_read+")("+toString(i)+");");
257	// vhdl->set_body (3,"reg_STATE("+reg_ptr_read+") <= var_STATE;");
258	if(_param->_size_queue>1)
259	vhdl->set_body (3,"reg_PTR_READ <= var_PTR_READ ;");
260	// vhdl->set_body (3,"internal_ICACHE_RSP_ACK <= internal_ICACHE_RSP_ACK;");
261	if (_param->_have_port_ifetch_queue_ptr)
262	{
263	vhdl->set_body (3,"internal_ICACHE_RSP_PACKET_ID <= var_internal_ICACHE_RSP_PACKET_ID;");
264	std::string address;
265	if (_param->_have_port_ifetch_queue_ptr)
266	address="conv_integer(var_internal_ICACHE_RSP_PACKET_ID)";
267	else
268	address="0";
269	// vhdl->set_body (3,"reg_EXCEPTION("+address+") <= var_EXCEPTION;");
270	vhdl->set_body (3,"reg_EXCEPTION <= var_EXCEPTION;");
271	}
272	}
273	vhdl->set_body (2,"end if;");
274	vhdl->set_body (1,"end if;");
275	vhdl->set_body (0,"end process; -- TRANSITION");
276
277
278	vhdl->set_comment(0,"---------------------------------------------------------------------------");
279	vhdl->set_comment(0,"GENMOORE");
280	vhdl->set_comment(0,"---------------------------------------------------------------------------");
281	vhdl->set_comment(0,"---------------------------------------------------------------------------");
282	vhdl->set_comment(0,"ADDRESS ");
283	vhdl->set_comment(0,"---------------------------------------------------------------------------");
284	{
285	std::string reg_ptr_write = (_param->_size_queue==1)?"0":"conv_integer(reg_PTR_WRITE)";
286	vhdl->set_body (1,"internal_ADDRESS_ACK <= '1' WHEN (reg_STATE("+reg_ptr_write+") = IFETCH_QUEUE_STATE_EMPTY) ELSE");
287	vhdl->set_body (1,"'0';");
288	vhdl->set_body (1,"out_ADDRESS_ACK <= internal_ADDRESS_ACK;");
289	if (_param->_have_port_ifetch_queue_ptr) {
290	vhdl->set_body (1,"out_ADDRESS_IFETCH_QUEUE_ID <= reg_PTR_WRITE;");
291	}
292	}
293	vhdl->set_comment(0,"---------------------------------------------------------------------------");
294	vhdl->set_comment(0,"DECOD ");
295	vhdl->set_comment(0,"---------------------------------------------------------------------------");
296	{
297	std::string reg_ptr_read = (_param->_size_queue==1)?"0":"conv_integer(reg_PTR_READ)";
298	vhdl->set_body (0,"internal_ack <= '1' WHEN (reg_STATE("+reg_ptr_read+") = IFETCH_QUEUE_STATE_HAVE_RSP) ELSE");
299	vhdl->set_body (0,"'0';");
300	for (uint32_t j=0; j<_param->_nb_instruction; j++)
301	{
302	vhdl->set_body(0,"internal_DECOD_"+toString(j)+"_VAL <= (internal_ack AND reg_INSTRUCTION_ENABLE("+reg_ptr_read+")("+toString(j)+"));");
303	vhdl->set_body(0,"out_DECOD_"+toString(j)+"_VAL <= internal_DECOD_"+toString(j)+"_VAL;");
304	vhdl->set_body(0,"out_DECOD_"+toString(j)+"_INSTRUCTION <= reg_DATA("+reg_ptr_read+")("+toString(j)+") ;");
305	}
306	vhdl->set_body(0,"out_DECOD_ADDRESS <= reg_ADDRESS("+reg_ptr_read+");");
307	if (_param->_have_port_inst_ifetch_ptr)
308	vhdl->set_body(0,"out_DECOD_INST_IFETCH_PTR <= reg_INST_IFETCH_PTR("+reg_ptr_read+");");
309	vhdl->set_body(0,"out_DECOD_BRANCH_STATE <= reg_BRANCH_STATE("+reg_ptr_read+");");
310	if (_param->_have_port_depth)
311	vhdl->set_body(0,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID <= reg_BRANCH_UPDATE_PREDICTION_ID("+reg_ptr_read+");");
312	vhdl->set_body(0,"out_DECOD_EXCEPTION <= reg_EXCEPTION("+reg_ptr_read+");");
313	}
314	vhdl->set_body(0,"");
315
316	log_printf(FUNC,Ifetch_queue,FUNCTION,"End");
317	};
318
319	}; // end namespace ifetch_queue
320	}; // end namespace ifetch_unit
321	}; // end namespace front_end
322	}; // end namespace multi_front_end
323	}; // end namespace core
324
325	}; // end namespace behavioural
326	}; // end namespace morpheo
327	#endif

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