1 | /* |
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2 | * $Id$ |
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3 | * |
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4 | * [ Description ] |
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5 | * |
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6 | * Test |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/include/test.h" |
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10 | #include "Common/include/Test.h" |
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11 | #include "Behavioural/include/Allocation.h" |
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12 | |
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13 | #define NB_ITERATION 1 |
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14 | #define CYCLE_MAX (128*NB_ITERATION) |
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15 | |
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16 | #define LABEL(str...) \ |
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17 | { \ |
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18 | msg (_("{%d} "),static_cast<uint32_t>(sc_simulation_time())); \ |
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19 | msg (str); \ |
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20 | msg (_("\n")); \ |
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21 | } while(0) |
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22 | |
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23 | #define SC_START(cycle_offset) \ |
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24 | do \ |
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25 | { \ |
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26 | /*cout << "SC_START (begin)" << endl;*/ \ |
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27 | \ |
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28 | uint32_t cycle_current = static_cast<uint32_t>(sc_simulation_time()); \ |
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29 | if (cycle_offset != 0) \ |
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30 | { \ |
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31 | cout << "##########[ cycle "<< cycle_current+cycle_offset << " ]" << endl; \ |
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32 | } \ |
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33 | \ |
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34 | if (cycle_current > CYCLE_MAX) \ |
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35 | { \ |
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36 | TEST_KO("Maximal cycles Reached"); \ |
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37 | } \ |
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38 | \ |
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39 | sc_start(cycle_offset); \ |
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40 | \ |
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41 | /*cout << "SC_START (end )" << endl;*/ \ |
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42 | } while(0) |
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43 | |
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44 | void test (string name, |
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45 | morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::Parameters * _param) |
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46 | { |
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47 | msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); |
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48 | |
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49 | #ifdef STATISTICS |
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50 | morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50); |
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51 | #endif |
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52 | |
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53 | Ifetch_unit * _Ifetch_unit = new Ifetch_unit (name.c_str(), |
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54 | #ifdef STATISTICS |
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55 | _parameters_statistics, |
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56 | #endif |
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57 | _param); |
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58 | |
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59 | #ifdef SYSTEMC |
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60 | /********************************************************************* |
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61 | * Déclarations des signaux |
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62 | *********************************************************************/ |
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63 | string rename; |
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64 | |
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65 | sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); |
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66 | sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); |
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67 | |
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68 | ALLOC_SC_SIGNAL (out_ICACHE_REQ_VAL ,"out_ICACHE_REQ_VAL ",Tcontrol_t ); |
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69 | ALLOC_SC_SIGNAL ( in_ICACHE_REQ_ACK ," in_ICACHE_REQ_ACK ",Tcontrol_t ); |
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70 | //ALLOC_SC_SIGNAL (out_ICACHE_REQ_THREAD_ID ,"out_ICACHE_REQ_THREAD_ID ",Tcontext_t ); |
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71 | ALLOC_SC_SIGNAL (out_ICACHE_REQ_PACKET_ID ,"out_ICACHE_REQ_PACKET_ID ",Tpacket_t ); |
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72 | ALLOC_SC_SIGNAL (out_ICACHE_REQ_ADDRESS ,"out_ICACHE_REQ_ADDRESS ",Ticache_instruction_t); |
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73 | ALLOC_SC_SIGNAL (out_ICACHE_REQ_TYPE ,"out_ICACHE_REQ_TYPE ",Ticache_type_t ); |
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74 | ALLOC_SC_SIGNAL ( in_ICACHE_RSP_VAL ," in_ICACHE_RSP_VAL ",Tcontrol_t ); |
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75 | ALLOC_SC_SIGNAL (out_ICACHE_RSP_ACK ,"out_ICACHE_RSP_ACK ",Tcontrol_t ); |
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76 | //ALLOC_SC_SIGNAL ( in_ICACHE_RSP_THREAD_ID ," in_ICACHE_RSP_THREAD_ID ",Tcontext_t ); |
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77 | ALLOC_SC_SIGNAL ( in_ICACHE_RSP_PACKET_ID ," in_ICACHE_RSP_PACKET_ID ",Tpacket_t ); |
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78 | ALLOC1_SC_SIGNAL( in_ICACHE_RSP_INSTRUCTION ," in_ICACHE_RSP_INSTRUCTION ",Ticache_instruction_t,_param->_nb_instruction); |
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79 | ALLOC_SC_SIGNAL ( in_ICACHE_RSP_ERROR ," in_ICACHE_RSP_ERROR ",Ticache_error_t ); |
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80 | ALLOC_SC_SIGNAL (out_PREDICT_VAL ,"out_PREDICT_VAL ",Tcontrol_t ); |
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81 | ALLOC_SC_SIGNAL ( in_PREDICT_ACK ," in_PREDICT_ACK ",Tcontrol_t ); |
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82 | ALLOC_SC_SIGNAL (out_PREDICT_PC_PREVIOUS ,"out_PREDICT_PC_PREVIOUS ",Tgeneral_address_t ); |
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83 | ALLOC_SC_SIGNAL (out_PREDICT_PC_CURRENT ,"out_PREDICT_PC_CURRENT ",Tgeneral_address_t ); |
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84 | ALLOC_SC_SIGNAL (out_PREDICT_PC_CURRENT_IS_DS_TAKE ,"out_PREDICT_PC_CURRENT_IS_DS_TAKE ",Tcontrol_t ); |
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85 | ALLOC_SC_SIGNAL ( in_PREDICT_PC_NEXT ," in_PREDICT_PC_NEXT ",Tgeneral_address_t ); |
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86 | ALLOC_SC_SIGNAL ( in_PREDICT_PC_NEXT_IS_DS_TAKE ," in_PREDICT_PC_NEXT_IS_DS_TAKE ",Tcontrol_t ); |
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87 | ALLOC1_SC_SIGNAL( in_PREDICT_INSTRUCTION_ENABLE ," in_PREDICT_INSTRUCTION_ENABLE ",Tcontrol_t ,_param->_nb_instruction); |
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88 | ALLOC_SC_SIGNAL ( in_PREDICT_INST_IFETCH_PTR ," in_PREDICT_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t ); |
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89 | ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_STATE ," in_PREDICT_BRANCH_STATE ",Tbranch_state_t ); |
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90 | ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID," in_PREDICT_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ); |
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91 | ALLOC1_SC_SIGNAL(out_DECOD_VAL ,"out_DECOD_VAL ",Tcontrol_t ,_param->_nb_instruction); |
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92 | ALLOC1_SC_SIGNAL( in_DECOD_ACK ," in_DECOD_ACK ",Tcontrol_t ,_param->_nb_instruction); |
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93 | ALLOC1_SC_SIGNAL(out_DECOD_INSTRUCTION ,"out_DECOD_INSTRUCTION ",Tinstruction_t ,_param->_nb_instruction); |
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94 | //ALLOC_SC_SIGNAL (out_DECOD_CONTEXT_ID ,"out_DECOD_CONTEXT_ID ",Tcontext_t ); |
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95 | ALLOC_SC_SIGNAL (out_DECOD_ADDRESS ,"out_DECOD_ADDRESS ",Tgeneral_address_t ); |
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96 | ALLOC_SC_SIGNAL (out_DECOD_INST_IFETCH_PTR ,"out_DECOD_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t ); |
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97 | ALLOC_SC_SIGNAL (out_DECOD_BRANCH_STATE ,"out_DECOD_BRANCH_STATE ",Tbranch_state_t ); |
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98 | ALLOC_SC_SIGNAL (out_DECOD_BRANCH_UPDATE_PREDICTION_ID ,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ); |
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99 | ALLOC_SC_SIGNAL (out_DECOD_EXCEPTION ,"out_DECOD_EXCEPTION ",Texception_t ); |
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100 | ALLOC_SC_SIGNAL ( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t ); |
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101 | ALLOC_SC_SIGNAL (out_EVENT_ACK ,"out_EVENT_ACK ",Tcontrol_t ); |
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102 | ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS ," in_EVENT_ADDRESS ",Tgeneral_address_t ); |
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103 | |
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104 | /******************************************************** |
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105 | * Instanciation |
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106 | ********************************************************/ |
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107 | |
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108 | msg(_("<%s> : Instanciation of _Ifetch_unit.\n"),name.c_str()); |
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109 | |
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110 | (*(_Ifetch_unit->in_CLOCK)) (*(in_CLOCK)); |
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111 | (*(_Ifetch_unit->in_NRESET)) (*(in_NRESET)); |
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112 | |
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113 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_ICACHE_REQ_VAL ); |
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114 | INSTANCE_SC_SIGNAL (_Ifetch_unit, in_ICACHE_REQ_ACK ); |
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115 | //INSTANCE_SC_SIGNAL (_Ifetch_unit,out_ICACHE_REQ_THREAD_ID ); |
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116 | if (_param->_have_port_queue_ptr) |
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117 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_ICACHE_REQ_PACKET_ID ); |
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118 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_ICACHE_REQ_ADDRESS ); |
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119 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_ICACHE_REQ_TYPE ); |
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120 | INSTANCE_SC_SIGNAL (_Ifetch_unit, in_ICACHE_RSP_VAL ); |
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121 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_ICACHE_RSP_ACK ); |
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122 | //INSTANCE_SC_SIGNAL (_Ifetch_unit, in_ICACHE_RSP_THREAD_ID ); |
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123 | if (_param->_have_port_queue_ptr) |
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124 | INSTANCE_SC_SIGNAL (_Ifetch_unit, in_ICACHE_RSP_PACKET_ID ); |
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125 | INSTANCE1_SC_SIGNAL(_Ifetch_unit, in_ICACHE_RSP_INSTRUCTION ,_param->_nb_instruction); |
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126 | INSTANCE_SC_SIGNAL (_Ifetch_unit, in_ICACHE_RSP_ERROR ); |
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127 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_PREDICT_VAL ); |
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128 | INSTANCE_SC_SIGNAL (_Ifetch_unit, in_PREDICT_ACK ); |
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129 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_PREDICT_PC_PREVIOUS ); |
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130 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_PREDICT_PC_CURRENT ); |
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131 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_PREDICT_PC_CURRENT_IS_DS_TAKE ); |
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132 | INSTANCE_SC_SIGNAL (_Ifetch_unit, in_PREDICT_PC_NEXT ); |
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133 | INSTANCE_SC_SIGNAL (_Ifetch_unit, in_PREDICT_PC_NEXT_IS_DS_TAKE ); |
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134 | INSTANCE1_SC_SIGNAL(_Ifetch_unit, in_PREDICT_INSTRUCTION_ENABLE ,_param->_nb_instruction); |
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135 | if (_param->_have_port_instruction_ptr) |
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136 | INSTANCE_SC_SIGNAL (_Ifetch_unit, in_PREDICT_INST_IFETCH_PTR ); |
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137 | INSTANCE_SC_SIGNAL (_Ifetch_unit, in_PREDICT_BRANCH_STATE ); |
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138 | if (_param->_have_port_branch_update_prediction_id) |
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139 | INSTANCE_SC_SIGNAL (_Ifetch_unit, in_PREDICT_BRANCH_UPDATE_PREDICTION_ID); |
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140 | INSTANCE1_SC_SIGNAL(_Ifetch_unit,out_DECOD_VAL ,_param->_nb_instruction); |
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141 | INSTANCE1_SC_SIGNAL(_Ifetch_unit, in_DECOD_ACK ,_param->_nb_instruction); |
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142 | INSTANCE1_SC_SIGNAL(_Ifetch_unit,out_DECOD_INSTRUCTION ,_param->_nb_instruction); |
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143 | //INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_CONTEXT_ID ); |
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144 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_ADDRESS ); |
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145 | if (_param->_have_port_instruction_ptr) |
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146 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_INST_IFETCH_PTR ); |
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147 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_BRANCH_STATE ); |
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148 | if (_param->_have_port_branch_update_prediction_id) |
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149 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_BRANCH_UPDATE_PREDICTION_ID ); |
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150 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_EXCEPTION ); |
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151 | INSTANCE_SC_SIGNAL (_Ifetch_unit, in_EVENT_VAL ); |
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152 | INSTANCE_SC_SIGNAL (_Ifetch_unit,out_EVENT_ACK ); |
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153 | INSTANCE_SC_SIGNAL (_Ifetch_unit, in_EVENT_ADDRESS ); |
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154 | |
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155 | msg(_("<%s> : Start Simulation ............\n"),name.c_str()); |
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156 | |
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157 | Time * _time = new Time(); |
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158 | |
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159 | /******************************************************** |
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160 | * Simulation - Begin |
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161 | ********************************************************/ |
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162 | |
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163 | // Initialisation |
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164 | |
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165 | const uint32_t seed = 0; |
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166 | //const uint32_t seed = static_cast<uint32_t>(time(NULL)); |
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167 | |
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168 | srand(seed); |
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169 | |
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170 | SC_START(0); |
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171 | LABEL("Initialisation"); |
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172 | |
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173 | LABEL("Reset"); |
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174 | in_NRESET->write(0); |
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175 | SC_START(5); |
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176 | in_NRESET->write(1); |
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177 | |
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178 | LABEL("Loop of Test"); |
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179 | |
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180 | for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) |
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181 | { |
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182 | LABEL("Iteration %d",iteration); |
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183 | |
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184 | SC_START(100); |
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185 | } |
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186 | |
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187 | /******************************************************** |
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188 | * Simulation - End |
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189 | ********************************************************/ |
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190 | |
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191 | TEST_OK ("End of Simulation"); |
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192 | delete _time; |
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193 | |
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194 | msg(_("<%s> : ............ Stop Simulation\n"),name.c_str()); |
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195 | |
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196 | delete in_CLOCK; |
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197 | delete in_NRESET; |
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198 | |
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199 | delete out_ICACHE_REQ_VAL ; |
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200 | delete in_ICACHE_REQ_ACK ; |
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201 | //delete out_ICACHE_REQ_THREAD_ID ; |
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202 | delete out_ICACHE_REQ_PACKET_ID ; |
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203 | delete out_ICACHE_REQ_ADDRESS ; |
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204 | delete out_ICACHE_REQ_TYPE ; |
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205 | |
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206 | delete in_ICACHE_RSP_VAL ; |
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207 | delete out_ICACHE_RSP_ACK ; |
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208 | //delete in_ICACHE_RSP_THREAD_ID ; |
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209 | delete in_ICACHE_RSP_PACKET_ID ; |
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210 | delete [] in_ICACHE_RSP_INSTRUCTION ; |
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211 | delete in_ICACHE_RSP_ERROR ; |
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212 | |
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213 | delete out_PREDICT_VAL ; |
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214 | delete in_PREDICT_ACK ; |
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215 | delete out_PREDICT_PC_PREVIOUS ; |
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216 | delete out_PREDICT_PC_CURRENT ; |
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217 | delete out_PREDICT_PC_CURRENT_IS_DS_TAKE ; |
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218 | delete in_PREDICT_PC_NEXT ; |
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219 | delete in_PREDICT_PC_NEXT_IS_DS_TAKE ; |
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220 | delete [] in_PREDICT_INSTRUCTION_ENABLE ; |
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221 | delete in_PREDICT_INST_IFETCH_PTR ; |
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222 | delete in_PREDICT_BRANCH_STATE ; |
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223 | delete in_PREDICT_BRANCH_UPDATE_PREDICTION_ID ; |
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224 | |
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225 | delete [] out_DECOD_VAL ; |
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226 | delete [] in_DECOD_ACK ; |
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227 | delete [] out_DECOD_INSTRUCTION ; |
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228 | //delete out_DECOD_CONTEXT_ID ; |
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229 | delete out_DECOD_ADDRESS ; |
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230 | delete out_DECOD_INST_IFETCH_PTR ; |
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231 | delete out_DECOD_BRANCH_STATE ; |
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232 | delete out_DECOD_BRANCH_UPDATE_PREDICTION_ID ; |
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233 | delete out_DECOD_EXCEPTION ; |
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234 | |
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235 | delete in_EVENT_VAL ; |
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236 | delete out_EVENT_ACK ; |
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237 | delete in_EVENT_ADDRESS ; |
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238 | #endif |
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239 | |
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240 | delete _Ifetch_unit; |
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241 | #ifdef STATISTICS |
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242 | delete _parameters_statistics; |
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243 | #endif |
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244 | } |
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