[78] | 1 | /* |
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| 2 | * $Id: Ifetch_unit_allocation.cpp 112 2009-03-18 22:36:26Z rosiere $ |
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| 3 | * |
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| 4 | * [ Description ] |
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| 5 | * |
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| 6 | */ |
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| 7 | |
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| 8 | #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/include/Ifetch_unit.h" |
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| 9 | #include "Behavioural/include/Allocation.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_front_end { |
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| 15 | namespace front_end { |
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| 16 | namespace ifetch_unit { |
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| 17 | |
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| 18 | |
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| 19 | |
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| 20 | #undef FUNCTION |
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| 21 | #define FUNCTION "Ifetch_unit::allocation" |
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| 22 | void Ifetch_unit::allocation ( |
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| 23 | #ifdef STATISTICS |
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| 24 | morpheo::behavioural::Parameters_Statistics * param_statistics |
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| 25 | #else |
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| 26 | void |
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| 27 | #endif |
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| 28 | ) |
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| 29 | { |
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| 30 | log_printf(FUNC,Ifetch_unit,FUNCTION,"Begin"); |
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| 31 | |
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| 32 | _component = new Component (_usage); |
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| 33 | |
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| 34 | Entity * entity = _component->set_entity (_name |
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| 35 | ,"Ifetch_unit" |
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| 36 | #ifdef POSITION |
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| 37 | ,COMBINATORY |
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| 38 | #endif |
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| 39 | ); |
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| 40 | |
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| 41 | _interfaces = entity->set_interfaces(); |
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| 42 | |
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| 43 | // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 44 | { |
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| 45 | Interface * interface = _interfaces->set_interface("" |
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| 46 | #ifdef POSITION |
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| 47 | ,IN |
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| 48 | ,SOUTH, |
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[112] | 49 | _("Generalist interface") |
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[78] | 50 | #endif |
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| 51 | ); |
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| 52 | |
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| 53 | in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES); |
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| 54 | in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, RESET_VHDL_YES); |
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| 55 | } |
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| 56 | |
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| 57 | // ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 58 | { |
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[112] | 59 | ALLOC0_INTERFACE_BEGIN("icache_req",OUT, WEST, _("Instruction cache request.")); |
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[78] | 60 | |
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[112] | 61 | ALLOC0_VALACK_OUT(out_ICACHE_REQ_VAL ,VAL); |
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| 62 | ALLOC0_VALACK_IN ( in_ICACHE_REQ_ACK ,ACK); |
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| 63 | //ALLOC0_SIGNAL_OUT(out_ICACHE_REQ_THREAD_ID,"thread_id",Tcontext_t ,_param->_size_context_id ); |
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| 64 | ALLOC0_SIGNAL_OUT(out_ICACHE_REQ_PACKET_ID,"packet_id",Tpacket_t ,_param->_size_ifetch_queue_ptr ); |
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| 65 | ALLOC0_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS ,"address" ,Ticache_instruction_t,_param->_size_instruction_address ); |
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| 66 | ALLOC0_SIGNAL_OUT(out_ICACHE_REQ_TYPE ,"type" ,Ticache_type_t ,_param->_size_icache_type); |
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| 67 | |
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| 68 | ALLOC0_INTERFACE_END(); |
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[78] | 69 | } |
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| 70 | |
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| 71 | // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 72 | { |
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[112] | 73 | ALLOC0_INTERFACE_BEGIN("icache_rsp",IN , WEST, _("Instruction cache respons.")); |
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[78] | 74 | |
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[112] | 75 | ALLOC0_VALACK_IN ( in_ICACHE_RSP_VAL ,VAL); |
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| 76 | ALLOC0_VALACK_OUT (out_ICACHE_RSP_ACK ,ACK); |
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| 77 | //ALLOC0_SIGNAL_IN ( in_ICACHE_RSP_THREAD_ID ,"thread_id" ,Tcontext_t ,_param->_size_context_id ); |
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| 78 | ALLOC0_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_ifetch_queue_ptr ); |
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| 79 | ALLOC0_SIGNAL_IN ( in_ICACHE_RSP_ERROR ,"error" ,Ticache_error_t ,_param->_size_icache_error); |
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| 80 | |
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| 81 | ALLOC0_INTERFACE_END(); |
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[78] | 82 | } |
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| 83 | { |
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[112] | 84 | ALLOC1_INTERFACE_BEGIN("icache_rsp",IN , WEST, _("Instruction cache respons."),_param->_nb_instruction); |
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[78] | 85 | |
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| 86 | ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_INSTRUCTION,"instruction",Ticache_instruction_t,_param->_size_instruction ); |
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[112] | 87 | |
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| 88 | ALLOC1_INTERFACE_END(_param->_nb_instruction); |
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[78] | 89 | } |
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| 90 | |
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| 91 | // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 92 | { |
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[112] | 93 | ALLOC0_INTERFACE_BEGIN("predict",OUT, NORTH, _("Predict the next pc.")); |
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[78] | 94 | |
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[112] | 95 | ALLOC0_VALACK_OUT (out_PREDICT_VAL ,VAL); |
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| 96 | ALLOC0_VALACK_IN ( in_PREDICT_ACK ,ACK); |
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| 97 | ALLOC0_SIGNAL_OUT (out_PREDICT_PC_PREVIOUS ,"pc_previous" ,Tgeneral_address_t,_param->_size_instruction_address); |
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| 98 | ALLOC0_SIGNAL_OUT (out_PREDICT_PC_CURRENT ,"pc_current" ,Tgeneral_address_t,_param->_size_instruction_address); |
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| 99 | ALLOC0_SIGNAL_OUT (out_PREDICT_PC_CURRENT_IS_DS_TAKE ,"pc_current_is_ds_take" ,Tcontrol_t ,1); |
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| 100 | ALLOC0_SIGNAL_IN ( in_PREDICT_PC_NEXT ,"pc_next" ,Tgeneral_address_t,_param->_size_instruction_address); |
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| 101 | ALLOC0_SIGNAL_IN ( in_PREDICT_PC_NEXT_IS_DS_TAKE ,"pc_next_is_ds_take" ,Tcontrol_t ,1); |
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| 102 | ALLOC0_SIGNAL_IN ( in_PREDICT_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr); |
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| 103 | ALLOC0_SIGNAL_IN ( in_PREDICT_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state); |
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| 104 | ALLOC0_SIGNAL_IN ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth); |
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| 105 | |
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| 106 | ALLOC0_INTERFACE_END(); |
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[78] | 107 | } |
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| 108 | { |
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[112] | 109 | ALLOC1_INTERFACE_BEGIN("predict",IN , NORTH, _("Predict the next pc."),_param->_nb_instruction); |
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[78] | 110 | |
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| 111 | ALLOC1_SIGNAL_IN ( in_PREDICT_INSTRUCTION_ENABLE ,"instruction_enable" ,Tcontrol_t ,1); |
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[112] | 112 | |
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| 113 | ALLOC1_INTERFACE_END(_param->_nb_instruction); |
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[78] | 114 | } |
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| 115 | |
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| 116 | // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 117 | { |
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[112] | 118 | ALLOC0_INTERFACE_BEGIN("decod",OUT , EAST, _("Send bundle to the decod unit.")); |
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[78] | 119 | |
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[112] | 120 | //ALLOC0_SIGNAL_OUT (out_DECOD_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); |
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| 121 | ALLOC0_SIGNAL_OUT (out_DECOD_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_instruction_address); |
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| 122 | ALLOC0_SIGNAL_OUT (out_DECOD_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr); |
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| 123 | ALLOC0_SIGNAL_OUT (out_DECOD_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state); |
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| 124 | ALLOC0_SIGNAL_OUT (out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth); |
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| 125 | ALLOC0_SIGNAL_OUT (out_DECOD_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_ifetch); |
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| 126 | |
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| 127 | ALLOC0_INTERFACE_END(); |
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[78] | 128 | } |
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| 129 | { |
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[112] | 130 | ALLOC1_INTERFACE_BEGIN("decod",OUT , EAST, _("Send bundle to the decod unit."),_param->_nb_instruction); |
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[78] | 131 | |
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| 132 | ALLOC1_VALACK_OUT(out_DECOD_VAL ,VAL); |
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| 133 | ALLOC1_VALACK_IN ( in_DECOD_ACK ,ACK); |
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| 134 | ALLOC1_SIGNAL_OUT(out_DECOD_INSTRUCTION ,"instruction" ,Tinstruction_t ,_param->_size_instruction); |
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[112] | 135 | |
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| 136 | ALLOC1_INTERFACE_END(_param->_nb_instruction); |
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[78] | 137 | } |
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| 138 | |
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| 139 | // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 140 | { |
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[112] | 141 | ALLOC0_INTERFACE_BEGIN("event",IN , NORTH, _("Event interface.")); |
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[78] | 142 | |
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[112] | 143 | ALLOC0_VALACK_IN ( in_EVENT_VAL ,VAL); |
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| 144 | ALLOC0_VALACK_OUT(out_EVENT_ACK ,ACK); |
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| 145 | ALLOC0_SIGNAL_IN ( in_EVENT_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_instruction_address); |
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| 146 | ALLOC0_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT ,"address_next" ,Tgeneral_address_t,_param->_size_instruction_address); |
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| 147 | ALLOC0_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT_VAL ,"address_next_val",Tcontrol_t,1); |
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| 148 | ALLOC0_SIGNAL_IN ( in_EVENT_IS_DS_TAKE ,"is_ds_take" ,Tcontrol_t,1); |
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| 149 | |
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| 150 | ALLOC0_INTERFACE_END(); |
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[78] | 151 | } |
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| 152 | |
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| 153 | // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 154 | std::string name; |
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| 155 | |
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| 156 | { |
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| 157 | name = _name+"_address_management"; |
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[88] | 158 | log_printf(Ifetch_unit,Core,FUNCTION,_("Create : %s"),name.c_str()); |
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[78] | 159 | |
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| 160 | _component_address_management = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::address_management::Address_management |
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| 161 | (name.c_str() |
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| 162 | #ifdef STATISTICS |
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| 163 | ,param_statistics |
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| 164 | #endif |
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[82] | 165 | ,_param->_param_address_management |
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| 166 | ,_usage); |
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[78] | 167 | |
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| 168 | _component->set_component (_component_address_management->_component |
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| 169 | #ifdef POSITION |
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| 170 | , 50, 50, 10, 10 |
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| 171 | #endif |
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| 172 | ); |
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| 173 | } |
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| 174 | |
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| 175 | { |
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| 176 | name = _name+"_ifetch_queue"; |
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[88] | 177 | log_printf(Ifetch_unit,Core,FUNCTION,_("Create : %s"),name.c_str()); |
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[78] | 178 | |
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| 179 | _component_ifetch_queue = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::Ifetch_queue |
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| 180 | (name.c_str() |
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| 181 | #ifdef STATISTICS |
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| 182 | ,param_statistics |
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| 183 | #endif |
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[82] | 184 | ,_param->_param_ifetch_queue |
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| 185 | ,_usage); |
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[78] | 186 | |
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| 187 | _component->set_component (_component_ifetch_queue->_component |
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| 188 | #ifdef POSITION |
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| 189 | , 50, 50, 10, 10 |
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| 190 | #endif |
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| 191 | ); |
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| 192 | } |
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| 193 | |
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| 194 | { |
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| 195 | name = _name+"_ifetch_unit_glue"; |
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[88] | 196 | log_printf(Ifetch_unit,Core,FUNCTION,_("Create : %s"),name.c_str()); |
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[78] | 197 | |
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| 198 | _component_ifetch_unit_glue = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_unit_glue::Ifetch_unit_Glue |
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| 199 | (name.c_str() |
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| 200 | #ifdef STATISTICS |
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| 201 | ,param_statistics |
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| 202 | #endif |
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[82] | 203 | ,_param->_param_ifetch_unit_glue |
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| 204 | ,_usage); |
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[78] | 205 | |
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| 206 | _component->set_component (_component_ifetch_unit_glue->_component |
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| 207 | #ifdef POSITION |
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| 208 | , 50, 50, 10, 10 |
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| 209 | #endif |
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| 210 | ); |
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| 211 | } |
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| 212 | |
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| 213 | // ~~~~~[ Instanciation ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 214 | std::string src,dest; |
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| 215 | |
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| 216 | // =================================================================== |
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| 217 | // =====[ address_management ]======================================== |
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| 218 | // =================================================================== |
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| 219 | { |
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| 220 | src = _name+"_address_management"; |
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[88] | 221 | log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str()); |
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[78] | 222 | |
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| 223 | { |
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| 224 | dest = _name; |
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| 225 | #ifdef POSITION |
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| 226 | _component->interface_map (src ,"", |
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| 227 | dest,""); |
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| 228 | #endif |
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| 229 | PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK"); |
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| 230 | PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET"); |
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| 231 | } |
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| 232 | |
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| 233 | { |
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[85] | 234 | dest = _name+"_ifetch_queue"; |
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[78] | 235 | |
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| 236 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 237 | { |
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| 238 | #ifdef POSITION |
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[85] | 239 | _component->interface_map (src ,"address_"+toString(i), |
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| 240 | dest,"address_"+toString(i)); |
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[78] | 241 | #endif |
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[85] | 242 | COMPONENT_MAP(_component,src ,"out_ADDRESS_"+toString(i)+"_INSTRUCTION_ENABLE", |
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| 243 | dest, "in_ADDRESS_"+toString(i)+"_INSTRUCTION_ENABLE"); |
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[78] | 244 | } |
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| 245 | |
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[88] | 246 | if (_param->_have_port_inst_ifetch_ptr) |
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[85] | 247 | COMPONENT_MAP(_component,src ,"out_ADDRESS_INST_IFETCH_PTR" , |
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| 248 | dest, "in_ADDRESS_INST_IFETCH_PTR" ); |
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| 249 | COMPONENT_MAP(_component,src ,"out_ADDRESS_BRANCH_STATE" , |
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| 250 | dest, "in_ADDRESS_BRANCH_STATE" ); |
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[88] | 251 | if (_param->_have_port_depth) |
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[85] | 252 | COMPONENT_MAP(_component,src ,"out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID", |
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| 253 | dest, "in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID"); |
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| 254 | |
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| 255 | dest = _name+"_ifetch_unit_glue"; |
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| 256 | |
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| 257 | #ifdef POSITION |
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| 258 | _component->interface_map (src ,"address", |
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| 259 | dest,"address"); |
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| 260 | #endif |
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| 261 | |
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| 262 | COMPONENT_MAP(_component,src ,"out_ADDRESS_VAL" , |
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| 263 | dest, "in_ICACHE_REQ_ADDRESS_VAL"); |
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| 264 | COMPONENT_MAP(_component,src , "in_ADDRESS_ACK" , |
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| 265 | dest,"out_ICACHE_REQ_ADDRESS_ACK"); |
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| 266 | COMPONENT_MAP(_component,src ,"out_ADDRESS_INSTRUCTION_ADDRESS", |
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| 267 | dest, "in_ICACHE_REQ_ADDRESS_ADDRESS"); |
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[78] | 268 | } |
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| 269 | |
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| 270 | { |
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| 271 | dest = _name; |
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| 272 | |
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| 273 | #ifdef POSITION |
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| 274 | _component->interface_map (src ,"predict", |
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| 275 | dest,"predict"); |
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| 276 | #endif |
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| 277 | |
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| 278 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 279 | { |
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| 280 | #ifdef POSITION |
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| 281 | _component->interface_map (src ,"predict_"+toString(i), |
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| 282 | dest,"predict_"+toString(i)); |
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| 283 | #endif |
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| 284 | PORT_MAP(_component,src , "in_PREDICT_"+toString(i)+"_INSTRUCTION_ENABLE" |
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| 285 | ,dest, "in_PREDICT_"+toString(i)+"_INSTRUCTION_ENABLE" ); |
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| 286 | } |
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| 287 | |
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| 288 | PORT_MAP(_component,src ,"out_PREDICT_VAL" |
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| 289 | ,dest,"out_PREDICT_VAL" ); |
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| 290 | PORT_MAP(_component,src , "in_PREDICT_ACK" |
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| 291 | ,dest, "in_PREDICT_ACK" ); |
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| 292 | PORT_MAP(_component,src ,"out_PREDICT_PC_PREVIOUS" |
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| 293 | ,dest,"out_PREDICT_PC_PREVIOUS" ); |
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| 294 | PORT_MAP(_component,src ,"out_PREDICT_PC_CURRENT" |
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| 295 | ,dest,"out_PREDICT_PC_CURRENT" ); |
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| 296 | PORT_MAP(_component,src ,"out_PREDICT_PC_CURRENT_IS_DS_TAKE" |
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| 297 | ,dest,"out_PREDICT_PC_CURRENT_IS_DS_TAKE" ); |
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| 298 | PORT_MAP(_component,src , "in_PREDICT_PC_NEXT" |
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| 299 | ,dest, "in_PREDICT_PC_NEXT" ); |
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| 300 | PORT_MAP(_component,src , "in_PREDICT_PC_NEXT_IS_DS_TAKE" |
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| 301 | ,dest, "in_PREDICT_PC_NEXT_IS_DS_TAKE" ); |
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[88] | 302 | if (_param->_have_port_inst_ifetch_ptr) |
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[78] | 303 | PORT_MAP(_component,src , "in_PREDICT_INST_IFETCH_PTR" |
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| 304 | ,dest, "in_PREDICT_INST_IFETCH_PTR" ); |
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| 305 | PORT_MAP(_component,src , "in_PREDICT_BRANCH_STATE" |
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| 306 | ,dest, "in_PREDICT_BRANCH_STATE" ); |
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[88] | 307 | if (_param->_have_port_depth) |
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[78] | 308 | PORT_MAP(_component,src , "in_PREDICT_BRANCH_UPDATE_PREDICTION_ID" |
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| 309 | ,dest, "in_PREDICT_BRANCH_UPDATE_PREDICTION_ID"); |
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| 310 | } |
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| 311 | |
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| 312 | { |
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| 313 | dest = _name+"_ifetch_unit_glue"; |
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| 314 | |
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| 315 | #ifdef POSITION |
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| 316 | _component->interface_map (src ,"event", |
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| 317 | dest,"event"); |
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| 318 | _component->interface_map (src ,"event", |
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| 319 | _name,"event"); |
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| 320 | #endif |
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| 321 | |
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[85] | 322 | COMPONENT_MAP(_component,src , "in_EVENT_VAL" ,dest ,"out_EVENT_ADDRESS_VAL"); |
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| 323 | COMPONENT_MAP(_component,src ,"out_EVENT_ACK" ,dest , "in_EVENT_ADDRESS_ACK"); |
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| 324 | |
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| 325 | |
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| 326 | dest = _name; |
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[88] | 327 | PORT_MAP(_component,src , "in_EVENT_ADDRESS" ,dest , "in_EVENT_ADDRESS" ); |
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| 328 | PORT_MAP(_component,src , "in_EVENT_ADDRESS_NEXT" ,dest , "in_EVENT_ADDRESS_NEXT" ); |
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| 329 | PORT_MAP(_component,src , "in_EVENT_ADDRESS_NEXT_VAL",dest , "in_EVENT_ADDRESS_NEXT_VAL" ); |
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| 330 | PORT_MAP(_component,src , "in_EVENT_IS_DS_TAKE" ,dest , "in_EVENT_IS_DS_TAKE" ); |
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[78] | 331 | } |
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| 332 | } |
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| 333 | |
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| 334 | // =================================================================== |
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| 335 | // =====[ ifetch_queue ]============================================== |
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| 336 | // =================================================================== |
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| 337 | { |
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| 338 | src = _name+"_ifetch_queue"; |
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[88] | 339 | log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str()); |
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[78] | 340 | |
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| 341 | { |
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| 342 | dest = _name; |
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| 343 | #ifdef POSITION |
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| 344 | _component->interface_map (src ,"", |
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| 345 | dest,""); |
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| 346 | #endif |
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| 347 | PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK"); |
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| 348 | PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET"); |
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| 349 | } |
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| 350 | |
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| 351 | { |
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| 352 | dest = _name; |
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| 353 | |
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| 354 | #ifdef POSITION |
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| 355 | _component->interface_map (src ,"address", |
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| 356 | dest,"address"); |
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| 357 | #endif |
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| 358 | |
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[88] | 359 | if (_param->_have_port_ifetch_queue_ptr) |
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[85] | 360 | PORT_MAP(_component,src ,"out_ADDRESS_IFETCH_QUEUE_ID" , |
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| 361 | dest,"out_ICACHE_REQ_PACKET_ID" ); |
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| 362 | |
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[78] | 363 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 364 | { |
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| 365 | #ifdef POSITION |
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| 366 | _component->interface_map (src ,"address_"+toString(i), |
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| 367 | dest+"_address_management","address_"+toString(i)); |
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| 368 | #endif |
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[85] | 369 | |
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| 370 | //out_ADDRESS_INSTRUCTION_ENABLE - address_management |
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[78] | 371 | } |
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| 372 | |
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[85] | 373 | dest = _name+"_ifetch_unit_glue"; |
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| 374 | |
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| 375 | COMPONENT_MAP(_component,src , "in_ADDRESS_VAL" , |
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| 376 | dest,"out_ICACHE_REQ_QUEUE_VAL"); |
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| 377 | COMPONENT_MAP(_component,src ,"out_ADDRESS_ACK" , |
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| 378 | dest, "in_ICACHE_REQ_QUEUE_ACK"); |
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| 379 | COMPONENT_MAP(_component,src , "in_ADDRESS_INSTRUCTION_ADDRESS", |
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| 380 | dest,"out_ICACHE_REQ_QUEUE_ADDRESS"); |
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| 381 | // in_ADDRESS_INST_IFETCH_PTR - address_management |
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| 382 | // in_ADDRESS_BRANCH_STATE - address_management |
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| 383 | // in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID - address_management |
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[78] | 384 | } |
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| 385 | |
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| 386 | { |
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| 387 | dest = _name; |
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| 388 | |
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| 389 | #ifdef POSITION |
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| 390 | _component->interface_map (src ,"icache_rsp", |
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| 391 | dest,"icache_rsp"); |
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| 392 | #endif |
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| 393 | |
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| 394 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 395 | { |
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| 396 | #ifdef POSITION |
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| 397 | _component->interface_map (src ,"icache_rsp_"+toString(i), |
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| 398 | dest,"icache_rsp_"+toString(i)); |
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| 399 | #endif |
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| 400 | |
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| 401 | PORT_MAP(_component,src ,"out_DECOD_"+toString(i)+"_VAL" , |
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| 402 | dest,"out_DECOD_"+toString(i)+"_VAL" ); |
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| 403 | PORT_MAP(_component,src , "in_DECOD_"+toString(i)+"_ACK" , |
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| 404 | dest, "in_DECOD_"+toString(i)+"_ACK" ); |
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| 405 | PORT_MAP(_component,src ,"out_DECOD_"+toString(i)+"_INSTRUCTION" , |
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| 406 | dest,"out_DECOD_"+toString(i)+"_INSTRUCTION" ); |
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| 407 | } |
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| 408 | |
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| 409 | PORT_MAP(_component,src ,"out_DECOD_ADDRESS" ,dest,"out_DECOD_ADDRESS" ); |
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[88] | 410 | if (_param->_have_port_inst_ifetch_ptr) |
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[78] | 411 | PORT_MAP(_component,src ,"out_DECOD_INST_IFETCH_PTR" ,dest,"out_DECOD_INST_IFETCH_PTR" ); |
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| 412 | PORT_MAP(_component,src ,"out_DECOD_BRANCH_STATE" ,dest,"out_DECOD_BRANCH_STATE" ); |
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[88] | 413 | if (_param->_have_port_depth) |
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[78] | 414 | PORT_MAP(_component,src ,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID",dest,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID"); |
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| 415 | PORT_MAP(_component,src ,"out_DECOD_EXCEPTION" ,dest,"out_DECOD_EXCEPTION" ); |
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| 416 | } |
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| 417 | |
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| 418 | { |
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| 419 | dest = _name; |
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| 420 | |
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| 421 | #ifdef POSITION |
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| 422 | _component->interface_map (src ,"icache_rsp", |
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| 423 | dest,"icache_rsp"); |
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| 424 | #endif |
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| 425 | |
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| 426 | PORT_MAP(_component,src , "in_ICACHE_RSP_VAL" ,dest, "in_ICACHE_RSP_VAL" ); |
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| 427 | PORT_MAP(_component,src ,"out_ICACHE_RSP_ACK" ,dest,"out_ICACHE_RSP_ACK" ); |
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[88] | 428 | if (_param->_have_port_ifetch_queue_ptr) |
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[78] | 429 | PORT_MAP(_component,src , "in_ICACHE_RSP_PACKET_ID",dest, "in_ICACHE_RSP_PACKET_ID"); |
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| 430 | PORT_MAP(_component,src , "in_ICACHE_RSP_ERROR" ,dest, "in_ICACHE_RSP_ERROR" ); |
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| 431 | |
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| 432 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 433 | { |
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| 434 | #ifdef POSITION |
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| 435 | _component->interface_map (src ,"icache_rsp_"+toString(i), |
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| 436 | dest,"icache_rsp_"+toString(i)); |
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| 437 | #endif |
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| 438 | PORT_MAP(_component,src , "in_ICACHE_RSP_"+toString(i)+"_INSTRUCTION", |
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| 439 | dest, "in_ICACHE_RSP_"+toString(i)+"_INSTRUCTION"); |
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| 440 | } |
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| 441 | } |
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| 442 | |
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| 443 | { |
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| 444 | dest = _name+"_ifetch_unit_glue"; |
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| 445 | |
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| 446 | #ifdef POSITION |
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| 447 | _component->interface_map (src ,"event_reset", |
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| 448 | dest,"event"); |
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| 449 | #endif |
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| 450 | |
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[85] | 451 | COMPONENT_MAP(_component,src , "in_EVENT_RESET_VAL",dest,"out_EVENT_QUEUE_VAL"); |
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| 452 | COMPONENT_MAP(_component,src ,"out_EVENT_RESET_ACK",dest, "in_EVENT_QUEUE_ACK"); |
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[78] | 453 | } |
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| 454 | } |
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| 455 | |
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| 456 | // =================================================================== |
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| 457 | // =====[ ifetch_unit_glue ]========================================== |
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| 458 | // =================================================================== |
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| 459 | { |
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| 460 | src = _name+"_ifetch_unit_glue"; |
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[88] | 461 | log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str()); |
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[78] | 462 | |
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| 463 | { |
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| 464 | dest = _name; |
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| 465 | #ifdef POSITION |
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| 466 | _component->interface_map (src ,"", |
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| 467 | dest,""); |
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| 468 | #endif |
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| 469 | PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK"); |
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| 470 | PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET"); |
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| 471 | } |
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| 472 | |
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| 473 | { |
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| 474 | dest = _name; |
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| 475 | |
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| 476 | #ifdef POSITION |
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| 477 | _component->interface_map (src ,"icache_req", |
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| 478 | dest,"icache_req"); |
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| 479 | #endif |
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| 480 | |
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[85] | 481 | PORT_MAP(_component,src ,"out_ICACHE_REQ_VAL" ,dest,"out_ICACHE_REQ_VAL"); |
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| 482 | PORT_MAP(_component,src , "in_ICACHE_REQ_ACK" ,dest, "in_ICACHE_REQ_ACK"); |
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| 483 | PORT_MAP(_component,src ,"out_ICACHE_REQ_TYPE" ,dest,"out_ICACHE_REQ_TYPE"); |
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| 484 | PORT_MAP(_component,src ,"out_ICACHE_REQ_ADDRESS",dest,"out_ICACHE_REQ_ADDRESS"); |
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| 485 | |
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| 486 | // in_ICACHE_REQ_ADDRESS_VAL - address_management |
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| 487 | //out_ICACHE_REQ_QUEUE_VAL - ifetch_queue |
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| 488 | //out_ICACHE_REQ_ADDRESS_ACK - address_management |
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| 489 | // in_ICACHE_REQ_QUEUE_ACK - ifetch_queue |
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| 490 | // in_ICACHE_REQ_ADDRESS_ADDRESS - address_management |
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| 491 | //out_ICACHE_REQ_QUEUE_ADDRESS - ifetch_queue |
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| 492 | |
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[78] | 493 | } |
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| 494 | |
---|
| 495 | { |
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| 496 | dest = _name; |
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| 497 | |
---|
| 498 | #ifdef POSITION |
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| 499 | _component->interface_map (src ,"event", |
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| 500 | dest,"event"); |
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| 501 | #endif |
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| 502 | |
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| 503 | PORT_MAP(_component,src , "in_EVENT_VAL" ,dest , "in_EVENT_VAL" ); |
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| 504 | PORT_MAP(_component,src ,"out_EVENT_ACK" ,dest ,"out_EVENT_ACK" ); |
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[85] | 505 | |
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| 506 | //out_EVENT_ADDRESS_VAL - address_management |
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| 507 | //out_EVENT_QUEUE_VAL - ifetch_queue |
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| 508 | // in_EVENT_ADDRESS_ACK - address_management |
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| 509 | // in_EVENT_QUEUE_ACK - ifetch_queue |
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[78] | 510 | } |
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| 511 | } |
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| 512 | |
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| 513 | // ~~~~~[ Others ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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[88] | 514 | #if DEBUG_Ifetch_unit == true |
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| 515 | _component->test_map(); |
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| 516 | #endif |
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| 517 | |
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[78] | 518 | #ifdef POSITION |
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[88] | 519 | if (usage_is_set(_usage,USE_POSITION)) |
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| 520 | _component->generate_file(); |
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[78] | 521 | #endif |
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| 522 | |
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| 523 | log_printf(FUNC,Ifetch_unit,FUNCTION,"End"); |
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| 524 | }; |
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| 525 | |
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| 526 | }; // end namespace ifetch_unit |
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| 527 | }; // end namespace front_end |
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| 528 | }; // end namespace multi_front_end |
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| 529 | }; // end namespace core |
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| 530 | |
---|
| 531 | }; // end namespace behavioural |
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| 532 | }; // end namespace morpheo |
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