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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_allocation.cpp @ 112

Last change on this file since 112 was 112, checked in by rosiere, 15 years ago
1) Stat_list : fix retire old and new register bug 2) Stat_list : remove read_counter and valid flag, because validation of destination is in retire step (not in commit step) 3) Model : add class Model (cf Morpheo.sim) 4) Allocation : alloc_interface_begin and alloc_interface_end to delete temporary array. 5) Script : add distexe.sh 6) Add Comparator, Multiplier, Divider. But this component are not implemented 7) Software : add Dhrystone
Property svn:keywords set to `Id`
File size: 19.7 KB

Line
1	/*
2	* $Id: Ifetch_unit_allocation.cpp 112 2009-03-18 22:36:26Z rosiere $
3	*
4	* [ Description ]
5	*
6	*/
7
8	#include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/include/Ifetch_unit.h"
9	#include "Behavioural/include/Allocation.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_front_end {
15	namespace front_end {
16	namespace ifetch_unit {
17
18
19
20	#undef FUNCTION
21	#define FUNCTION "Ifetch_unit::allocation"
22	void Ifetch_unit::allocation (
23	#ifdef STATISTICS
24	morpheo::behavioural::Parameters_Statistics * param_statistics
25	#else
26	void
27	#endif
28	)
29	{
30	log_printf(FUNC,Ifetch_unit,FUNCTION,"Begin");
31
32	_component = new Component (_usage);
33
34	Entity * entity = _component->set_entity (_name
35	,"Ifetch_unit"
36	#ifdef POSITION
37	,COMBINATORY
38	#endif
39	);
40
41	_interfaces = entity->set_interfaces();
42
43	// ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
44	{
45	Interface * interface = _interfaces->set_interface(""
46	#ifdef POSITION
47	,IN
48	,SOUTH,
49	_("Generalist interface")
50	#endif
51	);
52
53	in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES);
54	in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, RESET_VHDL_YES);
55	}
56
57	// ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
58	{
59	ALLOC0_INTERFACE_BEGIN("icache_req",OUT, WEST, _("Instruction cache request."));
60
61	ALLOC0_VALACK_OUT(out_ICACHE_REQ_VAL ,VAL);
62	ALLOC0_VALACK_IN ( in_ICACHE_REQ_ACK ,ACK);
63	//ALLOC0_SIGNAL_OUT(out_ICACHE_REQ_THREAD_ID,"thread_id",Tcontext_t ,_param->_size_context_id );
64	ALLOC0_SIGNAL_OUT(out_ICACHE_REQ_PACKET_ID,"packet_id",Tpacket_t ,_param->_size_ifetch_queue_ptr );
65	ALLOC0_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS ,"address" ,Ticache_instruction_t,_param->_size_instruction_address );
66	ALLOC0_SIGNAL_OUT(out_ICACHE_REQ_TYPE ,"type" ,Ticache_type_t ,_param->_size_icache_type);
67
68	ALLOC0_INTERFACE_END();
69	}
70
71	// ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
72	{
73	ALLOC0_INTERFACE_BEGIN("icache_rsp",IN , WEST, _("Instruction cache respons."));
74
75	ALLOC0_VALACK_IN ( in_ICACHE_RSP_VAL ,VAL);
76	ALLOC0_VALACK_OUT (out_ICACHE_RSP_ACK ,ACK);
77	//ALLOC0_SIGNAL_IN ( in_ICACHE_RSP_THREAD_ID ,"thread_id" ,Tcontext_t ,_param->_size_context_id );
78	ALLOC0_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_ifetch_queue_ptr );
79	ALLOC0_SIGNAL_IN ( in_ICACHE_RSP_ERROR ,"error" ,Ticache_error_t ,_param->_size_icache_error);
80
81	ALLOC0_INTERFACE_END();
82	}
83	{
84	ALLOC1_INTERFACE_BEGIN("icache_rsp",IN , WEST, _("Instruction cache respons."),_param->_nb_instruction);
85
86	ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_INSTRUCTION,"instruction",Ticache_instruction_t,_param->_size_instruction );
87
88	ALLOC1_INTERFACE_END(_param->_nb_instruction);
89	}
90
91	// ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
92	{
93	ALLOC0_INTERFACE_BEGIN("predict",OUT, NORTH, _("Predict the next pc."));
94
95	ALLOC0_VALACK_OUT (out_PREDICT_VAL ,VAL);
96	ALLOC0_VALACK_IN ( in_PREDICT_ACK ,ACK);
97	ALLOC0_SIGNAL_OUT (out_PREDICT_PC_PREVIOUS ,"pc_previous" ,Tgeneral_address_t,_param->_size_instruction_address);
98	ALLOC0_SIGNAL_OUT (out_PREDICT_PC_CURRENT ,"pc_current" ,Tgeneral_address_t,_param->_size_instruction_address);
99	ALLOC0_SIGNAL_OUT (out_PREDICT_PC_CURRENT_IS_DS_TAKE ,"pc_current_is_ds_take" ,Tcontrol_t ,1);
100	ALLOC0_SIGNAL_IN ( in_PREDICT_PC_NEXT ,"pc_next" ,Tgeneral_address_t,_param->_size_instruction_address);
101	ALLOC0_SIGNAL_IN ( in_PREDICT_PC_NEXT_IS_DS_TAKE ,"pc_next_is_ds_take" ,Tcontrol_t ,1);
102	ALLOC0_SIGNAL_IN ( in_PREDICT_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr);
103	ALLOC0_SIGNAL_IN ( in_PREDICT_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state);
104	ALLOC0_SIGNAL_IN ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth);
105
106	ALLOC0_INTERFACE_END();
107	}
108	{
109	ALLOC1_INTERFACE_BEGIN("predict",IN , NORTH, _("Predict the next pc."),_param->_nb_instruction);
110
111	ALLOC1_SIGNAL_IN ( in_PREDICT_INSTRUCTION_ENABLE ,"instruction_enable" ,Tcontrol_t ,1);
112
113	ALLOC1_INTERFACE_END(_param->_nb_instruction);
114	}
115
116	// ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
117	{
118	ALLOC0_INTERFACE_BEGIN("decod",OUT , EAST, _("Send bundle to the decod unit."));
119
120	//ALLOC0_SIGNAL_OUT (out_DECOD_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id);
121	ALLOC0_SIGNAL_OUT (out_DECOD_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_instruction_address);
122	ALLOC0_SIGNAL_OUT (out_DECOD_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr);
123	ALLOC0_SIGNAL_OUT (out_DECOD_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state);
124	ALLOC0_SIGNAL_OUT (out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth);
125	ALLOC0_SIGNAL_OUT (out_DECOD_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_ifetch);
126
127	ALLOC0_INTERFACE_END();
128	}
129	{
130	ALLOC1_INTERFACE_BEGIN("decod",OUT , EAST, _("Send bundle to the decod unit."),_param->_nb_instruction);
131
132	ALLOC1_VALACK_OUT(out_DECOD_VAL ,VAL);
133	ALLOC1_VALACK_IN ( in_DECOD_ACK ,ACK);
134	ALLOC1_SIGNAL_OUT(out_DECOD_INSTRUCTION ,"instruction" ,Tinstruction_t ,_param->_size_instruction);
135
136	ALLOC1_INTERFACE_END(_param->_nb_instruction);
137	}
138
139	// ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
140	{
141	ALLOC0_INTERFACE_BEGIN("event",IN , NORTH, _("Event interface."));
142
143	ALLOC0_VALACK_IN ( in_EVENT_VAL ,VAL);
144	ALLOC0_VALACK_OUT(out_EVENT_ACK ,ACK);
145	ALLOC0_SIGNAL_IN ( in_EVENT_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_instruction_address);
146	ALLOC0_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT ,"address_next" ,Tgeneral_address_t,_param->_size_instruction_address);
147	ALLOC0_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT_VAL ,"address_next_val",Tcontrol_t,1);
148	ALLOC0_SIGNAL_IN ( in_EVENT_IS_DS_TAKE ,"is_ds_take" ,Tcontrol_t,1);
149
150	ALLOC0_INTERFACE_END();
151	}
152
153	// ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
154	std::string name;
155
156	{
157	name = _name+"_address_management";
158	log_printf(Ifetch_unit,Core,FUNCTION,_("Create : %s"),name.c_str());
159
160	_component_address_management = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::address_management::Address_management
161	(name.c_str()
162	#ifdef STATISTICS
163	,param_statistics
164	#endif
165	,_param->_param_address_management
166	,_usage);
167
168	_component->set_component (_component_address_management->_component
169	#ifdef POSITION
170	, 50, 50, 10, 10
171	#endif
172	);
173	}
174
175	{
176	name = _name+"_ifetch_queue";
177	log_printf(Ifetch_unit,Core,FUNCTION,_("Create : %s"),name.c_str());
178
179	_component_ifetch_queue = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::Ifetch_queue
180	(name.c_str()
181	#ifdef STATISTICS
182	,param_statistics
183	#endif
184	,_param->_param_ifetch_queue
185	,_usage);
186
187	_component->set_component (_component_ifetch_queue->_component
188	#ifdef POSITION
189	, 50, 50, 10, 10
190	#endif
191	);
192	}
193
194	{
195	name = _name+"_ifetch_unit_glue";
196	log_printf(Ifetch_unit,Core,FUNCTION,_("Create : %s"),name.c_str());
197
198	_component_ifetch_unit_glue = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_unit_glue::Ifetch_unit_Glue
199	(name.c_str()
200	#ifdef STATISTICS
201	,param_statistics
202	#endif
203	,_param->_param_ifetch_unit_glue
204	,_usage);
205
206	_component->set_component (_component_ifetch_unit_glue->_component
207	#ifdef POSITION
208	, 50, 50, 10, 10
209	#endif
210	);
211	}
212
213	// ~~~~~[ Instanciation ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
214	std::string src,dest;
215
216	// ===================================================================
217	// =====[ address_management ]========================================
218	// ===================================================================
219	{
220	src = _name+"_address_management";
221	log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str());
222
223	{
224	dest = _name;
225	#ifdef POSITION
226	_component->interface_map (src ,"",
227	dest,"");
228	#endif
229	PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK");
230	PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET");
231	}
232
233	{
234	dest = _name+"_ifetch_queue";
235
236	for (uint32_t i=0; i<_param->_nb_instruction; i++)
237	{
238	#ifdef POSITION
239	_component->interface_map (src ,"address_"+toString(i),
240	dest,"address_"+toString(i));
241	#endif
242	COMPONENT_MAP(_component,src ,"out_ADDRESS_"+toString(i)+"_INSTRUCTION_ENABLE",
243	dest, "in_ADDRESS_"+toString(i)+"_INSTRUCTION_ENABLE");
244	}
245
246	if (_param->_have_port_inst_ifetch_ptr)
247	COMPONENT_MAP(_component,src ,"out_ADDRESS_INST_IFETCH_PTR" ,
248	dest, "in_ADDRESS_INST_IFETCH_PTR" );
249	COMPONENT_MAP(_component,src ,"out_ADDRESS_BRANCH_STATE" ,
250	dest, "in_ADDRESS_BRANCH_STATE" );
251	if (_param->_have_port_depth)
252	COMPONENT_MAP(_component,src ,"out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID",
253	dest, "in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID");
254
255	dest = _name+"_ifetch_unit_glue";
256
257	#ifdef POSITION
258	_component->interface_map (src ,"address",
259	dest,"address");
260	#endif
261
262	COMPONENT_MAP(_component,src ,"out_ADDRESS_VAL" ,
263	dest, "in_ICACHE_REQ_ADDRESS_VAL");
264	COMPONENT_MAP(_component,src , "in_ADDRESS_ACK" ,
265	dest,"out_ICACHE_REQ_ADDRESS_ACK");
266	COMPONENT_MAP(_component,src ,"out_ADDRESS_INSTRUCTION_ADDRESS",
267	dest, "in_ICACHE_REQ_ADDRESS_ADDRESS");
268	}
269
270	{
271	dest = _name;
272
273	#ifdef POSITION
274	_component->interface_map (src ,"predict",
275	dest,"predict");
276	#endif
277
278	for (uint32_t i=0; i<_param->_nb_instruction; i++)
279	{
280	#ifdef POSITION
281	_component->interface_map (src ,"predict_"+toString(i),
282	dest,"predict_"+toString(i));
283	#endif
284	PORT_MAP(_component,src , "in_PREDICT_"+toString(i)+"_INSTRUCTION_ENABLE"
285	,dest, "in_PREDICT_"+toString(i)+"_INSTRUCTION_ENABLE" );
286	}
287
288	PORT_MAP(_component,src ,"out_PREDICT_VAL"
289	,dest,"out_PREDICT_VAL" );
290	PORT_MAP(_component,src , "in_PREDICT_ACK"
291	,dest, "in_PREDICT_ACK" );
292	PORT_MAP(_component,src ,"out_PREDICT_PC_PREVIOUS"
293	,dest,"out_PREDICT_PC_PREVIOUS" );
294	PORT_MAP(_component,src ,"out_PREDICT_PC_CURRENT"
295	,dest,"out_PREDICT_PC_CURRENT" );
296	PORT_MAP(_component,src ,"out_PREDICT_PC_CURRENT_IS_DS_TAKE"
297	,dest,"out_PREDICT_PC_CURRENT_IS_DS_TAKE" );
298	PORT_MAP(_component,src , "in_PREDICT_PC_NEXT"
299	,dest, "in_PREDICT_PC_NEXT" );
300	PORT_MAP(_component,src , "in_PREDICT_PC_NEXT_IS_DS_TAKE"
301	,dest, "in_PREDICT_PC_NEXT_IS_DS_TAKE" );
302	if (_param->_have_port_inst_ifetch_ptr)
303	PORT_MAP(_component,src , "in_PREDICT_INST_IFETCH_PTR"
304	,dest, "in_PREDICT_INST_IFETCH_PTR" );
305	PORT_MAP(_component,src , "in_PREDICT_BRANCH_STATE"
306	,dest, "in_PREDICT_BRANCH_STATE" );
307	if (_param->_have_port_depth)
308	PORT_MAP(_component,src , "in_PREDICT_BRANCH_UPDATE_PREDICTION_ID"
309	,dest, "in_PREDICT_BRANCH_UPDATE_PREDICTION_ID");
310	}
311
312	{
313	dest = _name+"_ifetch_unit_glue";
314
315	#ifdef POSITION
316	_component->interface_map (src ,"event",
317	dest,"event");
318	_component->interface_map (src ,"event",
319	_name,"event");
320	#endif
321
322	COMPONENT_MAP(_component,src , "in_EVENT_VAL" ,dest ,"out_EVENT_ADDRESS_VAL");
323	COMPONENT_MAP(_component,src ,"out_EVENT_ACK" ,dest , "in_EVENT_ADDRESS_ACK");
324
325
326	dest = _name;
327	PORT_MAP(_component,src , "in_EVENT_ADDRESS" ,dest , "in_EVENT_ADDRESS" );
328	PORT_MAP(_component,src , "in_EVENT_ADDRESS_NEXT" ,dest , "in_EVENT_ADDRESS_NEXT" );
329	PORT_MAP(_component,src , "in_EVENT_ADDRESS_NEXT_VAL",dest , "in_EVENT_ADDRESS_NEXT_VAL" );
330	PORT_MAP(_component,src , "in_EVENT_IS_DS_TAKE" ,dest , "in_EVENT_IS_DS_TAKE" );
331	}
332	}
333
334	// ===================================================================
335	// =====[ ifetch_queue ]==============================================
336	// ===================================================================
337	{
338	src = _name+"_ifetch_queue";
339	log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str());
340
341	{
342	dest = _name;
343	#ifdef POSITION
344	_component->interface_map (src ,"",
345	dest,"");
346	#endif
347	PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK");
348	PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET");
349	}
350
351	{
352	dest = _name;
353
354	#ifdef POSITION
355	_component->interface_map (src ,"address",
356	dest,"address");
357	#endif
358
359	if (_param->_have_port_ifetch_queue_ptr)
360	PORT_MAP(_component,src ,"out_ADDRESS_IFETCH_QUEUE_ID" ,
361	dest,"out_ICACHE_REQ_PACKET_ID" );
362
363	for (uint32_t i=0; i<_param->_nb_instruction; i++)
364	{
365	#ifdef POSITION
366	_component->interface_map (src ,"address_"+toString(i),
367	dest+"_address_management","address_"+toString(i));
368	#endif
369
370	//out_ADDRESS_INSTRUCTION_ENABLE - address_management
371	}
372
373	dest = _name+"_ifetch_unit_glue";
374
375	COMPONENT_MAP(_component,src , "in_ADDRESS_VAL" ,
376	dest,"out_ICACHE_REQ_QUEUE_VAL");
377	COMPONENT_MAP(_component,src ,"out_ADDRESS_ACK" ,
378	dest, "in_ICACHE_REQ_QUEUE_ACK");
379	COMPONENT_MAP(_component,src , "in_ADDRESS_INSTRUCTION_ADDRESS",
380	dest,"out_ICACHE_REQ_QUEUE_ADDRESS");
381	// in_ADDRESS_INST_IFETCH_PTR - address_management
382	// in_ADDRESS_BRANCH_STATE - address_management
383	// in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID - address_management
384	}
385
386	{
387	dest = _name;
388
389	#ifdef POSITION
390	_component->interface_map (src ,"icache_rsp",
391	dest,"icache_rsp");
392	#endif
393
394	for (uint32_t i=0; i<_param->_nb_instruction; i++)
395	{
396	#ifdef POSITION
397	_component->interface_map (src ,"icache_rsp_"+toString(i),
398	dest,"icache_rsp_"+toString(i));
399	#endif
400
401	PORT_MAP(_component,src ,"out_DECOD_"+toString(i)+"_VAL" ,
402	dest,"out_DECOD_"+toString(i)+"_VAL" );
403	PORT_MAP(_component,src , "in_DECOD_"+toString(i)+"_ACK" ,
404	dest, "in_DECOD_"+toString(i)+"_ACK" );
405	PORT_MAP(_component,src ,"out_DECOD_"+toString(i)+"_INSTRUCTION" ,
406	dest,"out_DECOD_"+toString(i)+"_INSTRUCTION" );
407	}
408
409	PORT_MAP(_component,src ,"out_DECOD_ADDRESS" ,dest,"out_DECOD_ADDRESS" );
410	if (_param->_have_port_inst_ifetch_ptr)
411	PORT_MAP(_component,src ,"out_DECOD_INST_IFETCH_PTR" ,dest,"out_DECOD_INST_IFETCH_PTR" );
412	PORT_MAP(_component,src ,"out_DECOD_BRANCH_STATE" ,dest,"out_DECOD_BRANCH_STATE" );
413	if (_param->_have_port_depth)
414	PORT_MAP(_component,src ,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID",dest,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID");
415	PORT_MAP(_component,src ,"out_DECOD_EXCEPTION" ,dest,"out_DECOD_EXCEPTION" );
416	}
417
418	{
419	dest = _name;
420
421	#ifdef POSITION
422	_component->interface_map (src ,"icache_rsp",
423	dest,"icache_rsp");
424	#endif
425
426	PORT_MAP(_component,src , "in_ICACHE_RSP_VAL" ,dest, "in_ICACHE_RSP_VAL" );
427	PORT_MAP(_component,src ,"out_ICACHE_RSP_ACK" ,dest,"out_ICACHE_RSP_ACK" );
428	if (_param->_have_port_ifetch_queue_ptr)
429	PORT_MAP(_component,src , "in_ICACHE_RSP_PACKET_ID",dest, "in_ICACHE_RSP_PACKET_ID");
430	PORT_MAP(_component,src , "in_ICACHE_RSP_ERROR" ,dest, "in_ICACHE_RSP_ERROR" );
431
432	for (uint32_t i=0; i<_param->_nb_instruction; i++)
433	{
434	#ifdef POSITION
435	_component->interface_map (src ,"icache_rsp_"+toString(i),
436	dest,"icache_rsp_"+toString(i));
437	#endif
438	PORT_MAP(_component,src , "in_ICACHE_RSP_"+toString(i)+"_INSTRUCTION",
439	dest, "in_ICACHE_RSP_"+toString(i)+"_INSTRUCTION");
440	}
441	}
442
443	{
444	dest = _name+"_ifetch_unit_glue";
445
446	#ifdef POSITION
447	_component->interface_map (src ,"event_reset",
448	dest,"event");
449	#endif
450
451	COMPONENT_MAP(_component,src , "in_EVENT_RESET_VAL",dest,"out_EVENT_QUEUE_VAL");
452	COMPONENT_MAP(_component,src ,"out_EVENT_RESET_ACK",dest, "in_EVENT_QUEUE_ACK");
453	}
454	}
455
456	// ===================================================================
457	// =====[ ifetch_unit_glue ]==========================================
458	// ===================================================================
459	{
460	src = _name+"_ifetch_unit_glue";
461	log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str());
462
463	{
464	dest = _name;
465	#ifdef POSITION
466	_component->interface_map (src ,"",
467	dest,"");
468	#endif
469	PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK");
470	PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET");
471	}
472
473	{
474	dest = _name;
475
476	#ifdef POSITION
477	_component->interface_map (src ,"icache_req",
478	dest,"icache_req");
479	#endif
480
481	PORT_MAP(_component,src ,"out_ICACHE_REQ_VAL" ,dest,"out_ICACHE_REQ_VAL");
482	PORT_MAP(_component,src , "in_ICACHE_REQ_ACK" ,dest, "in_ICACHE_REQ_ACK");
483	PORT_MAP(_component,src ,"out_ICACHE_REQ_TYPE" ,dest,"out_ICACHE_REQ_TYPE");
484	PORT_MAP(_component,src ,"out_ICACHE_REQ_ADDRESS",dest,"out_ICACHE_REQ_ADDRESS");
485
486	// in_ICACHE_REQ_ADDRESS_VAL - address_management
487	//out_ICACHE_REQ_QUEUE_VAL - ifetch_queue
488	//out_ICACHE_REQ_ADDRESS_ACK - address_management
489	// in_ICACHE_REQ_QUEUE_ACK - ifetch_queue
490	// in_ICACHE_REQ_ADDRESS_ADDRESS - address_management
491	//out_ICACHE_REQ_QUEUE_ADDRESS - ifetch_queue
492
493	}
494
495	{
496	dest = _name;
497
498	#ifdef POSITION
499	_component->interface_map (src ,"event",
500	dest,"event");
501	#endif
502
503	PORT_MAP(_component,src , "in_EVENT_VAL" ,dest , "in_EVENT_VAL" );
504	PORT_MAP(_component,src ,"out_EVENT_ACK" ,dest ,"out_EVENT_ACK" );
505
506	//out_EVENT_ADDRESS_VAL - address_management
507	//out_EVENT_QUEUE_VAL - ifetch_queue
508	// in_EVENT_ADDRESS_ACK - address_management
509	// in_EVENT_QUEUE_ACK - ifetch_queue
510	}
511	}
512
513	// ~~~~~[ Others ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
514	#if DEBUG_Ifetch_unit == true
515	_component->test_map();
516	#endif
517
518	#ifdef POSITION
519	if (usage_is_set(_usage,USE_POSITION))
520	_component->generate_file();
521	#endif
522
523	log_printf(FUNC,Ifetch_unit,FUNCTION,"End");
524	};
525
526	}; // end namespace ifetch_unit
527	}; // end namespace front_end
528	}; // end namespace multi_front_end
529	}; // end namespace core
530
531	}; // end namespace behavioural
532	}; // end namespace morpheo

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