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Ifetch_unit_allocation.cpp @ 78

Last change on this file since 78 was 78, checked in by rosiere, 16 years ago

Add :

Execute_loop (must be test systemC)
Prediction
- Direction : predifined scheme
- Branch Target Buffer
iFetch_unit
- ifetch_queue
- pc management
Decod_unit
- coming soon : support for custom operation
Rename_unit
- RAT
- Free_list
- Dependence RAW check
- Load store unit pointer
New Environnement (hierarchy_memory will remove in a next version)

Modif :

Manage Custom Operation
All component in execute_loop to use the new statistics management

Not Finish :

Return Address Stack
Environnement

File size: 19.7 KB

Line
1	/*
2	* $Id$
3	*
4	* [ Description ]
5	*
6	*/
7
8	#include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/include/Ifetch_unit.h"
9	#include "Behavioural/include/Allocation.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_front_end {
15	namespace front_end {
16	namespace ifetch_unit {
17
18
19
20	#undef FUNCTION
21	#define FUNCTION "Ifetch_unit::allocation"
22	void Ifetch_unit::allocation (
23	#ifdef STATISTICS
24	morpheo::behavioural::Parameters_Statistics * param_statistics
25	#else
26	void
27	#endif
28	)
29	{
30	log_printf(FUNC,Ifetch_unit,FUNCTION,"Begin");
31
32	_component = new Component (_usage);
33
34	Entity * entity = _component->set_entity (_name
35	,"Ifetch_unit"
36	#ifdef POSITION
37	,COMBINATORY
38	#endif
39	);
40
41	_interfaces = entity->set_interfaces();
42
43	// ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
44	{
45	Interface * interface = _interfaces->set_interface(""
46	#ifdef POSITION
47	,IN
48	,SOUTH,
49	"Generalist interface"
50	#endif
51	);
52
53	in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES);
54	in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, RESET_VHDL_YES);
55	}
56
57	// ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
58	{
59	ALLOC_INTERFACE("icache_req",OUT, WEST, "Instruction cache request.");
60
61	ALLOC_VALACK_OUT(out_ICACHE_REQ_VAL ,VAL);
62	ALLOC_VALACK_IN ( in_ICACHE_REQ_ACK ,ACK);
63	//ALLOC_SIGNAL_OUT(out_ICACHE_REQ_THREAD_ID,"thread_id",Tcontext_t ,_param->_size_context_id );
64	ALLOC_SIGNAL_OUT(out_ICACHE_REQ_PACKET_ID,"packet_id",Tpacket_t ,_param->_size_queue_ptr );
65	ALLOC_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS ,"address" ,Ticache_instruction_t,_param->_size_address );
66	ALLOC_SIGNAL_OUT(out_ICACHE_REQ_TYPE ,"type" ,Ticache_type_t ,_param->_size_icache_type);
67	}
68
69	// ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
70	{
71	ALLOC_INTERFACE("icache_rsp",IN , WEST, "Instruction cache respons.");
72
73	ALLOC_VALACK_IN ( in_ICACHE_RSP_VAL ,VAL);
74	ALLOC_VALACK_OUT (out_ICACHE_RSP_ACK ,ACK);
75	//ALLOC_SIGNAL_IN ( in_ICACHE_RSP_THREAD_ID ,"thread_id" ,Tcontext_t ,_param->_size_context_id );
76	ALLOC_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_queue_ptr );
77	ALLOC_SIGNAL_IN ( in_ICACHE_RSP_ERROR ,"error" ,Ticache_error_t ,_param->_size_icache_error);
78	}
79	{
80	ALLOC1_INTERFACE("icache_rsp",IN , WEST, "Instruction cache respons.",_param->_nb_instruction);
81
82	ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_INSTRUCTION,"instruction",Ticache_instruction_t,_param->_size_instruction );
83	}
84
85	// ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
86	{
87	ALLOC_INTERFACE("predict",OUT, NORTH, "Acces Instruction cache respons.");
88
89	ALLOC_VALACK_OUT (out_PREDICT_VAL ,VAL);
90	ALLOC_VALACK_IN ( in_PREDICT_ACK ,ACK);
91	ALLOC_SIGNAL_OUT (out_PREDICT_PC_PREVIOUS ,"pc_previous" ,Tgeneral_address_t,_param->_size_address);
92	ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT ,"pc_current" ,Tgeneral_address_t,_param->_size_address);
93	ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT_IS_DS_TAKE ,"pc_current_is_ds_take" ,Tcontrol_t ,1);
94	ALLOC_SIGNAL_IN ( in_PREDICT_PC_NEXT ,"pc_next" ,Tgeneral_address_t,_param->_size_address);
95	ALLOC_SIGNAL_IN ( in_PREDICT_PC_NEXT_IS_DS_TAKE ,"pc_next_is_ds_take" ,Tcontrol_t ,1);
96	ALLOC_SIGNAL_IN ( in_PREDICT_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_instruction_ptr);
97	ALLOC_SIGNAL_IN ( in_PREDICT_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state);
98	ALLOC_SIGNAL_IN ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_branch_update_prediction);
99	}
100	{
101	ALLOC1_INTERFACE("predict",IN , NORTH, "Acces Instruction cache respons.",_param->_nb_instruction);
102
103	ALLOC1_SIGNAL_IN ( in_PREDICT_INSTRUCTION_ENABLE ,"instruction_enable" ,Tcontrol_t ,1);
104	}
105
106	// ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
107	{
108	ALLOC_INTERFACE("decod",OUT , EAST, "Send bundle to the decod unit.");
109
110	//ALLOC_SIGNAL_OUT (out_DECOD_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id);
111	ALLOC_SIGNAL_OUT (out_DECOD_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_address);
112	ALLOC_SIGNAL_OUT (out_DECOD_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_instruction_ptr);
113	ALLOC_SIGNAL_OUT (out_DECOD_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state);
114	ALLOC_SIGNAL_OUT (out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_branch_update_prediction);
115	ALLOC_SIGNAL_OUT (out_DECOD_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_ifetch);
116	}
117	{
118	ALLOC1_INTERFACE("decod",OUT , EAST, "Send bundle to the decod unit.",_param->_nb_instruction);
119
120	ALLOC1_VALACK_OUT(out_DECOD_VAL ,VAL);
121	ALLOC1_VALACK_IN ( in_DECOD_ACK ,ACK);
122	ALLOC1_SIGNAL_OUT(out_DECOD_INSTRUCTION ,"instruction" ,Tinstruction_t ,_param->_size_instruction);
123	}
124
125	// ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
126	{
127	ALLOC_INTERFACE("event",IN , NORTH, "Event interface.");
128
129	ALLOC_VALACK_IN ( in_EVENT_VAL ,VAL);
130	ALLOC_VALACK_OUT(out_EVENT_ACK ,ACK);
131	ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS,"address",Tgeneral_address_t,_param->_size_address);
132	}
133
134	// ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
135	std::string name;
136
137	{
138	name = _name+"_address_management";
139	std::cout << "Create : " << name << std::endl;
140
141	_component_address_management = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::address_management::Address_management
142	(name.c_str()
143	#ifdef STATISTICS
144	,param_statistics
145	#endif
146	,_param->_param_address_management);
147
148	_component->set_component (_component_address_management->_component
149	#ifdef POSITION
150	, 50, 50, 10, 10
151	#endif
152	);
153	}
154
155	{
156	name = _name+"_ifetch_queue";
157	std::cout << "Create : " << name << std::endl;
158
159	_component_ifetch_queue = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::Ifetch_queue
160	(name.c_str()
161	#ifdef STATISTICS
162	,param_statistics
163	#endif
164	,_param->_param_ifetch_queue);
165
166	_component->set_component (_component_ifetch_queue->_component
167	#ifdef POSITION
168	, 50, 50, 10, 10
169	#endif
170	);
171	}
172
173	{
174	name = _name+"_ifetch_unit_glue";
175	std::cout << "Create : " << name << std::endl;
176
177	_component_ifetch_unit_glue = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_unit_glue::Ifetch_unit_Glue
178	(name.c_str()
179	#ifdef STATISTICS
180	,param_statistics
181	#endif
182	,_param->_param_ifetch_unit_glue);
183
184	_component->set_component (_component_ifetch_unit_glue->_component
185	#ifdef POSITION
186	, 50, 50, 10, 10
187	#endif
188	);
189	}
190
191	// ~~~~~[ Instanciation ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
192	std::string src,dest;
193
194	// ===================================================================
195	// =====[ address_management ]========================================
196	// ===================================================================
197	{
198	src = _name+"_address_management";
199	std::cout << "Instance : " << src << std::endl;
200
201	{
202	dest = _name;
203	#ifdef POSITION
204	_component->interface_map (src ,"",
205	dest,"");
206	#endif
207	PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK");
208	PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET");
209	}
210
211	{
212	dest = _name;
213
214	#ifdef POSITION
215	_component->interface_map (src ,"address",
216	dest,"icache_req");
217	_component->interface_map (src ,"address",
218	dest+"_ifetch_unit_glue","address");
219	#endif
220
221	for (uint32_t i=0; i<_param->_nb_instruction; i++)
222	{
223	#ifdef POSITION
224	_component->interface_map (src ,"address_"+toString(i),
225	dest+"_ifetch_queue","address_"+toString(i));
226	#endif
227	PORT_MAP(_component,src ,"out_ADDRESS_"+toString(i)+"_INSTRUCTION_ENABLE",
228	dest+"_ifetch_queue", "in_ADDRESS_"+toString(i)+"_INSTRUCTION_ENABLE");
229	}
230
231	PORT_MAP(_component,src ,"out_ADDRESS_VAL" ,
232	dest+"_ifetch_unit_glue", "in_ICACHE_REQ_ADDRESS_VAL" );
233	PORT_MAP(_component,src , "in_ADDRESS_ACK" ,
234	dest+"_ifetch_unit_glue","out_ICACHE_REQ_ADDRESS_ACK" );
235	PORT_MAP(_component,src ,"out_ADDRESS_INSTRUCTION_ADDRESS" ,
236	dest,"out_ICACHE_REQ_ADDRESS");
237	PORT_MAP(_component,src ,"out_ADDRESS_INSTRUCTION_ADDRESS" ,
238	dest+"_ifetch_queue", "in_ADDRESS_INSTRUCTION_ADDRESS" );
239	if (_param->_have_port_instruction_ptr)
240	PORT_MAP(_component,src ,"out_ADDRESS_INST_IFETCH_PTR" ,
241	dest+"_ifetch_queue", "in_ADDRESS_INST_IFETCH_PTR" );
242	PORT_MAP(_component,src ,"out_ADDRESS_BRANCH_STATE" ,
243	dest+"_ifetch_queue", "in_ADDRESS_BRANCH_STATE" );
244	if (_param->_have_port_branch_update_prediction_id)
245	PORT_MAP(_component,src ,"out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID",
246	dest+"_ifetch_queue", "in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID");
247	}
248
249	{
250	dest = _name;
251
252	#ifdef POSITION
253	_component->interface_map (src ,"predict",
254	dest,"predict");
255	#endif
256
257	for (uint32_t i=0; i<_param->_nb_instruction; i++)
258	{
259	#ifdef POSITION
260	_component->interface_map (src ,"predict_"+toString(i),
261	dest,"predict_"+toString(i));
262	#endif
263	PORT_MAP(_component,src , "in_PREDICT_"+toString(i)+"_INSTRUCTION_ENABLE"
264	,dest, "in_PREDICT_"+toString(i)+"_INSTRUCTION_ENABLE" );
265	}
266
267	PORT_MAP(_component,src ,"out_PREDICT_VAL"
268	,dest,"out_PREDICT_VAL" );
269	PORT_MAP(_component,src , "in_PREDICT_ACK"
270	,dest, "in_PREDICT_ACK" );
271	PORT_MAP(_component,src ,"out_PREDICT_PC_PREVIOUS"
272	,dest,"out_PREDICT_PC_PREVIOUS" );
273	PORT_MAP(_component,src ,"out_PREDICT_PC_CURRENT"
274	,dest,"out_PREDICT_PC_CURRENT" );
275	PORT_MAP(_component,src ,"out_PREDICT_PC_CURRENT_IS_DS_TAKE"
276	,dest,"out_PREDICT_PC_CURRENT_IS_DS_TAKE" );
277	PORT_MAP(_component,src , "in_PREDICT_PC_NEXT"
278	,dest, "in_PREDICT_PC_NEXT" );
279	PORT_MAP(_component,src , "in_PREDICT_PC_NEXT_IS_DS_TAKE"
280	,dest, "in_PREDICT_PC_NEXT_IS_DS_TAKE" );
281	if (_param->_have_port_instruction_ptr)
282	PORT_MAP(_component,src , "in_PREDICT_INST_IFETCH_PTR"
283	,dest, "in_PREDICT_INST_IFETCH_PTR" );
284	PORT_MAP(_component,src , "in_PREDICT_BRANCH_STATE"
285	,dest, "in_PREDICT_BRANCH_STATE" );
286	if (_param->_have_port_branch_update_prediction_id)
287	PORT_MAP(_component,src , "in_PREDICT_BRANCH_UPDATE_PREDICTION_ID"
288	,dest, "in_PREDICT_BRANCH_UPDATE_PREDICTION_ID");
289	}
290
291	{
292	dest = _name+"_ifetch_unit_glue";
293
294	#ifdef POSITION
295	_component->interface_map (src ,"event",
296	dest,"event");
297	_component->interface_map (src ,"event",
298	_name,"event");
299	#endif
300
301	PORT_MAP(_component,src , "in_EVENT_VAL" ,dest ,"out_EVENT_ADDRESS_VAL");
302	PORT_MAP(_component,src ,"out_EVENT_ACK" ,dest , "in_EVENT_ADDRESS_ACK");
303	PORT_MAP(_component,src , "in_EVENT_ADDRESS",_name, "in_EVENT_ADDRESS");
304	}
305	}
306
307	// ===================================================================
308	// =====[ ifetch_queue ]==============================================
309	// ===================================================================
310	{
311	src = _name+"_ifetch_queue";
312	std::cout << "Instance : " << src << std::endl;
313
314	{
315	dest = _name;
316	#ifdef POSITION
317	_component->interface_map (src ,"",
318	dest,"");
319	#endif
320	PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK");
321	PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET");
322	}
323
324	{
325	dest = _name;
326
327	#ifdef POSITION
328	_component->interface_map (src ,"address",
329	dest,"address");
330	#endif
331
332	for (uint32_t i=0; i<_param->_nb_instruction; i++)
333	{
334	#ifdef POSITION
335	_component->interface_map (src ,"address_"+toString(i),
336	dest+"_address_management","address_"+toString(i));
337	#endif
338
339	PORT_MAP(_component,src , "in_ADDRESS_"+toString(i)+"_INSTRUCTION_ENABLE" ,
340	dest+"_address_management","out_ADDRESS_"+toString(i)+"_INSTRUCTION_ENABLE" );
341	}
342
343	PORT_MAP(_component,src , "in_ADDRESS_VAL" ,
344	dest+"_ifetch_unit_glue" ,"out_ICACHE_REQ_QUEUE_VAL" );
345	PORT_MAP(_component,src ,"out_ADDRESS_ACK" ,
346	dest+"_ifetch_unit_glue" , "in_ICACHE_REQ_QUEUE_ACK" );
347	if (_param->_have_port_queue_ptr)
348	PORT_MAP(_component,src ,"out_ADDRESS_IFETCH_QUEUE_ID" ,
349	dest ,"out_ICACHE_REQ_PACKET_ID" );
350	PORT_MAP(_component,src , "in_ADDRESS_INSTRUCTION_ADDRESS" ,
351	dest+"_address_management","out_ADDRESS_INSTRUCTION_ADDRESS" );
352	if (_param->_have_port_instruction_ptr)
353	PORT_MAP(_component,src , "in_ADDRESS_INST_IFETCH_PTR" ,
354	dest+"_address_management","out_ADDRESS_INST_IFETCH_PTR" );
355	PORT_MAP(_component,src , "in_ADDRESS_BRANCH_STATE" ,
356	dest+"_address_management","out_ADDRESS_BRANCH_STATE" );
357	if (_param->_have_port_branch_update_prediction_id)
358	PORT_MAP(_component,src , "in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID",
359	dest+"_address_management","out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID");
360	}
361
362	{
363	dest = _name;
364
365	#ifdef POSITION
366	_component->interface_map (src ,"icache_rsp",
367	dest,"icache_rsp");
368	#endif
369
370	for (uint32_t i=0; i<_param->_nb_instruction; i++)
371	{
372	#ifdef POSITION
373	_component->interface_map (src ,"icache_rsp_"+toString(i),
374	dest,"icache_rsp_"+toString(i));
375	#endif
376
377	PORT_MAP(_component,src ,"out_DECOD_"+toString(i)+"_VAL" ,
378	dest,"out_DECOD_"+toString(i)+"_VAL" );
379	PORT_MAP(_component,src , "in_DECOD_"+toString(i)+"_ACK" ,
380	dest, "in_DECOD_"+toString(i)+"_ACK" );
381	PORT_MAP(_component,src ,"out_DECOD_"+toString(i)+"_INSTRUCTION" ,
382	dest,"out_DECOD_"+toString(i)+"_INSTRUCTION" );
383	}
384
385	PORT_MAP(_component,src ,"out_DECOD_ADDRESS" ,dest,"out_DECOD_ADDRESS" );
386	if (_param->_have_port_instruction_ptr)
387	PORT_MAP(_component,src ,"out_DECOD_INST_IFETCH_PTR" ,dest,"out_DECOD_INST_IFETCH_PTR" );
388	PORT_MAP(_component,src ,"out_DECOD_BRANCH_STATE" ,dest,"out_DECOD_BRANCH_STATE" );
389	if (_param->_have_port_branch_update_prediction_id)
390	PORT_MAP(_component,src ,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID",dest,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID");
391	PORT_MAP(_component,src ,"out_DECOD_EXCEPTION" ,dest,"out_DECOD_EXCEPTION" );
392	}
393
394	{
395	dest = _name;
396
397	#ifdef POSITION
398	_component->interface_map (src ,"icache_rsp",
399	dest,"icache_rsp");
400	#endif
401
402	PORT_MAP(_component,src , "in_ICACHE_RSP_VAL" ,dest, "in_ICACHE_RSP_VAL" );
403	PORT_MAP(_component,src ,"out_ICACHE_RSP_ACK" ,dest,"out_ICACHE_RSP_ACK" );
404	if (_param->_have_port_queue_ptr)
405	PORT_MAP(_component,src , "in_ICACHE_RSP_PACKET_ID",dest, "in_ICACHE_RSP_PACKET_ID");
406	PORT_MAP(_component,src , "in_ICACHE_RSP_ERROR" ,dest, "in_ICACHE_RSP_ERROR" );
407
408	for (uint32_t i=0; i<_param->_nb_instruction; i++)
409	{
410	#ifdef POSITION
411	_component->interface_map (src ,"icache_rsp_"+toString(i),
412	dest,"icache_rsp_"+toString(i));
413	#endif
414	PORT_MAP(_component,src , "in_ICACHE_RSP_"+toString(i)+"_INSTRUCTION",
415	dest, "in_ICACHE_RSP_"+toString(i)+"_INSTRUCTION");
416	}
417	}
418
419	{
420	dest = _name+"_ifetch_unit_glue";
421
422	#ifdef POSITION
423	_component->interface_map (src ,"event_reset",
424	dest,"event");
425	#endif
426
427	PORT_MAP(_component,src , "in_EVENT_RESET_VAL",dest,"out_EVENT_QUEUE_VAL");
428	PORT_MAP(_component,src ,"out_EVENT_RESET_ACK",dest, "in_EVENT_QUEUE_ACK");
429	}
430	}
431
432	// ===================================================================
433	// =====[ ifetch_unit_glue ]==========================================
434	// ===================================================================
435	{
436	src = _name+"_ifetch_unit_glue";
437	std::cout << "Instance : " << src << std::endl;
438
439	{
440	dest = _name;
441	#ifdef POSITION
442	_component->interface_map (src ,"",
443	dest,"");
444	#endif
445	PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK");
446	PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET");
447	}
448
449	{
450	dest = _name;
451
452	#ifdef POSITION
453	_component->interface_map (src ,"icache_req",
454	dest,"icache_req");
455	#endif
456
457	PORT_MAP(_component,src ,"out_ICACHE_REQ_VAL" ,dest ,"out_ICACHE_REQ_VAL");
458	PORT_MAP(_component,src , "in_ICACHE_REQ_ADDRESS_VAL",dest+"_address_management","out_ADDRESS_VAL");
459	PORT_MAP(_component,src ,"out_ICACHE_REQ_QUEUE_VAL" ,dest+"_ifetch_queue" , "in_ADDRESS_VAL" );
460	PORT_MAP(_component,src , "in_ICACHE_REQ_ACK" ,dest , "in_ICACHE_REQ_ACK");
461	PORT_MAP(_component,src ,"out_ICACHE_REQ_ADDRESS_ACK",dest+"_address_management", "in_ADDRESS_ACK");
462	PORT_MAP(_component,src , "in_ICACHE_REQ_QUEUE_ACK" ,dest+"_ifetch_queue" ,"out_ADDRESS_ACK");
463	PORT_MAP(_component,src ,"out_ICACHE_REQ_TYPE" ,dest ,"out_ICACHE_REQ_TYPE");
464	}
465
466	{
467	dest = _name;
468
469	#ifdef POSITION
470	_component->interface_map (src ,"event",
471	dest,"event");
472	#endif
473
474	PORT_MAP(_component,src , "in_EVENT_VAL" ,dest , "in_EVENT_VAL" );
475	PORT_MAP(_component,src ,"out_EVENT_ADDRESS_VAL",dest+"_address_management", "in_EVENT_VAL" );
476	PORT_MAP(_component,src ,"out_EVENT_QUEUE_VAL" ,dest+"_ifetch_queue" , "in_EVENT_RESET_VAL" );
477	PORT_MAP(_component,src ,"out_EVENT_ACK" ,dest ,"out_EVENT_ACK" );
478	PORT_MAP(_component,src , "in_EVENT_ADDRESS_ACK",dest+"_address_management","out_EVENT_ACK" );
479	PORT_MAP(_component,src , "in_EVENT_QUEUE_ACK" ,dest+"_ifetch_queue" ,"out_EVENT_RESET_ACK" );
480	}
481	}
482
483	// ~~~~~[ Others ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
484	_component->test_map();
485
486	#ifdef POSITION
487	_component->generate_file();
488	#endif
489
490	log_printf(FUNC,Ifetch_unit,FUNCTION,"End");
491	};
492
493	}; // end namespace ifetch_unit
494	}; // end namespace front_end
495	}; // end namespace multi_front_end
496	}; // end namespace core
497
498	}; // end namespace behavioural
499	}; // end namespace morpheo

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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_allocation.cpp @ 78

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