[78] | 1 | /* |
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| 2 | * $Id: Branch_Target_Buffer_Glue_allocation.cpp 88 2008-12-10 18:31:39Z rosiere $ |
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| 3 | * |
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| 4 | * [ Description ] |
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| 5 | * |
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| 6 | */ |
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| 7 | |
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| 8 | #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/include/Branch_Target_Buffer_Glue.h" |
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| 9 | #include "Behavioural/include/Allocation.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_front_end { |
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| 15 | namespace front_end { |
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| 16 | namespace prediction_unit { |
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| 17 | namespace branch_target_buffer { |
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| 18 | namespace branch_target_buffer_glue { |
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| 19 | |
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| 20 | |
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| 21 | |
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| 22 | #undef FUNCTION |
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| 23 | #define FUNCTION "Branch_Target_Buffer_Glue::allocation" |
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| 24 | void Branch_Target_Buffer_Glue::allocation ( |
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| 25 | #ifdef STATISTICS |
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| 26 | morpheo::behavioural::Parameters_Statistics * param_statistics |
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| 27 | #else |
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| 28 | void |
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| 29 | #endif |
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| 30 | ) |
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| 31 | { |
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| 32 | log_printf(FUNC,Branch_Target_Buffer_Glue,FUNCTION,"Begin"); |
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| 33 | |
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| 34 | _component = new Component (_usage); |
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| 35 | |
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| 36 | Entity * entity = _component->set_entity (_name |
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| 37 | ,"Branch_Target_Buffer_Glue" |
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| 38 | #ifdef POSITION |
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| 39 | ,COMBINATORY |
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| 40 | #endif |
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| 41 | ); |
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| 42 | |
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| 43 | _interfaces = entity->set_interfaces(); |
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| 44 | |
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| 45 | // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 46 | { |
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| 47 | Interface * interface = _interfaces->set_interface("" |
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| 48 | #ifdef POSITION |
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| 49 | ,IN |
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| 50 | ,SOUTH, |
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| 51 | "Generalist interface" |
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| 52 | #endif |
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| 53 | ); |
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| 54 | |
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| 55 | in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES); |
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| 56 | in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, RESET_VHDL_YES); |
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| 57 | } |
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| 58 | |
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| 59 | // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 60 | { |
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| 61 | { |
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| 62 | ALLOC1_INTERFACE("predict", IN, WEST, "predict",_param->_nb_inst_predict); |
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| 63 | |
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| 64 | ALLOC1_SIGNAL_IN ( in_PREDICT_VAL , "val" ,Tcontrol_t , 1); |
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| 65 | ALLOC1_SIGNAL_OUT(out_PREDICT_ACK , "ack" ,Tcontrol_t , 1); |
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| 66 | ALLOC1_SIGNAL_OUT(out_PREDICT_HIT , "hit" ,Tcontrol_t , 1); |
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[88] | 67 | ALLOC1_SIGNAL_OUT(out_PREDICT_ADDRESS_SRC , "address_src" ,Tgeneral_data_t , _param->_size_instruction_address); |
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| 68 | ALLOC1_SIGNAL_OUT(out_PREDICT_ADDRESS_DEST , "address_dest" ,Tgeneral_data_t , _param->_size_instruction_address); |
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[78] | 69 | ALLOC1_SIGNAL_OUT(out_PREDICT_CONDITION , "condition" ,Tbranch_condition_t, _param->_size_branch_condition); |
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| 70 | ALLOC1_SIGNAL_OUT(out_PREDICT_LAST_TAKE , "last_take" ,Tcontrol_t , 1); |
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| 71 | ALLOC1_SIGNAL_OUT(out_PREDICT_IS_ACCURATE , "is_accurate" ,Tcontrol_t , 1); |
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| 72 | ALLOC1_SIGNAL_OUT(out_PREDICT_REGISTER_VAL , "register_val" ,Tcontrol_t , 1); |
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| 73 | ALLOC1_SIGNAL_IN ( in_PREDICT_REGISTER_ACK , "register_ack" ,Tcontrol_t , 1); |
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| 74 | if (_param->_have_port_victim) |
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| 75 | { |
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| 76 | ALLOC1_SIGNAL_IN ( in_PREDICT_SORT_VAL ,"sort_val" ,Tptr_t,1); |
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| 77 | ALLOC1_SIGNAL_IN ( in_PREDICT_SORT_INDEX,"sort_index",Tptr_t,_param->_size_victim); |
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| 78 | |
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| 79 | ALLOC1_SIGNAL_OUT(out_PREDICT_VICTIM_VAL , "victim_val" ,Tcontrol_t , 1); |
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| 80 | ALLOC1_SIGNAL_IN ( in_PREDICT_VICTIM_ACK , "victim_ack" ,Tcontrol_t , 1); |
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| 81 | ALLOC1_SIGNAL_OUT(out_PREDICT_VICTIM_HIT , "victim_hit" ,Tcontrol_t , 1); |
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| 82 | ALLOC1_SIGNAL_OUT(out_PREDICT_VICTIM_ADDRESS, "victim_address",Tgeneral_data_t , _param->_size_victim_address); |
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| 83 | ALLOC1_SIGNAL_OUT(out_PREDICT_VICTIM_INDEX , "victim_index" ,Tptr_t , _param->_size_victim); |
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| 84 | ALLOC1_SIGNAL_IN ( in_PREDICT_VICTIM_VICTIM , "victim_victim" ,Tptr_t , _param->_size_victim); |
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| 85 | } |
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| 86 | } |
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| 87 | { |
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| 88 | ALLOC2_INTERFACE("predict", IN, WEST, "predict",_param->_nb_inst_predict, _param->_associativity); |
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| 89 | |
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| 90 | ALLOC2_SIGNAL_IN ( in_PREDICT_REGISTER_HIT ,"register_hit" ,Tcontrol_t ,1); |
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[88] | 91 | ALLOC2_SIGNAL_IN ( in_PREDICT_REGISTER_ADDRESS_SRC ,"register_address_src" ,Tgeneral_data_t ,_param->_size_instruction_address); |
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| 92 | ALLOC2_SIGNAL_IN ( in_PREDICT_REGISTER_ADDRESS_DEST,"register_address_dest",Tgeneral_data_t ,_param->_size_instruction_address); |
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[78] | 93 | ALLOC2_SIGNAL_IN ( in_PREDICT_REGISTER_CONDITION ,"register_condition" ,Tbranch_condition_t,_param->_size_branch_condition); |
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| 94 | ALLOC2_SIGNAL_IN ( in_PREDICT_REGISTER_LAST_TAKE ,"register_last_take" ,Tcontrol_t ,1); |
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| 95 | ALLOC2_SIGNAL_IN ( in_PREDICT_REGISTER_IS_ACCURATE ,"register_is_accurate" ,Tcontrol_t ,1); |
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| 96 | } |
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| 97 | } |
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| 98 | |
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| 99 | // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 100 | { |
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| 101 | ALLOC1_INTERFACE("decod", IN, WEST, "decod",_param->_nb_inst_decod); |
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| 102 | |
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| 103 | ALLOC1_SIGNAL_IN ( in_DECOD_VAL ,"val" ,Tcontrol_t ,1); |
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| 104 | ALLOC1_SIGNAL_OUT(out_DECOD_ACK ,"ack" ,Tcontrol_t ,1); |
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| 105 | if (not _param->_is_full_associative) |
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[88] | 106 | ALLOC1_SIGNAL_IN ( in_DECOD_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t,_param->_size_instruction_address); |
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[78] | 107 | |
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| 108 | ALLOC1_SIGNAL_OUT(out_DECOD_REGISTER_VAL ,"register_val" ,Tcontrol_t ,1); |
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| 109 | ALLOC1_SIGNAL_IN ( in_DECOD_REGISTER_ACK ,"register_ack" ,Tcontrol_t ,1); |
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| 110 | |
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| 111 | if (_param->_have_port_victim) |
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| 112 | { |
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| 113 | ALLOC1_SIGNAL_OUT(out_DECOD_VICTIM_VAL ,"victim_val" ,Tcontrol_t ,1); |
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| 114 | ALLOC1_SIGNAL_IN ( in_DECOD_VICTIM_ACK ,"victim_ack" ,Tcontrol_t ,1); |
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| 115 | ALLOC1_SIGNAL_OUT(out_DECOD_VICTIM_ADDRESS,"victim_address",Tgeneral_data_t,_param->_size_victim_address); |
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| 116 | } |
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| 117 | } |
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| 118 | |
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| 119 | // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 120 | { |
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| 121 | ALLOC1_INTERFACE("update", IN, WEST, "update",_param->_nb_inst_update); |
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| 122 | |
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| 123 | ALLOC1_SIGNAL_IN ( in_UPDATE_VAL ,"val" ,Tcontrol_t ,1); |
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| 124 | ALLOC1_SIGNAL_OUT(out_UPDATE_ACK ,"ack" ,Tcontrol_t ,1); |
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| 125 | if (not _param->_is_full_associative) |
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[88] | 126 | ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t,_param->_size_instruction_address); |
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[78] | 127 | |
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| 128 | ALLOC1_SIGNAL_OUT(out_UPDATE_REGISTER_VAL ,"register_val" ,Tcontrol_t ,1); |
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| 129 | ALLOC1_SIGNAL_IN ( in_UPDATE_REGISTER_ACK ,"register_ack" ,Tcontrol_t ,1); |
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| 130 | |
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| 131 | if (_param->_have_port_victim) |
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| 132 | { |
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| 133 | ALLOC1_SIGNAL_OUT(out_UPDATE_VICTIM_VAL ,"victim_val" ,Tcontrol_t ,1); |
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| 134 | ALLOC1_SIGNAL_IN ( in_UPDATE_VICTIM_ACK ,"victim_ack" ,Tcontrol_t ,1); |
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| 135 | ALLOC1_SIGNAL_OUT(out_UPDATE_VICTIM_ADDRESS,"victim_address",Tgeneral_data_t,_param->_size_victim_address); |
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| 136 | } |
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| 137 | } |
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| 138 | |
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| 139 | // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 140 | |
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| 141 | #ifdef POSITION |
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[88] | 142 | if (usage_is_set(_usage,USE_POSITION)) |
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| 143 | _component->generate_file(); |
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[78] | 144 | #endif |
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| 145 | |
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| 146 | log_printf(FUNC,Branch_Target_Buffer_Glue,FUNCTION,"End"); |
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| 147 | }; |
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| 148 | |
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| 149 | }; // end namespace branch_target_buffer_glue |
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| 150 | }; // end namespace branch_target_buffer |
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| 151 | }; // end namespace prediction_unit |
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| 152 | }; // end namespace front_end |
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| 153 | }; // end namespace multi_front_end |
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| 154 | }; // end namespace core |
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| 155 | |
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| 156 | }; // end namespace behavioural |
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| 157 | }; // end namespace morpheo |
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