source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_genMealy_predict.cpp @ 98

Last change on this file since 98 was 98, checked in by rosiere, 16 years ago

1) Fix bug (read unit, RAT -> write in R0, SPR desallocation ...)
2) Change VHDL Execute_queue -> use Generic/Queue?
3) Complete document on VHDL generation
4) Add soc test
  • Property svn:keywords set to Id
File size: 4.3 KB
Line 
1#ifdef SYSTEMC
2/*
3 * $Id: Branch_Target_Buffer_Glue_genMealy_predict.cpp 98 2008-12-31 10:18:08Z rosiere $
4 *
5 * [ Description ]
6 *
7 */
8
9#include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/include/Branch_Target_Buffer_Glue.h"
10
11namespace morpheo {
12namespace behavioural {
13namespace core {
14namespace multi_front_end {
15namespace front_end {
16namespace prediction_unit {
17namespace branch_target_buffer {
18namespace branch_target_buffer_glue {
19
20#undef  FUNCTION
21#define FUNCTION "Branch_Target_Buffer_Glue::genMealy_predict"
22  void Branch_Target_Buffer_Glue::genMealy_predict (void)
23  {
24    log_begin(Branch_Target_Buffer_Glue,FUNCTION);
25    log_function(Branch_Target_Buffer_Glue,FUNCTION,_name.c_str());
26
27    for (uint32_t i=0; i<_param->_nb_inst_predict; i++)
28      {
29        log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION,"  * PREDICT [%d]",i);
30        Tptr_t          index       = (_param->_have_port_victim)?PORT_READ(in_PREDICT_SORT_INDEX [i]):0;
31        Tcontrol_t      hit         = PORT_READ(in_PREDICT_REGISTER_HIT         [i][index]);
32        Tgeneral_data_t address_src = PORT_READ(in_PREDICT_REGISTER_ADDRESS_SRC [i][index]);
33
34        log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION,"    * index        : %d"  ,index      );
35        log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION,"    * hit          : %d"  ,hit        );
36        log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION,"    * address_src  : %.8x",address_src);
37
38        // Multiplexor
39        PORT_WRITE(out_PREDICT_HIT          [i],hit);
40        PORT_WRITE(out_PREDICT_ADDRESS_SRC  [i],address_src);
41        PORT_WRITE(out_PREDICT_ADDRESS_DEST [i],PORT_READ(in_PREDICT_REGISTER_ADDRESS_DEST  [i][index]));
42        PORT_WRITE(out_PREDICT_CONDITION    [i],PORT_READ(in_PREDICT_REGISTER_CONDITION     [i][index]));
43        PORT_WRITE(out_PREDICT_LAST_TAKE    [i],PORT_READ(in_PREDICT_REGISTER_LAST_TAKE     [i][index]));
44        PORT_WRITE(out_PREDICT_IS_ACCURATE  [i],PORT_READ(in_PREDICT_REGISTER_IS_ACCURATE   [i][index]));
45
46        Tcontrol_t val          = PORT_READ(in_PREDICT_VAL          [i]);
47        Tcontrol_t register_ack = PORT_READ(in_PREDICT_REGISTER_ACK [i]);
48        Tcontrol_t sort_val     = (_param->_have_port_victim)?PORT_READ(in_PREDICT_SORT_VAL   [i]):true;
49        Tcontrol_t victim_ack   = (_param->_have_port_victim)?PORT_READ(in_PREDICT_VICTIM_ACK [i]):true;
50
51        log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION,"    * val          : %d",val         );
52        log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION,"    * register_ack : %d",register_ack);
53        log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION,"    * sort_val     : %d",sort_val    );
54        log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION,"    * victim_ack   : %d",victim_ack  );
55       
56        PORT_WRITE(out_PREDICT_ACK            [i], (
57//                                                  val          and
58                                                    register_ack and
59                                                    sort_val     and
60                                                    victim_ack
61                                                    ));
62        PORT_WRITE(out_PREDICT_REGISTER_VAL   [i], (
63                                                    val          and
64//                                                  register_ack and
65                                                    sort_val     and
66                                                    victim_ack
67                                                    ));
68
69        if (_param->_have_port_victim)
70          {
71        PORT_WRITE(out_PREDICT_VICTIM_VAL     [i], (
72                                                    val          and
73                                                    register_ack and
74                                                    sort_val     // and
75//                                                  victim_ack
76                                                    ));
77        PORT_WRITE(out_PREDICT_VICTIM_HIT     [i], hit);
78        if (not _param->_is_full_associative)
79        PORT_WRITE(out_PREDICT_VICTIM_ADDRESS [i], (address_src >> _param->_shift_bank)&_param->_mask_bank);
80        PORT_WRITE(out_PREDICT_VICTIM_INDEX   [i], index);
81          }
82      }
83
84    log_end(Branch_Target_Buffer_Glue,FUNCTION);
85  };
86
87}; // end namespace branch_target_buffer_glue
88}; // end namespace branch_target_buffer
89}; // end namespace prediction_unit
90}; // end namespace front_end
91}; // end namespace multi_front_end
92}; // end namespace core
93}; // end namespace behavioural
94}; // end namespace morpheo             
95#endif
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