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test.cpp @ 78

Last change on this file since 78 was 78, checked in by rosiere, 16 years ago

Add :

Execute_loop (must be test systemC)
Prediction
- Direction : predifined scheme
- Branch Target Buffer
iFetch_unit
- ifetch_queue
- pc management
Decod_unit
- coming soon : support for custom operation
Rename_unit
- RAT
- Free_list
- Dependence RAW check
- Load store unit pointer
New Environnement (hierarchy_memory will remove in a next version)

Modif :

Manage Custom Operation
All component in execute_loop to use the new statistics management

Not Finish :

Return Address Stack
Environnement

File size: 22.3 KB

Line
1	/*
2	* $Id$
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/include/test.h"
10	#include "Common/include/Test.h"
11	#include "Common/include/BitManipulation.h"
12	#include "Behavioural/include/Allocation.h"
13
14	#define NB_ITERATION 1024
15	#define CYCLE_MAX (128*NB_ITERATION)
16
17	#define LABEL(str...) \
18	{ \
19	msg (_("{%d} "),static_cast<uint32_t>(sc_simulation_time())); \
20	msg (str); \
21	msg (_("\n")); \
22	} while(0)
23
24	#define SC_START(cycle_offset) \
25	do \
26	{ \
27	/cout << "SC_START (begin)" << endl;/ \
28	\
29	uint32_t cycle_current = static_cast<uint32_t>(sc_simulation_time()); \
30	if (cycle_offset != 0) \
31	{ \
32	cout << "##########[ cycle "<< cycle_current+cycle_offset << " ]" << endl; \
33	} \
34	\
35	if (cycle_current > CYCLE_MAX) \
36	{ \
37	TEST_KO("Maximal cycles Reached"); \
38	} \
39	\
40	sc_start(cycle_offset); \
41	\
42	/cout << "SC_START (end )" << endl;/ \
43	} while(0)
44
45
46	class entry_t
47	{
48	public : Tcontrol_t _val ;
49	public : Tcontext_t _context ;
50	public : Tcontrol_t _address_dest_val;
51	public : Tgeneral_data_t _address_src ;
52	public : Tgeneral_data_t _address_dest ;
53	public : Tbranch_condition_t _condition ;
54	public : Tcontrol_t _last_take ;
55	public : Tcounter_t _accurate ;
56
57	public : bool hit (morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::branch_target_buffer::branch_target_buffer_register::Parameters * _param,
58	Tgeneral_data_t addr_test,
59	Tcontext_t context)
60	{
61	Tgeneral_data_t addr_src_offset = (_address_src >> _param->_shift_offset)&_param->_mask_offset;
62	Tgeneral_data_t addr_src_index = (_address_src >> _param->_shift_bank )&_param->_mask_bank ;
63	Tgeneral_data_t addr_src_tag = (_address_src >> _param->_shift_tag );
64
65	Tgeneral_data_t addr_test_offset = (addr_test >> _param->_shift_offset)&_param->_mask_offset;
66	Tgeneral_data_t addr_test_index = (addr_test >> _param->_shift_bank )&_param->_mask_bank ;
67	Tgeneral_data_t addr_test_tag = (addr_test >> _param->_shift_tag );
68
69	bool is_hit = ( (_val == 1 ) and
70	(_context == context ) and
71	(addr_test_tag == addr_src_tag ) and
72	(addr_test_index == addr_src_index ) and
73	(addr_test_offset <= addr_src_offset ));
74
75	LABEL("address_src (tag, index, offset) : %.8x %.8x %.8x",addr_src_tag, addr_src_index, addr_src_offset);
76	LABEL("address_test (tag, index, offset) : %.8x %.8x %.8x - hit : %d",addr_test_tag, addr_test_index, addr_test_offset, is_hit);
77	return is_hit;
78	}
79
80	public : void print (void)
81	{
82	LABEL("%d - %.2d %.8x %.1d %.8x %.3d %.1d %.4d",
83	_val ,
84	_context ,
85	_address_src ,
86	_address_dest_val,
87	_address_dest ,
88	_condition ,
89	_last_take ,
90	_accurate );
91
92	}
93
94	};
95
96
97
98	Tgeneral_data_t gen_addr (morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::branch_target_buffer::branch_target_buffer_register::Parameters * _param,
99	Tgeneral_data_t index)
100	{
101	Tgeneral_data_t addr_tag = (rand()%(2*_param->_associativity)) << _param->_shift_tag ;
102	Tgeneral_data_t addr_index = (index &_param->_mask_bank ) << _param->_shift_bank ;
103	Tgeneral_data_t addr_offset = (rand()&_param->_mask_offset ) << _param->_shift_offset;
104
105	LABEL("gen_addr (tag, index, offset) : %.8x %.8x %.8x",addr_tag, addr_index, addr_offset);
106
107	return (addr_tag \|
108	addr_index \|
109	addr_offset );
110	}
111
112
113	void test (string name,
114	morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::branch_target_buffer::branch_target_buffer_register::Parameters * _param)
115	{
116	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
117
118	#ifdef STATISTICS
119	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50);
120	#endif
121
122	Branch_Target_Buffer_Register * _Branch_Target_Buffer_Register = new Branch_Target_Buffer_Register (name.c_str(),
123	#ifdef STATISTICS
124	_parameters_statistics,
125	#endif
126	_param);
127
128	#ifdef SYSTEMC
129	/*********************************************************************
130	* Déclarations des signaux
131	*********************************************************************/
132	string rename;
133
134	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
135	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
136
137	ALLOC1_SC_SIGNAL( in_PREDICT_VAL ," in_PREDICT_VAL ",Tcontrol_t ,_param->_nb_inst_predict);
138	ALLOC1_SC_SIGNAL(out_PREDICT_ACK ,"out_PREDICT_ACK ",Tcontrol_t ,_param->_nb_inst_predict);
139	ALLOC1_SC_SIGNAL( in_PREDICT_CONTEXT_ID ," in_PREDICT_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_predict);
140	ALLOC1_SC_SIGNAL( in_PREDICT_ADDRESS ," in_PREDICT_ADDRESS ",Tgeneral_data_t ,_param->_nb_inst_predict);
141	ALLOC2_SC_SIGNAL(out_PREDICT_HIT ,"out_PREDICT_HIT ",Tcontrol_t ,_param->_nb_inst_predict,_param->_associativity);
142	ALLOC2_SC_SIGNAL(out_PREDICT_ADDRESS_SRC ,"out_PREDICT_ADDRESS_SRC ",Tgeneral_data_t ,_param->_nb_inst_predict,_param->_associativity);
143	ALLOC2_SC_SIGNAL(out_PREDICT_ADDRESS_DEST ,"out_PREDICT_ADDRESS_DEST ",Tgeneral_data_t ,_param->_nb_inst_predict,_param->_associativity);
144	ALLOC2_SC_SIGNAL(out_PREDICT_CONDITION ,"out_PREDICT_CONDITION ",Tbranch_condition_t,_param->_nb_inst_predict,_param->_associativity);
145	ALLOC2_SC_SIGNAL(out_PREDICT_LAST_TAKE ,"out_PREDICT_LAST_TAKE ",Tcontrol_t ,_param->_nb_inst_predict,_param->_associativity);
146	ALLOC2_SC_SIGNAL(out_PREDICT_IS_ACCURATE ,"out_PREDICT_IS_ACCURATE ",Tcontrol_t ,_param->_nb_inst_predict,_param->_associativity);
147	ALLOC1_SC_SIGNAL( in_DECOD_VAL ," in_DECOD_VAL ",Tcontrol_t ,_param->_nb_inst_decod);
148	ALLOC1_SC_SIGNAL(out_DECOD_ACK ,"out_DECOD_ACK ",Tcontrol_t ,_param->_nb_inst_decod);
149	ALLOC1_SC_SIGNAL(out_DECOD_HIT ,"out_DECOD_HIT ",Tcontrol_t ,_param->_nb_inst_decod);
150	ALLOC1_SC_SIGNAL(out_DECOD_HIT_INDEX ,"out_DECOD_HIT_INDEX ",Tptr_t ,_param->_nb_inst_decod);
151	ALLOC1_SC_SIGNAL( in_DECOD_VICTIM ," in_DECOD_VICTIM ",Tptr_t ,_param->_nb_inst_decod);
152	ALLOC1_SC_SIGNAL( in_DECOD_CONTEXT_ID ," in_DECOD_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_decod);
153	ALLOC1_SC_SIGNAL( in_DECOD_ADDRESS_SRC ," in_DECOD_ADDRESS_SRC ",Tgeneral_data_t ,_param->_nb_inst_decod);
154	ALLOC1_SC_SIGNAL( in_DECOD_ADDRESS_DEST ," in_DECOD_ADDRESS_DEST ",Tgeneral_data_t ,_param->_nb_inst_decod);
155	ALLOC1_SC_SIGNAL( in_DECOD_CONDITION ," in_DECOD_CONDITION ",Tbranch_condition_t,_param->_nb_inst_decod);
156	ALLOC1_SC_SIGNAL( in_DECOD_LAST_TAKE ," in_DECOD_LAST_TAKE ",Tcontrol_t ,_param->_nb_inst_decod);
157	ALLOC1_SC_SIGNAL( in_DECOD_MISS_PREDICTION ," in_DECOD_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_inst_decod);
158	ALLOC1_SC_SIGNAL( in_UPDATE_VAL ," in_UPDATE_VAL ",Tcontrol_t ,_param->_nb_inst_update);
159	ALLOC1_SC_SIGNAL(out_UPDATE_ACK ,"out_UPDATE_ACK ",Tcontrol_t ,_param->_nb_inst_update);
160	ALLOC1_SC_SIGNAL(out_UPDATE_HIT ,"out_UPDATE_HIT ",Tcontrol_t ,_param->_nb_inst_update);
161	ALLOC1_SC_SIGNAL(out_UPDATE_HIT_INDEX ,"out_UPDATE_HIT_INDEX ",Tptr_t ,_param->_nb_inst_update);
162	ALLOC1_SC_SIGNAL( in_UPDATE_VICTIM ," in_UPDATE_VICTIM ",Tptr_t ,_param->_nb_inst_update);
163	ALLOC1_SC_SIGNAL( in_UPDATE_CONTEXT_ID ," in_UPDATE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_update);
164	ALLOC1_SC_SIGNAL( in_UPDATE_ADDRESS_SRC ," in_UPDATE_ADDRESS_SRC ",Tgeneral_data_t ,_param->_nb_inst_update);
165	ALLOC1_SC_SIGNAL( in_UPDATE_ADDRESS_DEST ," in_UPDATE_ADDRESS_DEST ",Tgeneral_data_t ,_param->_nb_inst_update);
166	ALLOC1_SC_SIGNAL( in_UPDATE_CONDITION ," in_UPDATE_CONDITION ",Tbranch_condition_t,_param->_nb_inst_update);
167	ALLOC1_SC_SIGNAL( in_UPDATE_LAST_TAKE ," in_UPDATE_LAST_TAKE ",Tcontrol_t ,_param->_nb_inst_update);
168	ALLOC1_SC_SIGNAL( in_UPDATE_MISS_PREDICTION," in_UPDATE_MISS_PREDICTION",Tcontrol_t ,_param->_nb_inst_update);
169
170	/********************************************************
171	* Instanciation
172	********************************************************/
173
174	msg(_("<%s> : Instanciation of _Branch_Target_Buffer_Register.\n"),name.c_str());
175
176	((_Branch_Target_Buffer_Register->in_CLOCK)) ((in_CLOCK));
177	((_Branch_Target_Buffer_Register->in_NRESET)) ((in_NRESET));
178
179	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_PREDICT_VAL ,_param->_nb_inst_predict);
180	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register,out_PREDICT_ACK ,_param->_nb_inst_predict);
181	if (_param->_have_port_context_id)
182	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_PREDICT_CONTEXT_ID ,_param->_nb_inst_predict);
183	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_PREDICT_ADDRESS ,_param->_nb_inst_predict);
184	INSTANCE2_SC_SIGNAL(_Branch_Target_Buffer_Register,out_PREDICT_HIT ,_param->_nb_inst_predict,_param->_associativity);
185	INSTANCE2_SC_SIGNAL(_Branch_Target_Buffer_Register,out_PREDICT_ADDRESS_SRC ,_param->_nb_inst_predict,_param->_associativity);
186	INSTANCE2_SC_SIGNAL(_Branch_Target_Buffer_Register,out_PREDICT_ADDRESS_DEST ,_param->_nb_inst_predict,_param->_associativity);
187	INSTANCE2_SC_SIGNAL(_Branch_Target_Buffer_Register,out_PREDICT_CONDITION ,_param->_nb_inst_predict,_param->_associativity);
188	INSTANCE2_SC_SIGNAL(_Branch_Target_Buffer_Register,out_PREDICT_LAST_TAKE ,_param->_nb_inst_predict,_param->_associativity);
189	INSTANCE2_SC_SIGNAL(_Branch_Target_Buffer_Register,out_PREDICT_IS_ACCURATE ,_param->_nb_inst_predict,_param->_associativity);
190
191	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_DECOD_VAL ,_param->_nb_inst_decod);
192	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register,out_DECOD_ACK ,_param->_nb_inst_decod);
193	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register,out_DECOD_HIT ,_param->_nb_inst_decod);
194	if (_param->_have_port_victim)
195	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register,out_DECOD_HIT_INDEX ,_param->_nb_inst_decod);
196	if (_param->_have_port_victim)
197	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_DECOD_VICTIM ,_param->_nb_inst_decod);
198	if (_param->_have_port_context_id)
199	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_DECOD_CONTEXT_ID ,_param->_nb_inst_decod);
200	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_DECOD_ADDRESS_SRC ,_param->_nb_inst_decod);
201	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_DECOD_ADDRESS_DEST ,_param->_nb_inst_decod);
202	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_DECOD_CONDITION ,_param->_nb_inst_decod);
203	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_DECOD_LAST_TAKE ,_param->_nb_inst_decod);
204	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_DECOD_MISS_PREDICTION ,_param->_nb_inst_decod);
205
206	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_UPDATE_VAL ,_param->_nb_inst_update);
207	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register,out_UPDATE_ACK ,_param->_nb_inst_update);
208	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register,out_UPDATE_HIT ,_param->_nb_inst_update);
209	if (_param->_have_port_victim)
210	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register,out_UPDATE_HIT_INDEX ,_param->_nb_inst_update);
211	if (_param->_have_port_victim)
212	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_UPDATE_VICTIM ,_param->_nb_inst_update);
213	if (_param->_have_port_context_id)
214	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_UPDATE_CONTEXT_ID ,_param->_nb_inst_update);
215	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_UPDATE_ADDRESS_SRC ,_param->_nb_inst_update);
216	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_UPDATE_ADDRESS_DEST ,_param->_nb_inst_update);
217	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_UPDATE_CONDITION ,_param->_nb_inst_update);
218	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_UPDATE_LAST_TAKE ,_param->_nb_inst_update);
219	INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_UPDATE_MISS_PREDICTION,_param->_nb_inst_update);
220
221	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
222
223	Time * _time = new Time();
224
225	/********************************************************
226	* Simulation - Begin
227	********************************************************/
228
229	// Initialisation
230
231	const uint32_t seed = 0;
232	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
233
234	srand(seed);
235
236	const int32_t percent_transaction_predict = 75;
237	const int32_t percent_transaction_decod = 75;
238	const int32_t percent_transaction_update = 75;
239
240	uint32_t num_index = 0;
241	entry_t tab_old [_param->_associativity];
242	entry_t tab [_param->_associativity];
243
244	for (uint32_t i=0; i<_param->_associativity; i++)
245	tab[i]._val = false;
246
247	SC_START(0);
248	LABEL("Initialisation");
249
250	for (uint32_t i=0; i<_param->_nb_inst_predict; i++)
251	in_PREDICT_VAL [i]->write(0);
252	for (uint32_t i=0; i<_param->_nb_inst_decod ; i++)
253	in_DECOD_VAL [i]->write(0);
254	for (uint32_t i=0; i<_param->_nb_inst_update ; i++)
255	in_UPDATE_VAL [i]->write(0);
256
257	LABEL("Reset");
258	in_NRESET->write(0);
259	SC_START(5);
260	in_NRESET->write(1);
261
262	LABEL("Loop of Test");
263
264	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
265	{
266	LABEL("Iteration %d",iteration);
267
268	for (uint32_t j=0; j<_param->_associativity; j++)
269	tab[j].print();
270
271	for (uint32_t i=0; i<_param->_nb_inst_predict; i++)
272	{
273	Tgeneral_data_t addr;
274	uint32_t j = rand()%_param->_associativity;
275
276	if ( ((rand()%100)<percent_transaction_predict) and
277	tab [j]._val)
278	addr = tab [j]._address_src;
279	else
280	addr = gen_addr(_param, num_index);
281
282	in_PREDICT_VAL [i]->write((rand()%100)<percent_transaction_predict);
283	in_PREDICT_CONTEXT_ID [i]->write(rand()%_param->_nb_context);
284	in_PREDICT_ADDRESS [i]->write(addr);
285	}
286
287	for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
288	{
289	Tgeneral_data_t addr = gen_addr(_param, num_index);
290
291	in_DECOD_VAL [i]->write((rand()%100)<percent_transaction_decod);
292	in_DECOD_VICTIM [i]->write(rand()%_param->_associativity);
293	in_DECOD_CONTEXT_ID [i]->write(rand()%_param->_nb_context);
294	in_DECOD_ADDRESS_SRC [i]->write(addr);
295	in_DECOD_ADDRESS_DEST [i]->write(~addr);
296	in_DECOD_CONDITION [i]->write((addr&1)?BRANCH_CONDITION_FLAG_SET:BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK);
297	in_DECOD_LAST_TAKE [i]->write(rand()%2);
298	in_DECOD_MISS_PREDICTION [i]->write(rand()%2);
299	}
300
301	for (uint32_t i=0; i<_param->_nb_inst_update; i++)
302	{
303	Tgeneral_data_t addr = gen_addr(_param, num_index);
304
305	in_UPDATE_VAL [i]->write((rand()%100)<percent_transaction_update);
306	in_UPDATE_VICTIM [i]->write(rand()%_param->_associativity);
307	in_UPDATE_CONTEXT_ID [i]->write(rand()%_param->_nb_context);
308	in_UPDATE_ADDRESS_SRC [i]->write(addr);
309	in_UPDATE_ADDRESS_DEST [i]->write(~addr);
310	in_UPDATE_CONDITION [i]->write((addr&1)?BRANCH_CONDITION_FLAG_SET:BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK);
311	in_UPDATE_LAST_TAKE [i]->write(rand()%2);
312	in_UPDATE_MISS_PREDICTION [i]->write(rand()%2);
313	}
314
315	SC_START(0);
316
317	for (uint32_t i=0; i<_param->_associativity; i++)
318	tab_old [i] = tab [i];
319
320	for (uint32_t i=0; i<_param->_nb_inst_predict ; i++)
321	if (in_PREDICT_VAL [i]->read() and out_PREDICT_ACK [i]->read())
322	{
323	LABEL("PREDICT [%d] : Transaction accepted",i);
324	LABEL(" * context : %d" ,in_PREDICT_CONTEXT_ID [i]->read());
325	LABEL(" * address : %.8x",in_PREDICT_ADDRESS [i]->read());
326
327	Tcontext_t ctxt = in_PREDICT_CONTEXT_ID [i]->read();
328	Tgeneral_data_t addr = in_PREDICT_ADDRESS [i]->read();
329
330	for (uint32_t j=0; j<_param->_associativity; j++)
331	{
332	LABEL(" * [%d]",j);
333
334	bool hit = tab_old[j].hit(_param, addr, ctxt);
335	TEST(Tcontrol_t , out_PREDICT_HIT [i][j]->read(), hit);
336
337	if (tab_old[j]._val)
338	{
339	Tgeneral_data_t addr_src = tab_old[j]._address_src;
340
341	TEST(Tgeneral_data_t , out_PREDICT_ADDRESS_SRC [i][j]->read(), addr_src);
342	TEST(Tgeneral_data_t , out_PREDICT_ADDRESS_DEST [i][j]->read(), ~addr_src);
343	TEST(Tbranch_condition_t, out_PREDICT_CONDITION [i][j]->read(), ((addr_src&1)?BRANCH_CONDITION_FLAG_SET:BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK));
344	TEST(Tcontrol_t , out_PREDICT_LAST_TAKE [i][j]->read(), tab_old[j]._last_take);
345	// TEST(Tcontrol_t , out_PREDICT_IS_ACCURATE [i][j]->read(), );
346	}
347	}
348	}
349
350	for (uint32_t i=0; i<_param->_nb_inst_decod ; i++)
351	if (in_DECOD_VAL [i]->read() and out_DECOD_ACK [i]->read())
352	{
353	LABEL("DECOD [%d] : Transaction accepted",i);
354	LABEL(" * context : %d" ,in_DECOD_CONTEXT_ID [i]->read());
355	LABEL(" * address_src : %.8x",in_DECOD_ADDRESS_SRC [i]->read());
356
357	bool hit = false;
358
359	for (uint32_t j=0; j<_param->_associativity; j++)
360	hit \|= ((tab_old[j]._val == 1) and
361	(tab_old[j]._context == in_DECOD_CONTEXT_ID [i]->read()) and
362	(tab_old[j]._address_src == in_DECOD_ADDRESS_SRC [i]->read()));
363
364	if (not hit)
365	{
366	Tptr_t k = in_DECOD_VICTIM [i]->read();
367
368	LABEL(" * miss");
369	LABEL(" * victim : %d",k);
370
371	tab[k]._val = 1;
372	tab[k]._context = in_DECOD_CONTEXT_ID [i]->read();
373	tab[k]._address_src = in_DECOD_ADDRESS_SRC [i]->read();
374	tab[k]._address_dest_val = in_DECOD_CONDITION [i]->read() == BRANCH_CONDITION_FLAG_SET;
375	tab[k]._address_dest = in_DECOD_ADDRESS_DEST[i]->read();
376	tab[k]._condition = in_DECOD_CONDITION [i]->read();
377	tab[k]._last_take = in_DECOD_LAST_TAKE [i]->read();
378	//tab[k]._accurate = _param->_first_accurate_if_hit;
379	}
380	else
381	{
382	LABEL(" * miss");
383	}
384
385	TEST(Tcontrol_t, out_DECOD_HIT [i]->read(), hit);
386	}
387
388	for (uint32_t i=0; i<_param->_nb_inst_update ; i++)
389	if (in_UPDATE_VAL [i]->read() and out_UPDATE_ACK [i]->read())
390	{
391	LABEL("UPDATE [%d] : Transaction accepted",i);
392	LABEL(" * context : %d" ,in_UPDATE_CONTEXT_ID [i]->read());
393	LABEL(" * address_src : %.8x",in_UPDATE_ADDRESS_SRC [i]->read());
394
395	bool hit = false;
396
397	Tptr_t k = 0;
398	for (uint32_t j=0; j<_param->_associativity; j++)
399	{
400	hit \|= ((tab_old[j]._val == 1) and
401	(tab_old[j]._context == in_UPDATE_CONTEXT_ID [i]->read()) and
402	(tab_old[j]._address_src == in_UPDATE_ADDRESS_SRC [i]->read()));
403	if (hit)
404	{
405	k = j;
406	break;
407	}
408	}
409
410	if (not hit)
411	{
412	k = in_UPDATE_VICTIM [i]->read();
413
414	LABEL(" * miss");
415	LABEL(" * victim : %d",k);
416
417	tab[k]._val = 1;
418	tab[k]._context = in_UPDATE_CONTEXT_ID [i]->read();
419	tab[k]._address_src = in_UPDATE_ADDRESS_SRC [i]->read();
420	tab[k]._address_dest_val = 1;
421	tab[k]._address_dest = in_UPDATE_ADDRESS_DEST[i]->read();
422	tab[k]._condition = in_UPDATE_CONDITION [i]->read();
423	tab[k]._last_take = in_UPDATE_LAST_TAKE [i]->read();
424	//tab[k]._accurate = (in_UPDATE_MISS_PREDICTION [i]->read())?_param->_first_accurate_if_miss:_param->_first_accurate_if_hit;
425	}
426	else
427	{
428	LABEL(" * hit");
429	LABEL(" * update : %d",k);
430
431	tab[k]._val = 1;
432	tab[k]._context = in_UPDATE_CONTEXT_ID [i]->read();
433	tab[k]._address_src = in_UPDATE_ADDRESS_SRC [i]->read();
434	tab[k]._address_dest_val = 1;
435	tab[k]._address_dest = in_UPDATE_ADDRESS_DEST[i]->read();
436	tab[k]._condition = in_UPDATE_CONDITION [i]->read();
437	tab[k]._last_take = in_UPDATE_LAST_TAKE [i]->read();
438	//tab[k]._accurate = (in_UPDATE_MISS_PREDICTION [i]->read())?_param->_first_accurate_if_miss:_param->_first_accurate_if_hit;
439	}
440
441	TEST(Tcontrol_t, out_UPDATE_HIT [i]->read(), hit);
442	}
443
444	SC_START(1);
445	}
446
447	/********************************************************
448	* Simulation - End
449	********************************************************/
450
451	TEST_OK ("End of Simulation");
452	delete _time;
453
454	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
455
456	delete in_CLOCK;
457	delete in_NRESET;
458
459	delete [] in_PREDICT_VAL ;
460	delete [] out_PREDICT_ACK ;
461	delete [] in_PREDICT_CONTEXT_ID ;
462	delete [] in_PREDICT_ADDRESS ;
463	delete [] out_PREDICT_HIT ;
464	delete [] out_PREDICT_ADDRESS_SRC ;
465	delete [] out_PREDICT_ADDRESS_DEST ;
466	delete [] out_PREDICT_CONDITION ;
467	delete [] out_PREDICT_LAST_TAKE ;
468	delete [] out_PREDICT_IS_ACCURATE ;
469	delete [] in_DECOD_VAL ;
470	delete [] out_DECOD_ACK ;
471	delete [] out_DECOD_HIT ;
472	delete [] out_DECOD_HIT_INDEX ;
473	delete [] in_DECOD_VICTIM ;
474	delete [] in_DECOD_CONTEXT_ID ;
475	delete [] in_DECOD_ADDRESS_SRC ;
476	delete [] in_DECOD_ADDRESS_DEST ;
477	delete [] in_DECOD_CONDITION ;
478	delete [] in_DECOD_LAST_TAKE ;
479	delete [] in_DECOD_MISS_PREDICTION ;
480	delete [] in_UPDATE_VAL ;
481	delete [] out_UPDATE_ACK ;
482	delete [] out_UPDATE_HIT ;
483	delete [] out_UPDATE_HIT_INDEX ;
484	delete [] in_UPDATE_VICTIM ;
485	delete [] in_UPDATE_CONTEXT_ID ;
486	delete [] in_UPDATE_ADDRESS_SRC ;
487	delete [] in_UPDATE_ADDRESS_DEST ;
488	delete [] in_UPDATE_CONDITION ;
489	delete [] in_UPDATE_LAST_TAKE ;
490	delete [] in_UPDATE_MISS_PREDICTION;
491
492	#endif
493
494	delete _Branch_Target_Buffer_Register;
495	#ifdef STATISTICS
496	delete _parameters_statistics;
497	#endif
498	}

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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/src/test.cpp @ 78

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