source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_allocation.cpp @ 135

Last change on this file since 135 was 135, checked in by rosiere, 15 years ago

1) Add Vhdl component
2) Inhib VHDL Seltest interface
  • Property svn:keywords set to Id
File size: 7.0 KB
RevLine 
[78]1/*
2 * $Id: Branch_Target_Buffer_Register_allocation.cpp 135 2009-07-17 08:59:05Z rosiere $
3 *
4 * [ Description ]
5 *
6 */
7
8#include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/include/Branch_Target_Buffer_Register.h"
9#include "Behavioural/include/Allocation.h"
10
11namespace morpheo                    {
12namespace behavioural {
13namespace core {
14namespace multi_front_end {
15namespace front_end {
16namespace prediction_unit {
17namespace branch_target_buffer {
18namespace branch_target_buffer_register {
19
20
21
22#undef  FUNCTION
23#define FUNCTION "Branch_Target_Buffer_Register::allocation"
24  void Branch_Target_Buffer_Register::allocation (
25#ifdef STATISTICS
26                               morpheo::behavioural::Parameters_Statistics * param_statistics
27#else
28                               void
29#endif
30                               )
31  {
32    log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"Begin");
33
34    _component   = new Component (_usage);
35
36    Entity * entity = _component->set_entity (_name       
37                                              ,"Branch_Target_Buffer_Register"
38#ifdef POSITION
39                                              ,COMBINATORY
40#endif
41                                              );
42
43    _interfaces = entity->set_interfaces();
44
45    // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
46    {
47      Interface * interface = _interfaces->set_interface(""
48#ifdef POSITION
49                                                         ,IN
50                                                         ,SOUTH,
[112]51                                                         _("Generalist interface")
[78]52#endif
53                                                         );
54     
55      in_CLOCK        = interface->set_signal_clk              ("clock" ,1, CLOCK_VHDL_YES);
56      in_NRESET       = interface->set_signal_in  <Tcontrol_t> ("nreset",1, RESET_VHDL_YES);
57    }
58
59    // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
60    {
[112]61      ALLOC1_INTERFACE_BEGIN("predict", IN, SOUTH, _("Compute next pc."), _param->_nb_inst_predict);
[78]62
63      ALLOC1_VALACK_IN ( in_PREDICT_VAL         ,VAL);
64      ALLOC1_VALACK_OUT(out_PREDICT_ACK         ,ACK);
65      ALLOC1_SIGNAL_IN ( in_PREDICT_CONTEXT_ID  ,"context_id"  ,Tcontext_t         ,_param->_size_context_id);
[88]66      ALLOC1_SIGNAL_IN ( in_PREDICT_ADDRESS     ,"address"     ,Tgeneral_data_t    ,_param->_size_instruction_address);
[78]67
[112]68      ALLOC1_INTERFACE_END(_param->_nb_inst_predict);
[78]69    }
[112]70    {
71      ALLOC2_INTERFACE_BEGIN("predict", OUT, SOUTH, _("Compute next pc."), _param->_nb_inst_predict, _param->_associativity);
72     
73      ALLOC2_SIGNAL_OUT(out_PREDICT_HIT         ,"hit"         ,Tcontrol_t         ,1);
74      ALLOC2_SIGNAL_OUT(out_PREDICT_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t    ,_param->_size_instruction_address);
75      ALLOC2_SIGNAL_OUT(out_PREDICT_ADDRESS_DEST,"address_dest",Tgeneral_data_t    ,_param->_size_instruction_address);
[135]76      ALLOC2_SIGNAL_OUT(out_PREDICT_CONDITION   ,"condition"   ,Tbranch_condition_t,_param->_size_branch_condition);
[112]77      ALLOC2_SIGNAL_OUT(out_PREDICT_LAST_TAKE   ,"last_take"   ,Tcontrol_t         ,1);
78      ALLOC2_SIGNAL_OUT(out_PREDICT_IS_ACCURATE ,"is_accurate" ,Tcontrol_t         ,1);
[78]79
[112]80      ALLOC2_INTERFACE_END(_param->_nb_inst_predict, _param->_associativity);
81    }
82
[78]83    // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
84    {
[112]85      ALLOC1_INTERFACE_BEGIN("decod", IN, SOUTH, _("decod instruction"), _param->_nb_inst_decod);
[78]86
87      ALLOC1_VALACK_IN ( in_DECOD_VAL            ,VAL);
88      ALLOC1_VALACK_OUT(out_DECOD_ACK            ,ACK);
[82]89      if (_param->_have_port_victim)
90        {
[78]91      ALLOC1_SIGNAL_OUT(out_DECOD_HIT            ,"hit"            ,Tcontrol_t         ,1);
92      ALLOC1_SIGNAL_OUT(out_DECOD_HIT_INDEX      ,"hit_index"      ,Tptr_t             ,_param->_size_victim);
93      ALLOC1_SIGNAL_IN ( in_DECOD_VICTIM         ,"victim"         ,Tptr_t             ,_param->_size_victim);
[82]94        }
[78]95      ALLOC1_SIGNAL_IN ( in_DECOD_CONTEXT_ID     ,"context_id"     ,Tcontext_t         ,_param->_size_context_id);
[88]96      ALLOC1_SIGNAL_IN ( in_DECOD_ADDRESS_SRC    ,"address_src"    ,Tgeneral_data_t    ,_param->_size_instruction_address);
97      ALLOC1_SIGNAL_IN ( in_DECOD_ADDRESS_DEST   ,"address_dest"   ,Tgeneral_data_t    ,_param->_size_instruction_address);
[135]98      ALLOC1_SIGNAL_IN ( in_DECOD_CONDITION      ,"condition"      ,Tbranch_condition_t,_param->_size_branch_condition);
[78]99      ALLOC1_SIGNAL_IN ( in_DECOD_LAST_TAKE      ,"last_take"      ,Tcontrol_t         ,1);
100      ALLOC1_SIGNAL_IN ( in_DECOD_MISS_PREDICTION,"miss_prediction",Tcontrol_t         ,1);
[82]101      ALLOC1_SIGNAL_IN ( in_DECOD_IS_ACCURATE    ,"is_accurate"    ,Tcontrol_t         ,1);
[112]102
103      ALLOC1_INTERFACE_END(_param->_nb_inst_decod);
[78]104    }
105
106    // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
107    {
[112]108      ALLOC1_INTERFACE_BEGIN("update", IN, SOUTH, _("update instruction"), _param->_nb_inst_update);
[78]109
110      ALLOC1_VALACK_IN ( in_UPDATE_VAL            ,VAL);
111      ALLOC1_VALACK_OUT(out_UPDATE_ACK            ,ACK);
[82]112      if (_param->_have_port_victim)
113        {
[78]114      ALLOC1_SIGNAL_OUT(out_UPDATE_HIT            ,"hit"            ,Tcontrol_t         ,1);
115      ALLOC1_SIGNAL_OUT(out_UPDATE_HIT_INDEX      ,"hit_index"      ,Tptr_t             ,_param->_size_victim);
116      ALLOC1_SIGNAL_IN ( in_UPDATE_VICTIM         ,"victim"         ,Tptr_t             ,_param->_size_victim);
[82]117        }
[78]118      ALLOC1_SIGNAL_IN ( in_UPDATE_CONTEXT_ID     ,"context_id"     ,Tcontext_t         ,_param->_size_context_id);
[88]119      ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS_SRC    ,"address_src"    ,Tgeneral_data_t    ,_param->_size_instruction_address);
120      ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS_DEST   ,"address_dest"   ,Tgeneral_data_t    ,_param->_size_instruction_address);
[135]121      ALLOC1_SIGNAL_IN ( in_UPDATE_CONDITION      ,"condition"      ,Tbranch_condition_t,_param->_size_branch_condition);
[78]122      ALLOC1_SIGNAL_IN ( in_UPDATE_LAST_TAKE      ,"last_take"      ,Tcontrol_t         ,1);
123      ALLOC1_SIGNAL_IN ( in_UPDATE_MISS_PREDICTION,"miss_prediction",Tcontrol_t         ,1);
[112]124
125      ALLOC1_INTERFACE_END(_param->_nb_inst_update);
[78]126    }
127
[88]128    if (usage_is_set(_usage,USE_SYSTEMC))
129      {
[78]130    // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   
[112]131        ALLOC2(reg_BTB,btb_entry_t,_param->_size_bank,_param->_associativity);
[78]132
[112]133        ALLOC1(internal_DECOD_ACK       ,Tcontrol_t,_param->_nb_inst_decod );
134        ALLOC1(internal_DECOD_HIT       ,Tcontrol_t,_param->_nb_inst_decod );
135        ALLOC1(internal_DECOD_NUM_BANK  ,uint32_t  ,_param->_nb_inst_decod );
136        ALLOC1(internal_DECOD_NUM_ENTRY ,uint32_t  ,_param->_nb_inst_decod );
[78]137
[112]138        ALLOC1(internal_UPDATE_ACK      ,Tcontrol_t,_param->_nb_inst_update);
139        ALLOC1(internal_UPDATE_HIT      ,Tcontrol_t,_param->_nb_inst_update);
140        ALLOC1(internal_UPDATE_NUM_BANK ,uint32_t  ,_param->_nb_inst_update);
141        ALLOC1(internal_UPDATE_NUM_ENTRY,uint32_t  ,_param->_nb_inst_update);
[88]142      }
[78]143
144    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   
145
146#ifdef POSITION
[88]147    if (usage_is_set(_usage,USE_POSITION))
148      _component->generate_file();
[78]149#endif
150
151    log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"End");
152  };
153
154}; // end namespace branch_target_buffer_register
155}; // end namespace branch_target_buffer
156}; // end namespace prediction_unit
157}; // end namespace front_end
158}; // end namespace multi_front_end
159}; // end namespace core
160
161}; // end namespace behavioural
162}; // end namespace morpheo             
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