/* * $Id: Branch_Target_Buffer_Register_allocation.cpp 112 2009-03-18 22:36:26Z rosiere $ * * [ Description ] * */ #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/include/Branch_Target_Buffer_Register.h" #include "Behavioural/include/Allocation.h" namespace morpheo { namespace behavioural { namespace core { namespace multi_front_end { namespace front_end { namespace prediction_unit { namespace branch_target_buffer { namespace branch_target_buffer_register { #undef FUNCTION #define FUNCTION "Branch_Target_Buffer_Register::allocation" void Branch_Target_Buffer_Register::allocation ( #ifdef STATISTICS morpheo::behavioural::Parameters_Statistics * param_statistics #else void #endif ) { log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"Begin"); _component = new Component (_usage); Entity * entity = _component->set_entity (_name ,"Branch_Target_Buffer_Register" #ifdef POSITION ,COMBINATORY #endif ); _interfaces = entity->set_interfaces(); // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { Interface * interface = _interfaces->set_interface("" #ifdef POSITION ,IN ,SOUTH, _("Generalist interface") #endif ); in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES); in_NRESET = interface->set_signal_in ("nreset",1, RESET_VHDL_YES); } // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { ALLOC1_INTERFACE_BEGIN("predict", IN, SOUTH, _("Compute next pc."), _param->_nb_inst_predict); ALLOC1_VALACK_IN ( in_PREDICT_VAL ,VAL); ALLOC1_VALACK_OUT(out_PREDICT_ACK ,ACK); ALLOC1_SIGNAL_IN ( in_PREDICT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); ALLOC1_SIGNAL_IN ( in_PREDICT_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_instruction_address); ALLOC1_INTERFACE_END(_param->_nb_inst_predict); } { ALLOC2_INTERFACE_BEGIN("predict", OUT, SOUTH, _("Compute next pc."), _param->_nb_inst_predict, _param->_associativity); ALLOC2_SIGNAL_OUT(out_PREDICT_HIT ,"hit" ,Tcontrol_t ,1); ALLOC2_SIGNAL_OUT(out_PREDICT_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t ,_param->_size_instruction_address); ALLOC2_SIGNAL_OUT(out_PREDICT_ADDRESS_DEST,"address_dest",Tgeneral_data_t ,_param->_size_instruction_address); ALLOC2_SIGNAL_OUT(out_PREDICT_CONDITION ,"condition" ,Tbranch_condition_t,_param->_size_branch_state); ALLOC2_SIGNAL_OUT(out_PREDICT_LAST_TAKE ,"last_take" ,Tcontrol_t ,1); ALLOC2_SIGNAL_OUT(out_PREDICT_IS_ACCURATE ,"is_accurate" ,Tcontrol_t ,1); ALLOC2_INTERFACE_END(_param->_nb_inst_predict, _param->_associativity); } // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { ALLOC1_INTERFACE_BEGIN("decod", IN, SOUTH, _("decod instruction"), _param->_nb_inst_decod); ALLOC1_VALACK_IN ( in_DECOD_VAL ,VAL); ALLOC1_VALACK_OUT(out_DECOD_ACK ,ACK); if (_param->_have_port_victim) { ALLOC1_SIGNAL_OUT(out_DECOD_HIT ,"hit" ,Tcontrol_t ,1); ALLOC1_SIGNAL_OUT(out_DECOD_HIT_INDEX ,"hit_index" ,Tptr_t ,_param->_size_victim); ALLOC1_SIGNAL_IN ( in_DECOD_VICTIM ,"victim" ,Tptr_t ,_param->_size_victim); } ALLOC1_SIGNAL_IN ( in_DECOD_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); ALLOC1_SIGNAL_IN ( in_DECOD_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t ,_param->_size_instruction_address); ALLOC1_SIGNAL_IN ( in_DECOD_ADDRESS_DEST ,"address_dest" ,Tgeneral_data_t ,_param->_size_instruction_address); ALLOC1_SIGNAL_IN ( in_DECOD_CONDITION ,"condition" ,Tbranch_condition_t,_param->_size_branch_state); ALLOC1_SIGNAL_IN ( in_DECOD_LAST_TAKE ,"last_take" ,Tcontrol_t ,1); ALLOC1_SIGNAL_IN ( in_DECOD_MISS_PREDICTION,"miss_prediction",Tcontrol_t ,1); ALLOC1_SIGNAL_IN ( in_DECOD_IS_ACCURATE ,"is_accurate" ,Tcontrol_t ,1); ALLOC1_INTERFACE_END(_param->_nb_inst_decod); } // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { ALLOC1_INTERFACE_BEGIN("update", IN, SOUTH, _("update instruction"), _param->_nb_inst_update); ALLOC1_VALACK_IN ( in_UPDATE_VAL ,VAL); ALLOC1_VALACK_OUT(out_UPDATE_ACK ,ACK); if (_param->_have_port_victim) { ALLOC1_SIGNAL_OUT(out_UPDATE_HIT ,"hit" ,Tcontrol_t ,1); ALLOC1_SIGNAL_OUT(out_UPDATE_HIT_INDEX ,"hit_index" ,Tptr_t ,_param->_size_victim); ALLOC1_SIGNAL_IN ( in_UPDATE_VICTIM ,"victim" ,Tptr_t ,_param->_size_victim); } ALLOC1_SIGNAL_IN ( in_UPDATE_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t ,_param->_size_instruction_address); ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS_DEST ,"address_dest" ,Tgeneral_data_t ,_param->_size_instruction_address); ALLOC1_SIGNAL_IN ( in_UPDATE_CONDITION ,"condition" ,Tbranch_condition_t,_param->_size_branch_state); ALLOC1_SIGNAL_IN ( in_UPDATE_LAST_TAKE ,"last_take" ,Tcontrol_t ,1); ALLOC1_SIGNAL_IN ( in_UPDATE_MISS_PREDICTION,"miss_prediction",Tcontrol_t ,1); ALLOC1_INTERFACE_END(_param->_nb_inst_update); } if (usage_is_set(_usage,USE_SYSTEMC)) { // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ALLOC2(reg_BTB,btb_entry_t,_param->_size_bank,_param->_associativity); ALLOC1(internal_DECOD_ACK ,Tcontrol_t,_param->_nb_inst_decod ); ALLOC1(internal_DECOD_HIT ,Tcontrol_t,_param->_nb_inst_decod ); ALLOC1(internal_DECOD_NUM_BANK ,uint32_t ,_param->_nb_inst_decod ); ALLOC1(internal_DECOD_NUM_ENTRY ,uint32_t ,_param->_nb_inst_decod ); ALLOC1(internal_UPDATE_ACK ,Tcontrol_t,_param->_nb_inst_update); ALLOC1(internal_UPDATE_HIT ,Tcontrol_t,_param->_nb_inst_update); ALLOC1(internal_UPDATE_NUM_BANK ,uint32_t ,_param->_nb_inst_update); ALLOC1(internal_UPDATE_NUM_ENTRY,uint32_t ,_param->_nb_inst_update); } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ #ifdef POSITION if (usage_is_set(_usage,USE_POSITION)) _component->generate_file(); #endif log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"End"); }; }; // end namespace branch_target_buffer_register }; // end namespace branch_target_buffer }; // end namespace prediction_unit }; // end namespace front_end }; // end namespace multi_front_end }; // end namespace core }; // end namespace behavioural }; // end namespace morpheo