1 | /* |
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2 | * $Id: Branch_Target_Buffer_Register_allocation.cpp 135 2009-07-17 08:59:05Z rosiere $ |
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3 | * |
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4 | * [ Description ] |
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5 | * |
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6 | */ |
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7 | |
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8 | #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/include/Branch_Target_Buffer_Register.h" |
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9 | #include "Behavioural/include/Allocation.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | namespace core { |
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14 | namespace multi_front_end { |
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15 | namespace front_end { |
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16 | namespace prediction_unit { |
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17 | namespace branch_target_buffer { |
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18 | namespace branch_target_buffer_register { |
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19 | |
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20 | |
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21 | |
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22 | #undef FUNCTION |
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23 | #define FUNCTION "Branch_Target_Buffer_Register::allocation" |
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24 | void Branch_Target_Buffer_Register::allocation ( |
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25 | #ifdef STATISTICS |
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26 | morpheo::behavioural::Parameters_Statistics * param_statistics |
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27 | #else |
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28 | void |
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29 | #endif |
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30 | ) |
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31 | { |
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32 | log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"Begin"); |
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33 | |
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34 | _component = new Component (_usage); |
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35 | |
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36 | Entity * entity = _component->set_entity (_name |
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37 | ,"Branch_Target_Buffer_Register" |
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38 | #ifdef POSITION |
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39 | ,COMBINATORY |
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40 | #endif |
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41 | ); |
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42 | |
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43 | _interfaces = entity->set_interfaces(); |
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44 | |
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45 | // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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46 | { |
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47 | Interface * interface = _interfaces->set_interface("" |
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48 | #ifdef POSITION |
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49 | ,IN |
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50 | ,SOUTH, |
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51 | _("Generalist interface") |
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52 | #endif |
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53 | ); |
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54 | |
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55 | in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES); |
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56 | in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, RESET_VHDL_YES); |
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57 | } |
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58 | |
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59 | // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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60 | { |
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61 | ALLOC1_INTERFACE_BEGIN("predict", IN, SOUTH, _("Compute next pc."), _param->_nb_inst_predict); |
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62 | |
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63 | ALLOC1_VALACK_IN ( in_PREDICT_VAL ,VAL); |
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64 | ALLOC1_VALACK_OUT(out_PREDICT_ACK ,ACK); |
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65 | ALLOC1_SIGNAL_IN ( in_PREDICT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); |
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66 | ALLOC1_SIGNAL_IN ( in_PREDICT_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_instruction_address); |
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67 | |
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68 | ALLOC1_INTERFACE_END(_param->_nb_inst_predict); |
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69 | } |
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70 | { |
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71 | ALLOC2_INTERFACE_BEGIN("predict", OUT, SOUTH, _("Compute next pc."), _param->_nb_inst_predict, _param->_associativity); |
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72 | |
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73 | ALLOC2_SIGNAL_OUT(out_PREDICT_HIT ,"hit" ,Tcontrol_t ,1); |
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74 | ALLOC2_SIGNAL_OUT(out_PREDICT_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t ,_param->_size_instruction_address); |
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75 | ALLOC2_SIGNAL_OUT(out_PREDICT_ADDRESS_DEST,"address_dest",Tgeneral_data_t ,_param->_size_instruction_address); |
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76 | ALLOC2_SIGNAL_OUT(out_PREDICT_CONDITION ,"condition" ,Tbranch_condition_t,_param->_size_branch_condition); |
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77 | ALLOC2_SIGNAL_OUT(out_PREDICT_LAST_TAKE ,"last_take" ,Tcontrol_t ,1); |
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78 | ALLOC2_SIGNAL_OUT(out_PREDICT_IS_ACCURATE ,"is_accurate" ,Tcontrol_t ,1); |
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79 | |
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80 | ALLOC2_INTERFACE_END(_param->_nb_inst_predict, _param->_associativity); |
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81 | } |
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82 | |
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83 | // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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84 | { |
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85 | ALLOC1_INTERFACE_BEGIN("decod", IN, SOUTH, _("decod instruction"), _param->_nb_inst_decod); |
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86 | |
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87 | ALLOC1_VALACK_IN ( in_DECOD_VAL ,VAL); |
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88 | ALLOC1_VALACK_OUT(out_DECOD_ACK ,ACK); |
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89 | if (_param->_have_port_victim) |
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90 | { |
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91 | ALLOC1_SIGNAL_OUT(out_DECOD_HIT ,"hit" ,Tcontrol_t ,1); |
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92 | ALLOC1_SIGNAL_OUT(out_DECOD_HIT_INDEX ,"hit_index" ,Tptr_t ,_param->_size_victim); |
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93 | ALLOC1_SIGNAL_IN ( in_DECOD_VICTIM ,"victim" ,Tptr_t ,_param->_size_victim); |
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94 | } |
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95 | ALLOC1_SIGNAL_IN ( in_DECOD_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); |
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96 | ALLOC1_SIGNAL_IN ( in_DECOD_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t ,_param->_size_instruction_address); |
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97 | ALLOC1_SIGNAL_IN ( in_DECOD_ADDRESS_DEST ,"address_dest" ,Tgeneral_data_t ,_param->_size_instruction_address); |
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98 | ALLOC1_SIGNAL_IN ( in_DECOD_CONDITION ,"condition" ,Tbranch_condition_t,_param->_size_branch_condition); |
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99 | ALLOC1_SIGNAL_IN ( in_DECOD_LAST_TAKE ,"last_take" ,Tcontrol_t ,1); |
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100 | ALLOC1_SIGNAL_IN ( in_DECOD_MISS_PREDICTION,"miss_prediction",Tcontrol_t ,1); |
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101 | ALLOC1_SIGNAL_IN ( in_DECOD_IS_ACCURATE ,"is_accurate" ,Tcontrol_t ,1); |
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102 | |
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103 | ALLOC1_INTERFACE_END(_param->_nb_inst_decod); |
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104 | } |
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105 | |
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106 | // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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107 | { |
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108 | ALLOC1_INTERFACE_BEGIN("update", IN, SOUTH, _("update instruction"), _param->_nb_inst_update); |
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109 | |
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110 | ALLOC1_VALACK_IN ( in_UPDATE_VAL ,VAL); |
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111 | ALLOC1_VALACK_OUT(out_UPDATE_ACK ,ACK); |
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112 | if (_param->_have_port_victim) |
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113 | { |
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114 | ALLOC1_SIGNAL_OUT(out_UPDATE_HIT ,"hit" ,Tcontrol_t ,1); |
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115 | ALLOC1_SIGNAL_OUT(out_UPDATE_HIT_INDEX ,"hit_index" ,Tptr_t ,_param->_size_victim); |
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116 | ALLOC1_SIGNAL_IN ( in_UPDATE_VICTIM ,"victim" ,Tptr_t ,_param->_size_victim); |
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117 | } |
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118 | ALLOC1_SIGNAL_IN ( in_UPDATE_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); |
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119 | ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t ,_param->_size_instruction_address); |
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120 | ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS_DEST ,"address_dest" ,Tgeneral_data_t ,_param->_size_instruction_address); |
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121 | ALLOC1_SIGNAL_IN ( in_UPDATE_CONDITION ,"condition" ,Tbranch_condition_t,_param->_size_branch_condition); |
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122 | ALLOC1_SIGNAL_IN ( in_UPDATE_LAST_TAKE ,"last_take" ,Tcontrol_t ,1); |
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123 | ALLOC1_SIGNAL_IN ( in_UPDATE_MISS_PREDICTION,"miss_prediction",Tcontrol_t ,1); |
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124 | |
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125 | ALLOC1_INTERFACE_END(_param->_nb_inst_update); |
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126 | } |
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127 | |
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128 | if (usage_is_set(_usage,USE_SYSTEMC)) |
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129 | { |
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130 | // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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131 | ALLOC2(reg_BTB,btb_entry_t,_param->_size_bank,_param->_associativity); |
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132 | |
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133 | ALLOC1(internal_DECOD_ACK ,Tcontrol_t,_param->_nb_inst_decod ); |
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134 | ALLOC1(internal_DECOD_HIT ,Tcontrol_t,_param->_nb_inst_decod ); |
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135 | ALLOC1(internal_DECOD_NUM_BANK ,uint32_t ,_param->_nb_inst_decod ); |
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136 | ALLOC1(internal_DECOD_NUM_ENTRY ,uint32_t ,_param->_nb_inst_decod ); |
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137 | |
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138 | ALLOC1(internal_UPDATE_ACK ,Tcontrol_t,_param->_nb_inst_update); |
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139 | ALLOC1(internal_UPDATE_HIT ,Tcontrol_t,_param->_nb_inst_update); |
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140 | ALLOC1(internal_UPDATE_NUM_BANK ,uint32_t ,_param->_nb_inst_update); |
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141 | ALLOC1(internal_UPDATE_NUM_ENTRY,uint32_t ,_param->_nb_inst_update); |
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142 | } |
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143 | |
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144 | // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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145 | |
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146 | #ifdef POSITION |
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147 | if (usage_is_set(_usage,USE_POSITION)) |
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148 | _component->generate_file(); |
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149 | #endif |
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150 | |
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151 | log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"End"); |
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152 | }; |
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153 | |
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154 | }; // end namespace branch_target_buffer_register |
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155 | }; // end namespace branch_target_buffer |
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156 | }; // end namespace prediction_unit |
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157 | }; // end namespace front_end |
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158 | }; // end namespace multi_front_end |
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159 | }; // end namespace core |
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160 | |
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161 | }; // end namespace behavioural |
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162 | }; // end namespace morpheo |
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