[78] | 1 | #ifdef SYSTEMC |
---|
| 2 | /* |
---|
| 3 | * $Id: Branch_Target_Buffer_Register_transition.cpp 88 2008-12-10 18:31:39Z rosiere $ |
---|
| 4 | * |
---|
| 5 | * [ Description ] |
---|
| 6 | * |
---|
| 7 | */ |
---|
| 8 | |
---|
| 9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/include/Branch_Target_Buffer_Register.h" |
---|
| 10 | |
---|
| 11 | namespace morpheo { |
---|
| 12 | namespace behavioural { |
---|
| 13 | namespace core { |
---|
| 14 | namespace multi_front_end { |
---|
| 15 | namespace front_end { |
---|
| 16 | namespace prediction_unit { |
---|
| 17 | namespace branch_target_buffer { |
---|
| 18 | namespace branch_target_buffer_register { |
---|
| 19 | |
---|
| 20 | #undef FUNCTION |
---|
| 21 | #define FUNCTION "Branch_Target_Buffer_Register::transition" |
---|
| 22 | void Branch_Target_Buffer_Register::transition (void) |
---|
| 23 | { |
---|
[88] | 24 | log_begin(Branch_Target_Buffer_Register,FUNCTION); |
---|
| 25 | log_function(Branch_Target_Buffer_Register,FUNCTION,_name.c_str()); |
---|
[78] | 26 | |
---|
| 27 | if (PORT_READ(in_NRESET) == 0) |
---|
| 28 | { |
---|
| 29 | for (uint32_t i=0; i<_param->_size_bank; i++) |
---|
| 30 | for (uint32_t j=0; j<_param->_associativity; j++) |
---|
| 31 | reg_BTB [i][j]._val = false; |
---|
| 32 | } |
---|
| 33 | else |
---|
| 34 | { |
---|
[82] | 35 | if (not _param->_have_port_victim) |
---|
| 36 | { |
---|
| 37 | genMealy_decod (); |
---|
| 38 | genMealy_update (); |
---|
| 39 | } |
---|
| 40 | |
---|
[78] | 41 | // ======================================================= |
---|
| 42 | // =====[ PREDICT ]======================================= |
---|
| 43 | // ======================================================= |
---|
| 44 | |
---|
| 45 | // ======================================================= |
---|
| 46 | // =====[ DECOD ]========================================= |
---|
| 47 | // ======================================================= |
---|
| 48 | for (uint32_t i=0; i<_param->_nb_inst_decod; i++) |
---|
| 49 | if (PORT_READ(in_DECOD_VAL [i]) and internal_DECOD_ACK [i]) |
---|
| 50 | { |
---|
| 51 | bool hit = internal_DECOD_HIT [i]; |
---|
| 52 | // uint32_t num_bank = internal_DECOD_NUM_BANK [i]; |
---|
| 53 | // uint32_t num_entry = (hit)?internal_DECOD_NUM_ENTRY [i]:((_param->_have_port_victim)?PORT_READ(in_DECOD_VICTIM [i]):0); |
---|
| 54 | |
---|
| 55 | // detect new branch !!! insert in branch target buffer |
---|
| 56 | if (not hit) |
---|
| 57 | { |
---|
| 58 | // =====[ Miss Case ] |
---|
| 59 | uint32_t num_bank = internal_DECOD_NUM_BANK [i]; |
---|
| 60 | uint32_t num_entry = (_param->_have_port_victim)?PORT_READ(in_DECOD_VICTIM [i]):0; |
---|
| 61 | |
---|
| 62 | // dest_val if not jr or jalr |
---|
| 63 | Tbranch_condition_t cond = PORT_READ(in_DECOD_CONDITION [i]); |
---|
| 64 | bool dest_val = not ((cond == BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK) or |
---|
| 65 | (cond == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK ) or |
---|
| 66 | (cond == BRANCH_CONDITION_READ_STACK )); |
---|
| 67 | |
---|
| 68 | reg_BTB[num_bank][num_entry]._val = 1; |
---|
| 69 | reg_BTB[num_bank][num_entry]._context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0; |
---|
| 70 | reg_BTB[num_bank][num_entry]._address_src = PORT_READ(in_DECOD_ADDRESS_SRC [i]); |
---|
| 71 | reg_BTB[num_bank][num_entry]._address_dest = PORT_READ(in_DECOD_ADDRESS_DEST [i]); |
---|
| 72 | reg_BTB[num_bank][num_entry]._address_dest_val = dest_val; |
---|
| 73 | reg_BTB[num_bank][num_entry]._condition = cond; |
---|
| 74 | reg_BTB[num_bank][num_entry]._last_take = PORT_READ(in_DECOD_LAST_TAKE [i]); |
---|
[82] | 75 | reg_BTB[num_bank][num_entry]._accurate = (PORT_READ(in_DECOD_IS_ACCURATE [i]))?_param->_first_accurate_if_hit:_param->_first_accurate_if_miss; |
---|
[78] | 76 | } |
---|
| 77 | // else (hit) : no update -> it's not the last result of the branch |
---|
| 78 | } |
---|
| 79 | |
---|
| 80 | // ======================================================= |
---|
| 81 | // =====[ UPDATE ]========================================= |
---|
| 82 | // ======================================================= |
---|
| 83 | for (uint32_t i=0; i<_param->_nb_inst_update; i++) |
---|
| 84 | if (PORT_READ(in_UPDATE_VAL [i]) and internal_UPDATE_ACK [i]) |
---|
| 85 | { |
---|
[88] | 86 | log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * UPDATE [%d]",i); |
---|
| 87 | |
---|
[78] | 88 | bool hit = internal_UPDATE_HIT [i]; |
---|
| 89 | uint32_t num_bank = internal_UPDATE_NUM_BANK [i]; |
---|
| 90 | uint32_t num_entry = (hit)?internal_UPDATE_NUM_ENTRY [i]:((_param->_have_port_victim)?PORT_READ(in_UPDATE_VICTIM [i]):0); |
---|
| 91 | bool miss_pred = PORT_READ(in_UPDATE_MISS_PREDICTION [i]); |
---|
| 92 | |
---|
| 93 | // detect new branch !!! insert in branch target buffer |
---|
[88] | 94 | log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * hit : %d",hit); |
---|
| 95 | log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * num_bank : %d",num_bank ); |
---|
| 96 | log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * num_entry : %d",num_entry); |
---|
| 97 | |
---|
[78] | 98 | Tcounter_t accurate_new = 0; |
---|
| 99 | |
---|
| 100 | if (hit) |
---|
| 101 | { |
---|
| 102 | // =====[ Hit Case ] |
---|
| 103 | // * Have destination |
---|
| 104 | // * if cond == read_register or read_stack : destination valid in commit stage |
---|
| 105 | // * if cond != read_register or read_stack : destination valid in decod stage |
---|
| 106 | // * in all case : is valid in this step |
---|
| 107 | Tcounter_t accurate_old = reg_BTB[num_bank][num_entry]._accurate; |
---|
| 108 | // hit : increase accurate |
---|
| 109 | // miss : decrease accurate |
---|
| 110 | Tcounter_t accurate_new = (miss_pred)?((accurate_old>0)?(accurate_old-1):accurate_old):((accurate_old<_param->_accurate_max)?(accurate_old+1):accurate_old); |
---|
| 111 | |
---|
| 112 | // test if accurate go to the threshold |
---|
| 113 | if ((accurate_old >= _param->_accurate_limit) and |
---|
| 114 | (accurate_new < _param->_accurate_limit)) |
---|
| 115 | accurate_new = 0; |
---|
| 116 | |
---|
| 117 | //reg_BTB[num_bank][num_entry]._val : no update because hit |
---|
| 118 | //reg_BTB[num_bank][num_entry]._context : no update because hit |
---|
| 119 | //reg_BTB[num_bank][num_entry]._address_src : no update because hit |
---|
| 120 | //reg_BTB[num_bank][num_entry]._condition : no update because hit |
---|
| 121 | } |
---|
| 122 | else |
---|
| 123 | { |
---|
| 124 | // =====[ Miss Case ] |
---|
| 125 | //reg_BTB[num_bank][num_entry]._val = 1; |
---|
| 126 | //reg_BTB[num_bank][num_entry]._context = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0; |
---|
| 127 | //reg_BTB[num_bank][num_entry]._address_src = PORT_READ(in_UPDATE_ADDRESS_SRC [i]); |
---|
| 128 | //reg_BTB[num_bank][num_entry]._condition = PORT_READ(in_UPDATE_CONDITION [i]); |
---|
| 129 | |
---|
| 130 | accurate_new = (miss_pred)?_param->_first_accurate_if_miss:_param->_first_accurate_if_hit; |
---|
[82] | 131 | |
---|
[88] | 132 | // reg_BTB[num_bank][num_entry]._val = 1; |
---|
| 133 | // reg_BTB[num_bank][num_entry]._context = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0; |
---|
| 134 | // reg_BTB[num_bank][num_entry]._address_src = PORT_READ(in_UPDATE_ADDRESS_SRC [i]); |
---|
| 135 | // reg_BTB[num_bank][num_entry]._condition = PORT_READ(in_UPDATE_CONDITION [i]); |
---|
| 136 | // reg_BTB[num_bank][num_entry]._last_take = PORT_READ(in_UPDATE_LAST_TAKE [i]); |
---|
| 137 | reg_BTB[num_bank][num_entry]._address_dest_val = 0; |
---|
| 138 | } |
---|
[78] | 139 | |
---|
| 140 | // =====[ All Case ] |
---|
[88] | 141 | // if (reg_BTB[num_bank][num_entry]._address_dest_val == 0) |
---|
| 142 | // { |
---|
| 143 | // reg_BTB[num_bank][num_entry]._address_dest_val = 1; |
---|
| 144 | // reg_BTB[num_bank][num_entry]._address_dest = PORT_READ(in_UPDATE_ADDRESS_DEST [i]); |
---|
| 145 | // } |
---|
| 146 | reg_BTB[num_bank][num_entry]._val = 1; |
---|
| 147 | reg_BTB[num_bank][num_entry]._context = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0; |
---|
| 148 | reg_BTB[num_bank][num_entry]._address_src = PORT_READ(in_UPDATE_ADDRESS_SRC [i]); |
---|
| 149 | reg_BTB[num_bank][num_entry]._condition = PORT_READ(in_UPDATE_CONDITION [i]); |
---|
| 150 | reg_BTB[num_bank][num_entry]._last_take = PORT_READ(in_UPDATE_LAST_TAKE [i]); |
---|
| 151 | reg_BTB[num_bank][num_entry]._address_dest_val = 1; |
---|
| 152 | reg_BTB[num_bank][num_entry]._address_dest = PORT_READ(in_UPDATE_ADDRESS_DEST [i]); |
---|
[78] | 153 | reg_BTB[num_bank][num_entry]._accurate = accurate_new; |
---|
| 154 | } |
---|
| 155 | |
---|
[88] | 156 | #if (DEBUG >= DEBUG_TRACE) and DEBUG_Branch_Target_Buffer_Register |
---|
| 157 | log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * Dump BTB"); |
---|
[78] | 158 | for (uint32_t i=0; i<_param->_size_bank; i++) |
---|
| 159 | for (uint32_t j=0; j<_param->_associativity; j++) |
---|
[88] | 160 | log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," [%.4d][%.4d] %d - %.4d %.8x (%.8x) %.1d %.8x (%.8x) %.3d %.1d %.4d", |
---|
[78] | 161 | i,j, |
---|
| 162 | reg_BTB [i][j]._val , |
---|
| 163 | reg_BTB [i][j]._context , |
---|
| 164 | reg_BTB [i][j]._address_src , |
---|
[88] | 165 | reg_BTB [i][j]._address_src <<2, |
---|
[78] | 166 | reg_BTB [i][j]._address_dest_val, |
---|
| 167 | reg_BTB [i][j]._address_dest , |
---|
[88] | 168 | reg_BTB [i][j]._address_dest<<2 , |
---|
[78] | 169 | reg_BTB [i][j]._condition , |
---|
| 170 | reg_BTB [i][j]._last_take , |
---|
| 171 | reg_BTB [i][j]._accurate ); |
---|
[88] | 172 | #endif |
---|
[78] | 173 | } |
---|
[88] | 174 | |
---|
[78] | 175 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
---|
| 176 | end_cycle (); |
---|
| 177 | #endif |
---|
| 178 | |
---|
[88] | 179 | log_end(Branch_Target_Buffer_Register,FUNCTION); |
---|
[78] | 180 | }; |
---|
| 181 | |
---|
| 182 | }; // end namespace branch_target_buffer_register |
---|
| 183 | }; // end namespace branch_target_buffer |
---|
| 184 | }; // end namespace prediction_unit |
---|
| 185 | }; // end namespace front_end |
---|
| 186 | }; // end namespace multi_front_end |
---|
| 187 | }; // end namespace core |
---|
| 188 | |
---|
| 189 | }; // end namespace behavioural |
---|
| 190 | }; // end namespace morpheo |
---|
| 191 | #endif |
---|