1 | #ifdef SYSTEMC |
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2 | /* |
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3 | * $Id: Branch_Target_Buffer_Register_transition.cpp 82 2008-05-01 16:48:45Z rosiere $ |
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4 | * |
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5 | * [ Description ] |
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6 | * |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/include/Branch_Target_Buffer_Register.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | namespace core { |
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14 | namespace multi_front_end { |
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15 | namespace front_end { |
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16 | namespace prediction_unit { |
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17 | namespace branch_target_buffer { |
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18 | namespace branch_target_buffer_register { |
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19 | |
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20 | #undef FUNCTION |
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21 | #define FUNCTION "Branch_Target_Buffer_Register::transition" |
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22 | void Branch_Target_Buffer_Register::transition (void) |
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23 | { |
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24 | log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"Begin"); |
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25 | |
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26 | if (PORT_READ(in_NRESET) == 0) |
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27 | { |
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28 | for (uint32_t i=0; i<_param->_size_bank; i++) |
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29 | for (uint32_t j=0; j<_param->_associativity; j++) |
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30 | reg_BTB [i][j]._val = false; |
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31 | } |
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32 | else |
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33 | { |
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34 | if (not _param->_have_port_victim) |
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35 | { |
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36 | genMealy_decod (); |
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37 | genMealy_update (); |
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38 | } |
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39 | |
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40 | // ======================================================= |
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41 | // =====[ PREDICT ]======================================= |
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42 | // ======================================================= |
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43 | |
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44 | // ======================================================= |
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45 | // =====[ DECOD ]========================================= |
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46 | // ======================================================= |
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47 | for (uint32_t i=0; i<_param->_nb_inst_decod; i++) |
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48 | if (PORT_READ(in_DECOD_VAL [i]) and internal_DECOD_ACK [i]) |
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49 | { |
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50 | bool hit = internal_DECOD_HIT [i]; |
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51 | // uint32_t num_bank = internal_DECOD_NUM_BANK [i]; |
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52 | // uint32_t num_entry = (hit)?internal_DECOD_NUM_ENTRY [i]:((_param->_have_port_victim)?PORT_READ(in_DECOD_VICTIM [i]):0); |
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53 | |
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54 | // detect new branch !!! insert in branch target buffer |
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55 | if (not hit) |
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56 | { |
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57 | // =====[ Miss Case ] |
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58 | uint32_t num_bank = internal_DECOD_NUM_BANK [i]; |
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59 | uint32_t num_entry = (_param->_have_port_victim)?PORT_READ(in_DECOD_VICTIM [i]):0; |
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60 | |
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61 | // dest_val if not jr or jalr |
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62 | Tbranch_condition_t cond = PORT_READ(in_DECOD_CONDITION [i]); |
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63 | bool dest_val = not ((cond == BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK) or |
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64 | (cond == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK ) or |
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65 | (cond == BRANCH_CONDITION_READ_STACK )); |
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66 | |
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67 | reg_BTB[num_bank][num_entry]._val = 1; |
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68 | reg_BTB[num_bank][num_entry]._context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0; |
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69 | reg_BTB[num_bank][num_entry]._address_src = PORT_READ(in_DECOD_ADDRESS_SRC [i]); |
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70 | reg_BTB[num_bank][num_entry]._address_dest = PORT_READ(in_DECOD_ADDRESS_DEST [i]); |
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71 | reg_BTB[num_bank][num_entry]._address_dest_val = dest_val; |
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72 | reg_BTB[num_bank][num_entry]._condition = cond; |
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73 | reg_BTB[num_bank][num_entry]._last_take = PORT_READ(in_DECOD_LAST_TAKE [i]); |
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74 | reg_BTB[num_bank][num_entry]._accurate = (PORT_READ(in_DECOD_IS_ACCURATE [i]))?_param->_first_accurate_if_hit:_param->_first_accurate_if_miss; |
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75 | } |
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76 | // else (hit) : no update -> it's not the last result of the branch |
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77 | } |
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78 | |
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79 | // ======================================================= |
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80 | // =====[ UPDATE ]========================================= |
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81 | // ======================================================= |
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82 | for (uint32_t i=0; i<_param->_nb_inst_update; i++) |
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83 | if (PORT_READ(in_UPDATE_VAL [i]) and internal_UPDATE_ACK [i]) |
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84 | { |
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85 | bool hit = internal_UPDATE_HIT [i]; |
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86 | uint32_t num_bank = internal_UPDATE_NUM_BANK [i]; |
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87 | uint32_t num_entry = (hit)?internal_UPDATE_NUM_ENTRY [i]:((_param->_have_port_victim)?PORT_READ(in_UPDATE_VICTIM [i]):0); |
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88 | bool miss_pred = PORT_READ(in_UPDATE_MISS_PREDICTION [i]); |
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89 | |
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90 | // detect new branch !!! insert in branch target buffer |
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91 | Tcounter_t accurate_new = 0; |
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92 | |
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93 | if (hit) |
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94 | { |
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95 | // =====[ Hit Case ] |
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96 | // * Have destination |
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97 | // * if cond == read_register or read_stack : destination valid in commit stage |
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98 | // * if cond != read_register or read_stack : destination valid in decod stage |
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99 | // * in all case : is valid in this step |
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100 | Tcounter_t accurate_old = reg_BTB[num_bank][num_entry]._accurate; |
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101 | // hit : increase accurate |
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102 | // miss : decrease accurate |
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103 | Tcounter_t accurate_new = (miss_pred)?((accurate_old>0)?(accurate_old-1):accurate_old):((accurate_old<_param->_accurate_max)?(accurate_old+1):accurate_old); |
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104 | |
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105 | // test if accurate go to the threshold |
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106 | if ((accurate_old >= _param->_accurate_limit) and |
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107 | (accurate_new < _param->_accurate_limit)) |
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108 | accurate_new = 0; |
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109 | |
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110 | //reg_BTB[num_bank][num_entry]._val : no update because hit |
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111 | //reg_BTB[num_bank][num_entry]._context : no update because hit |
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112 | //reg_BTB[num_bank][num_entry]._address_src : no update because hit |
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113 | //reg_BTB[num_bank][num_entry]._condition : no update because hit |
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114 | } |
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115 | else |
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116 | { |
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117 | // =====[ Miss Case ] |
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118 | //reg_BTB[num_bank][num_entry]._val = 1; |
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119 | //reg_BTB[num_bank][num_entry]._context = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0; |
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120 | //reg_BTB[num_bank][num_entry]._address_src = PORT_READ(in_UPDATE_ADDRESS_SRC [i]); |
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121 | //reg_BTB[num_bank][num_entry]._condition = PORT_READ(in_UPDATE_CONDITION [i]); |
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122 | |
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123 | accurate_new = (miss_pred)?_param->_first_accurate_if_miss:_param->_first_accurate_if_hit; |
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124 | |
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125 | reg_BTB[num_bank][num_entry]._val = 1; |
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126 | reg_BTB[num_bank][num_entry]._context = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0; |
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127 | reg_BTB[num_bank][num_entry]._address_src = PORT_READ(in_UPDATE_ADDRESS_SRC [i]); |
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128 | reg_BTB[num_bank][num_entry]._condition = PORT_READ(in_UPDATE_CONDITION [i]); |
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129 | reg_BTB[num_bank][num_entry]._last_take = PORT_READ(in_UPDATE_LAST_TAKE [i]); |
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130 | } |
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131 | |
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132 | // =====[ All Case ] |
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133 | if (reg_BTB[num_bank][num_entry]._address_dest_val == 0) |
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134 | { |
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135 | reg_BTB[num_bank][num_entry]._address_dest_val = 1; |
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136 | reg_BTB[num_bank][num_entry]._address_dest = PORT_READ(in_UPDATE_ADDRESS_DEST [i]); |
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137 | } |
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138 | reg_BTB[num_bank][num_entry]._accurate = accurate_new; |
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139 | } |
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140 | |
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141 | for (uint32_t i=0; i<_param->_size_bank; i++) |
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142 | for (uint32_t j=0; j<_param->_associativity; j++) |
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143 | log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"[%.4d][%.4d] %d - %.2d %.8x %.1d %.8x %.3d %.1d %.4d", |
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144 | i,j, |
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145 | reg_BTB [i][j]._val , |
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146 | reg_BTB [i][j]._context , |
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147 | reg_BTB [i][j]._address_src , |
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148 | reg_BTB [i][j]._address_dest_val, |
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149 | reg_BTB [i][j]._address_dest , |
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150 | reg_BTB [i][j]._condition , |
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151 | reg_BTB [i][j]._last_take , |
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152 | reg_BTB [i][j]._accurate ); |
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153 | } |
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154 | |
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155 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
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156 | end_cycle (); |
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157 | #endif |
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158 | |
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159 | log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"End"); |
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160 | }; |
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161 | |
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162 | }; // end namespace branch_target_buffer_register |
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163 | }; // end namespace branch_target_buffer |
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164 | }; // end namespace prediction_unit |
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165 | }; // end namespace front_end |
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166 | }; // end namespace multi_front_end |
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167 | }; // end namespace core |
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168 | |
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169 | }; // end namespace behavioural |
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170 | }; // end namespace morpheo |
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171 | #endif |
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