1 | #ifdef SYSTEMC |
---|
2 | /* |
---|
3 | * $Id: Branch_Target_Buffer_Register_transition.cpp 128 2009-06-26 08:43:23Z rosiere $ |
---|
4 | * |
---|
5 | * [ Description ] |
---|
6 | * |
---|
7 | */ |
---|
8 | |
---|
9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/include/Branch_Target_Buffer_Register.h" |
---|
10 | |
---|
11 | namespace morpheo { |
---|
12 | namespace behavioural { |
---|
13 | namespace core { |
---|
14 | namespace multi_front_end { |
---|
15 | namespace front_end { |
---|
16 | namespace prediction_unit { |
---|
17 | namespace branch_target_buffer { |
---|
18 | namespace branch_target_buffer_register { |
---|
19 | |
---|
20 | #undef FUNCTION |
---|
21 | #define FUNCTION "Branch_Target_Buffer_Register::transition" |
---|
22 | void Branch_Target_Buffer_Register::transition (void) |
---|
23 | { |
---|
24 | log_begin(Branch_Target_Buffer_Register,FUNCTION); |
---|
25 | log_function(Branch_Target_Buffer_Register,FUNCTION,_name.c_str()); |
---|
26 | |
---|
27 | if (PORT_READ(in_NRESET) == 0) |
---|
28 | { |
---|
29 | for (uint32_t i=0; i<_param->_size_bank; i++) |
---|
30 | for (uint32_t j=0; j<_param->_associativity; j++) |
---|
31 | { |
---|
32 | reg_BTB [i][j]._val = false; |
---|
33 | reg_BTB [i][j]._context = 0; // not necessary |
---|
34 | reg_BTB [i][j]._address_dest_val = 0; // not necessary |
---|
35 | reg_BTB [i][j]._address_src = 0; // not necessary |
---|
36 | reg_BTB [i][j]._address_dest = 0; // not necessary |
---|
37 | reg_BTB [i][j]._condition = 0; // not necessary |
---|
38 | reg_BTB [i][j]._last_take = 0; // not necessary |
---|
39 | reg_BTB [i][j]._accurate = 0; // not necessary |
---|
40 | } |
---|
41 | } |
---|
42 | else |
---|
43 | { |
---|
44 | if (not _param->_have_port_victim) |
---|
45 | { |
---|
46 | genMealy_decod (); |
---|
47 | genMealy_update (); |
---|
48 | } |
---|
49 | |
---|
50 | // ======================================================= |
---|
51 | // =====[ PREDICT ]======================================= |
---|
52 | // ======================================================= |
---|
53 | |
---|
54 | // ======================================================= |
---|
55 | // =====[ DECOD ]========================================= |
---|
56 | // ======================================================= |
---|
57 | for (uint32_t i=0; i<_param->_nb_inst_decod; i++) |
---|
58 | if (PORT_READ(in_DECOD_VAL [i]) and internal_DECOD_ACK [i]) |
---|
59 | { |
---|
60 | bool hit = internal_DECOD_HIT [i]; |
---|
61 | // uint32_t num_bank = internal_DECOD_NUM_BANK [i]; |
---|
62 | // uint32_t num_entry = (hit)?internal_DECOD_NUM_ENTRY [i]:((_param->_have_port_victim)?PORT_READ(in_DECOD_VICTIM [i]):0); |
---|
63 | |
---|
64 | // detect new branch !!! insert in branch target buffer |
---|
65 | if (not hit) |
---|
66 | { |
---|
67 | // =====[ Miss Case ] |
---|
68 | uint32_t num_bank = internal_DECOD_NUM_BANK [i]; |
---|
69 | uint32_t num_entry = (_param->_have_port_victim)?PORT_READ(in_DECOD_VICTIM [i]):0; |
---|
70 | |
---|
71 | // dest_val if not jr or jalr |
---|
72 | Tbranch_condition_t cond = PORT_READ(in_DECOD_CONDITION [i]); |
---|
73 | bool dest_val = not ((cond == BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK) or |
---|
74 | (cond == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK ) or |
---|
75 | (cond == BRANCH_CONDITION_READ_STACK )); |
---|
76 | |
---|
77 | reg_BTB[num_bank][num_entry]._val = 1; |
---|
78 | reg_BTB[num_bank][num_entry]._context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0; |
---|
79 | reg_BTB[num_bank][num_entry]._address_src = PORT_READ(in_DECOD_ADDRESS_SRC [i]); |
---|
80 | reg_BTB[num_bank][num_entry]._address_dest = PORT_READ(in_DECOD_ADDRESS_DEST [i]); |
---|
81 | reg_BTB[num_bank][num_entry]._address_dest_val = dest_val; |
---|
82 | reg_BTB[num_bank][num_entry]._condition = cond; |
---|
83 | reg_BTB[num_bank][num_entry]._last_take = PORT_READ(in_DECOD_LAST_TAKE [i]); |
---|
84 | reg_BTB[num_bank][num_entry]._accurate = (PORT_READ(in_DECOD_IS_ACCURATE [i]))?_param->_first_accurate_if_hit:_param->_first_accurate_if_miss; |
---|
85 | } |
---|
86 | // else (hit) : no update -> it's not the last result of the branch |
---|
87 | } |
---|
88 | |
---|
89 | // ======================================================= |
---|
90 | // =====[ UPDATE ]========================================= |
---|
91 | // ======================================================= |
---|
92 | for (uint32_t i=0; i<_param->_nb_inst_update; i++) |
---|
93 | if (PORT_READ(in_UPDATE_VAL [i]) and internal_UPDATE_ACK [i]) |
---|
94 | { |
---|
95 | log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * UPDATE [%d]",i); |
---|
96 | |
---|
97 | bool hit = internal_UPDATE_HIT [i]; |
---|
98 | uint32_t num_bank = internal_UPDATE_NUM_BANK [i]; |
---|
99 | uint32_t num_entry = (hit)?internal_UPDATE_NUM_ENTRY [i]:((_param->_have_port_victim)?PORT_READ(in_UPDATE_VICTIM [i]):0); |
---|
100 | bool miss_pred = PORT_READ(in_UPDATE_MISS_PREDICTION [i]); |
---|
101 | |
---|
102 | // detect new branch !!! insert in branch target buffer |
---|
103 | log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * hit : %d",hit); |
---|
104 | log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * miss_pred : %d",miss_pred); |
---|
105 | log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * num_bank : %d",num_bank ); |
---|
106 | log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * num_entry : %d",num_entry); |
---|
107 | |
---|
108 | Tcounter_t accurate_new = 0; |
---|
109 | |
---|
110 | if (hit) |
---|
111 | { |
---|
112 | // =====[ Hit Case ] |
---|
113 | // * Have destination |
---|
114 | // * if cond == read_register or read_stack : destination valid in commit stage |
---|
115 | // * if cond != read_register or read_stack : destination valid in decod stage |
---|
116 | // * in all case : is valid in this step |
---|
117 | Tcounter_t accurate_old = reg_BTB[num_bank][num_entry]._accurate; |
---|
118 | |
---|
119 | log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * accurate_old : %d",accurate_old); |
---|
120 | |
---|
121 | // hit : increase accurate |
---|
122 | // miss : decrease accurate |
---|
123 | accurate_new = (miss_pred)?((accurate_old>0)?(accurate_old-1):accurate_old):((accurate_old<_param->_accurate_max)?(accurate_old+1):accurate_old); |
---|
124 | |
---|
125 | // test if accurate go to the threshold |
---|
126 | if ((accurate_old >= _param->_accurate_limit) and |
---|
127 | (accurate_new < _param->_accurate_limit)) |
---|
128 | { |
---|
129 | log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * decrease downto the accurate_limid (%d)",_param->_accurate_limit); |
---|
130 | accurate_new = 0; |
---|
131 | } |
---|
132 | |
---|
133 | //reg_BTB[num_bank][num_entry]._val : no update because hit |
---|
134 | //reg_BTB[num_bank][num_entry]._context : no update because hit |
---|
135 | //reg_BTB[num_bank][num_entry]._address_src : no update because hit |
---|
136 | //reg_BTB[num_bank][num_entry]._condition : no update because hit |
---|
137 | } |
---|
138 | else |
---|
139 | { |
---|
140 | // =====[ Miss Case ] |
---|
141 | //reg_BTB[num_bank][num_entry]._val = 1; |
---|
142 | //reg_BTB[num_bank][num_entry]._context = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0; |
---|
143 | //reg_BTB[num_bank][num_entry]._address_src = PORT_READ(in_UPDATE_ADDRESS_SRC [i]); |
---|
144 | //reg_BTB[num_bank][num_entry]._condition = PORT_READ(in_UPDATE_CONDITION [i]); |
---|
145 | |
---|
146 | accurate_new = (miss_pred)?_param->_first_accurate_if_miss:_param->_first_accurate_if_hit; |
---|
147 | |
---|
148 | // reg_BTB[num_bank][num_entry]._val = 1; |
---|
149 | // reg_BTB[num_bank][num_entry]._context = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0; |
---|
150 | // reg_BTB[num_bank][num_entry]._address_src = PORT_READ(in_UPDATE_ADDRESS_SRC [i]); |
---|
151 | // reg_BTB[num_bank][num_entry]._condition = PORT_READ(in_UPDATE_CONDITION [i]); |
---|
152 | // reg_BTB[num_bank][num_entry]._last_take = PORT_READ(in_UPDATE_LAST_TAKE [i]); |
---|
153 | // reg_BTB[num_bank][num_entry]._address_dest_val = 0; |
---|
154 | } |
---|
155 | |
---|
156 | // =====[ All Case ] |
---|
157 | // if (reg_BTB[num_bank][num_entry]._address_dest_val == 0) |
---|
158 | // { |
---|
159 | // reg_BTB[num_bank][num_entry]._address_dest_val = 1; |
---|
160 | // reg_BTB[num_bank][num_entry]._address_dest = PORT_READ(in_UPDATE_ADDRESS_DEST [i]); |
---|
161 | // } |
---|
162 | |
---|
163 | log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * accurate_new : %d",accurate_new); |
---|
164 | |
---|
165 | reg_BTB[num_bank][num_entry]._val = 1; |
---|
166 | reg_BTB[num_bank][num_entry]._context = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0; |
---|
167 | reg_BTB[num_bank][num_entry]._address_src = PORT_READ(in_UPDATE_ADDRESS_SRC [i]); |
---|
168 | reg_BTB[num_bank][num_entry]._condition = PORT_READ(in_UPDATE_CONDITION [i]); |
---|
169 | reg_BTB[num_bank][num_entry]._last_take = PORT_READ(in_UPDATE_LAST_TAKE [i]); |
---|
170 | reg_BTB[num_bank][num_entry]._address_dest_val = 1; |
---|
171 | reg_BTB[num_bank][num_entry]._address_dest = PORT_READ(in_UPDATE_ADDRESS_DEST [i]); |
---|
172 | reg_BTB[num_bank][num_entry]._accurate = accurate_new; |
---|
173 | } |
---|
174 | |
---|
175 | #if (DEBUG >= DEBUG_TRACE) and DEBUG_Branch_Target_Buffer_Register |
---|
176 | log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * Dump BTB"); |
---|
177 | for (uint32_t i=0; i<_param->_size_bank; i++) |
---|
178 | for (uint32_t j=0; j<_param->_associativity; j++) |
---|
179 | log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," [%.4d][%.4d] %d - %.4d %.8x (%.8x) %.1d %.8x (%.8x) %.3d %.1d %.4d", |
---|
180 | i,j, |
---|
181 | reg_BTB [i][j]._val , |
---|
182 | reg_BTB [i][j]._context , |
---|
183 | reg_BTB [i][j]._address_src , |
---|
184 | reg_BTB [i][j]._address_src <<2, |
---|
185 | reg_BTB [i][j]._address_dest_val, |
---|
186 | reg_BTB [i][j]._address_dest , |
---|
187 | reg_BTB [i][j]._address_dest<<2 , |
---|
188 | reg_BTB [i][j]._condition , |
---|
189 | reg_BTB [i][j]._last_take , |
---|
190 | reg_BTB [i][j]._accurate ); |
---|
191 | #endif |
---|
192 | } |
---|
193 | |
---|
194 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
---|
195 | end_cycle (); |
---|
196 | #endif |
---|
197 | |
---|
198 | log_end(Branch_Target_Buffer_Register,FUNCTION); |
---|
199 | }; |
---|
200 | |
---|
201 | }; // end namespace branch_target_buffer_register |
---|
202 | }; // end namespace branch_target_buffer |
---|
203 | }; // end namespace prediction_unit |
---|
204 | }; // end namespace front_end |
---|
205 | }; // end namespace multi_front_end |
---|
206 | }; // end namespace core |
---|
207 | |
---|
208 | }; // end namespace behavioural |
---|
209 | }; // end namespace morpheo |
---|
210 | #endif |
---|