1 | #ifdef SYSTEMC |
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2 | /* |
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3 | * $Id: Return_Address_Stack_transition.cpp 95 2008-12-16 16:24:26Z rosiere $ |
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4 | * |
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5 | * [ Description ] |
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6 | * |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/include/Return_Address_Stack.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | namespace core { |
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14 | namespace multi_front_end { |
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15 | namespace front_end { |
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16 | namespace prediction_unit { |
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17 | namespace return_address_stack { |
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18 | |
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19 | |
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20 | #undef FUNCTION |
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21 | #define FUNCTION "Return_Address_Stack::transition" |
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22 | void Return_Address_Stack::transition (void) |
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23 | { |
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24 | log_printf(FUNC,Return_Address_Stack,FUNCTION,"Begin"); |
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25 | |
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26 | if (PORT_READ(in_NRESET)==0) |
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27 | { |
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28 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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29 | { |
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30 | reg_TOP [i] = 0; |
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31 | reg_BOTTOM [i] = 0; |
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32 | reg_NB_ELT [i] = 0; |
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33 | |
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34 | reg_PREDICT_TOP [i] = 0; |
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35 | reg_PREDICT_BOTTOM [i] = 0; |
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36 | reg_PREDICT_NB_ELT [i] = 0; |
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37 | |
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38 | for (uint32_t j=0; j<_param->_size_queue [i]; j++) |
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39 | { |
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40 | reg_stack[i][j]._val = false; |
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41 | reg_stack[i][j]._predict = false; |
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42 | reg_stack[i][j]._miss = false; |
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43 | } |
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44 | } |
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45 | } |
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46 | else |
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47 | { |
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48 | // =================================================================== |
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49 | // =====[ PREDICT ]=================================================== |
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50 | // =================================================================== |
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51 | for (uint32_t i=0; i<_param->_nb_inst_predict; i++) |
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52 | if (PORT_READ(in_PREDICT_VAL [i]) and internal_PREDICT_ACK [i]) |
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53 | { |
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54 | log_printf(TRACE,Return_Address_Stack,FUNCTION,"PREDICT[%d] : Transaction",i); |
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55 | Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_PREDICT_CONTEXT_ID [i]):0; |
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56 | Tcontrol_t push = PORT_READ(in_PREDICT_PUSH [i]); |
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57 | Tptr_t top_old = reg_PREDICT_TOP [context]; |
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58 | Tptr_t top_new = top_old; |
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59 | Tptr_t bottom_old = reg_PREDICT_BOTTOM [context]; |
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60 | |
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61 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * context : %d",context); |
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62 | |
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63 | // Hit : push or (val and not miss and not empty) |
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64 | // Miss : ifetch is stall, no update |
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65 | if (internal_PREDICT_HIT [i]) |
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66 | { |
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67 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * before"); |
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68 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_top : %d",reg_PREDICT_TOP [context]); |
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69 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_bottom : %d",reg_PREDICT_BOTTOM [context]); |
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70 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_nb_elt : %d",reg_PREDICT_NB_ELT [context]); |
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71 | |
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72 | if (push) |
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73 | { |
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74 | // push : increase the top (circular) |
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75 | top_new = (top_old+1)%_param->_size_queue[context]; |
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76 | |
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77 | reg_stack [context][top_new]._val = true; // New addr |
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78 | reg_stack [context][top_new]._predict = true; // Is speculative (erase a old addr (or not)) |
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79 | //reg_stack [context][top_new]._miss = ; |
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80 | reg_stack [context][top_new]._address = PORT_READ(in_PREDICT_ADDRESS_PUSH [i]); |
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81 | |
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82 | // the stack is full, erase the most old stack |
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83 | |
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84 | // Test if full |
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85 | if (reg_PREDICT_NB_ELT[context]==_param->_size_queue[context]) |
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86 | reg_PREDICT_BOTTOM [context] = (bottom_old+1)%_param->_size_queue[context]; |
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87 | // A new data is write : the stack is not empty |
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88 | if (reg_PREDICT_NB_ELT[context]< _param->_size_queue[context]) |
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89 | reg_PREDICT_NB_ELT[context]++; |
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90 | } |
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91 | else |
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92 | { |
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93 | // pop |
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94 | // top_new = (top_old==0)?(_param->_size_queue[context]-1):(top_old-1); |
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95 | |
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96 | //reg_stack [context][top_new]._val = ; |
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97 | //reg_stack [context][top_new]._predict = ; |
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98 | //reg_stack [context][top_new]._miss = ; |
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99 | //reg_stack [context][top_new]._address = ; |
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100 | |
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101 | // the stack is empty |
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102 | if (reg_PREDICT_NB_ELT[context]>0) |
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103 | { |
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104 | top_new = (top_old==0)?(_param->_size_queue[context]-1):(top_old-1); |
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105 | reg_PREDICT_NB_ELT[context] --; |
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106 | } |
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107 | } |
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108 | |
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109 | reg_PREDICT_TOP [context] = top_new; |
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110 | |
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111 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * after"); |
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112 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_top : %d",reg_PREDICT_TOP [context]); |
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113 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_bottom : %d",reg_PREDICT_BOTTOM [context]); |
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114 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_nb_elt : %d",reg_PREDICT_NB_ELT [context]); |
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115 | } |
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116 | } |
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117 | |
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118 | // =================================================================== |
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119 | // =====[ DECOD ]===================================================== |
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120 | // =================================================================== |
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121 | for (uint32_t i=0; i<_param->_nb_inst_decod; i++) |
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122 | if (PORT_READ(in_DECOD_VAL [i]) and internal_DECOD_ACK [i]) |
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123 | { |
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124 | log_printf(TRACE,Return_Address_Stack,FUNCTION,"DECOD[%d] : Transaction",i); |
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125 | Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0; |
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126 | Tcontrol_t push = PORT_READ(in_DECOD_PUSH [i]); |
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127 | Tptr_t top_old = reg_TOP [context]; |
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128 | Tptr_t top_new = top_old; |
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129 | Tptr_t bottom_old = reg_BOTTOM [context]; |
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130 | //Tcontrol_t hit = internal_DECOD_HIT [i]; |
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131 | Tcontrol_t miss = PORT_READ(in_DECOD_MISS_PREDICTION [i]); |
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132 | |
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133 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * context : %d",context); |
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134 | |
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135 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * before"); |
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136 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_top : %d",reg_TOP [context]); |
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137 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_bottom : %d",reg_BOTTOM [context]); |
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138 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_nb_elt : %d",reg_NB_ELT [context]); |
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139 | |
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140 | if (push) |
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141 | { |
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142 | // push : increase the top (circular) |
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143 | top_new = (top_old+1)%_param->_size_queue[context]; |
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144 | |
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145 | reg_stack [context][top_new]._val = true; // New address |
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146 | reg_stack [context][top_new]._predict = false; // No speculative |
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147 | reg_stack [context][top_new]._miss = false; |
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148 | reg_stack [context][top_new]._address = PORT_READ(in_DECOD_ADDRESS_PUSH [i]); |
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149 | |
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150 | // Test if full : if true, then icrease the bottom (erase the most old stack) |
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151 | if (reg_NB_ELT[context]==_param->_size_queue[context]) |
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152 | reg_BOTTOM [context] = (bottom_old+1)%_param->_size_queue[context]; |
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153 | // A new data is write : the stack is not empty |
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154 | if (reg_NB_ELT[context]< _param->_size_queue[context]) |
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155 | reg_NB_ELT[context]++; |
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156 | } |
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157 | else |
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158 | { |
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159 | // pop |
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160 | // top_new = (top_old==0)?(_param->_size_queue[context]-1):(top_old-1); |
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161 | |
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162 | //reg_stack [context][top_new]._val = ; |
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163 | //reg_stack [context][top_new]._predict = ; |
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164 | //reg_stack [context][top_new]._miss = ; |
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165 | //reg_stack [context][top_new]._address = ; |
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166 | |
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167 | // the stack is empty |
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168 | if (reg_NB_ELT[context]>0) |
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169 | { |
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170 | top_new = (top_old==0)?(_param->_size_queue[context]-1):(top_old-1); |
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171 | reg_NB_ELT[context] --; |
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172 | } |
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173 | } |
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174 | |
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175 | reg_TOP [context] = top_new; |
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176 | |
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177 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * after"); |
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178 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_top : %d",reg_TOP [context]); |
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179 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_bottom : %d",reg_BOTTOM [context]); |
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180 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_nb_elt : %d",reg_NB_ELT [context]); |
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181 | |
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182 | // have previous miss of ifetch ? |
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183 | // 2 miss : |
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184 | // 1) miss predict : is very limited (local at context), can be update very quickly |
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185 | // 2) miss decod : result is in commit stage ... |
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186 | if (miss) |
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187 | { |
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188 | reg_PREDICT_BOTTOM [context] = reg_BOTTOM [context]; |
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189 | reg_PREDICT_TOP [context] = reg_TOP [context]; |
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190 | reg_PREDICT_NB_ELT [context] = reg_NB_ELT [context]; |
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191 | |
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192 | // Scan full assoc !!! |
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193 | for (uint32_t j=0; j<_param->_size_queue [context]; j++) |
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194 | // Test if this slot is tagged with "predict" : if true, tagged as miss |
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195 | if (reg_stack [context][j]._predict) |
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196 | { |
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197 | reg_stack [context][j]._predict = false; |
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198 | reg_stack [context][j]._miss = true; |
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199 | } |
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200 | } |
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201 | } |
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202 | |
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203 | // =================================================================== |
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204 | // =====[ UPDATE ]=================================================== |
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205 | // =================================================================== |
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206 | for (uint32_t i=0; i<_param->_nb_inst_update; i++) |
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207 | if (PORT_READ(in_UPDATE_VAL [i]) and internal_UPDATE_ACK [i]) |
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208 | { |
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209 | throw ERRORMORPHEO(FUNCTION,"Fonction à implémenter !!!!!!!!!!!!"); |
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210 | |
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211 | |
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212 | // Tcontrol_t miss = PORT_READ(in_UPDATE_MISS_PREDICTION [i]); |
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213 | // // |
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214 | // if (miss) |
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215 | // { |
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216 | // Tcontrol_t context = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0; |
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217 | // Tcontrol_t ifetch = PORT_READ(in_UPDATE_PREDICTION_IFETCH [i]); |
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218 | // Tcontrol_t push = PORT_READ(in_UPDATE_PUSH [i]); |
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219 | // Tcontrol_t flush = PORT_READ(in_UPDATE_FLUSH [i]); |
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220 | // Tptr_t index = PORT_READ(in_UPDATE_INDEX [i]); |
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221 | // Taddress_t address = PORT_READ(in_UPDATE_ADDRESS [i]); |
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222 | |
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223 | // if (push) |
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224 | // { |
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225 | // // // push |
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226 | // // top_new = (top_old+1)%_param->_size_queue[context]; |
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227 | |
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228 | // // reg_stack [context][index]._val = true; |
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229 | // // reg_stack [context][index]._predict = false; |
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230 | // // reg_stack [context][index]._miss = false; |
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231 | // // reg_stack [context][index]._address = PORT_READ(in_UPDATE_ADDRESS [i]); |
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232 | |
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233 | // } |
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234 | // else |
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235 | // { |
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236 | // // //reg_stack [context][top_new]._val = ; |
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237 | // // //reg_stack [context][top_new]._predict = ; |
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238 | // // //reg_stack [context][top_new]._miss = ; |
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239 | // // //reg_stack [context][top_new]._address = ; |
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240 | // } |
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241 | |
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242 | // // // // Mouais bof ....... |
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243 | // // // reg_PREDICT_TOP [context] = index; |
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244 | // } |
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245 | } |
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246 | } |
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247 | |
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248 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
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249 | end_cycle (); |
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250 | #endif |
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251 | |
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252 | log_printf(FUNC,Return_Address_Stack,FUNCTION,"End"); |
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253 | }; |
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254 | |
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255 | }; // end namespace return_address_stack |
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256 | }; // end namespace prediction_unit |
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257 | }; // end namespace front_end |
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258 | }; // end namespace multi_front_end |
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259 | }; // end namespace core |
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260 | |
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261 | }; // end namespace behavioural |
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262 | }; // end namespace morpheo |
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263 | #endif |
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