1 | #ifdef SYSTEMC |
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2 | /* |
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3 | * $Id$ |
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4 | * |
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5 | * [ Description ] |
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6 | * |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/include/Return_Address_Stack.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | namespace core { |
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14 | namespace multi_front_end { |
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15 | namespace front_end { |
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16 | namespace prediction_unit { |
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17 | namespace return_address_stack { |
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18 | |
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19 | |
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20 | #undef FUNCTION |
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21 | #define FUNCTION "Return_Address_Stack::transition" |
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22 | void Return_Address_Stack::transition (void) |
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23 | { |
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24 | log_printf(FUNC,Return_Address_Stack,FUNCTION,"Begin"); |
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25 | |
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26 | if (PORT_READ(in_NRESET)) |
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27 | { |
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28 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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29 | { |
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30 | reg_TOP [i] = 0; |
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31 | reg_BOTTOM [i] = 0; |
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32 | |
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33 | reg_PREDICT_TOP [i] = 0; |
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34 | reg_PREDICT_BOTTOM [i] = 0; |
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35 | |
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36 | for (uint32_t j=0; j<_param->_size_queue [i]; j++) |
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37 | reg_stack[i][j]._val = false; |
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38 | } |
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39 | } |
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40 | else |
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41 | { |
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42 | // =================================================================== |
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43 | // =====[ PREDICT ]=================================================== |
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44 | // =================================================================== |
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45 | for (uint32_t i=0; i<_param->_nb_inst_predict; i++) |
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46 | if (PORT_READ(in_PREDICT_VAL [i]) and internal_PREDICT_ACK [i]) |
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47 | { |
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48 | Tcontrol_t context = (_param->_have_port_context_id)?PORT_READ(in_PREDICT_CONTEXT_ID [i]):0; |
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49 | Tcontrol_t push = PORT_READ(in_PREDICT_PUSH [i]); |
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50 | Tptr_t top_old = reg_PREDICT_TOP [i]; |
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51 | Tptr_t top_new; |
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52 | |
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53 | if (internal_PREDICT_HIT [i]) |
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54 | { |
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55 | if (push) |
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56 | { |
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57 | // push |
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58 | top_new = (top_old+1)%_param->_size_queue[context]; |
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59 | |
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60 | reg_stack [context][top_new]._val = true; // New addr |
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61 | reg_stack [context][top_new]._predict = true; // Is speculative (erase a old addr) |
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62 | //reg_stack [context][top_new]._miss = ; |
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63 | reg_stack [context][top_new]._address = PORT_READ(in_PREDICT_ADDRESS_PUSH [i]); |
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64 | |
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65 | // the stack is full, erase the most old stack |
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66 | if (top_new == reg_PREDICT_BOTTOM [i]) |
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67 | reg_PREDICT_BOTTOM [i] = (reg_PREDICT_BOTTOM [i]+1)%_param->_size_queue[context]; |
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68 | } |
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69 | else |
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70 | { |
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71 | // pop |
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72 | top_new = (top_old==0)?(_param->_size_queue[context]-1):(top_old-1); |
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73 | |
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74 | //reg_stack [context][top_new]._val = ; |
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75 | //reg_stack [context][top_new]._predict = ; |
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76 | //reg_stack [context][top_new]._miss = ; |
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77 | //reg_stack [context][top_new]._address = ; |
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78 | |
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79 | // the stack is empty |
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80 | if (top_old == reg_PREDICT_BOTTOM [i]) |
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81 | reg_PREDICT_BOTTOM [i] = top_new; |
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82 | |
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83 | } |
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84 | |
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85 | reg_PREDICT_TOP [i] = top_new; |
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86 | } |
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87 | } |
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88 | |
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89 | // // =================================================================== |
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90 | // // =====[ DECOD ]===================================================== |
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91 | // // =================================================================== |
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92 | // for (uint32_t i=0; i<_param->_nb_inst_decod; i++) |
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93 | // if (PORT_READ(in_DECOD_VAL [i]) and internal_DECOD_ACK [i]) |
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94 | // { |
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95 | // Tcontrol_t context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0; |
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96 | // Tcontrol_t push = PORT_READ(in_DECOD_PUSH [i]); |
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97 | // Tptr_t top_old = reg_TOP [i]; |
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98 | // Tptr_t top_new; |
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99 | |
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100 | // Tcontrol_t hit = PORT_READ(in_DECOD_HIT [i]); |
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101 | // Tcontrol_t miss = PORT_READ(in_DECOD_MISS_PREDICTION [i]); |
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102 | |
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103 | // if (push) |
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104 | // { |
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105 | // // push |
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106 | // top_new = (top_old+1)%_param->_size_queue[context]; |
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107 | |
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108 | // reg_stack [context][top_new]._val = true; |
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109 | // reg_stack [context][top_new]._predict = false; |
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110 | // reg_stack [context][top_new]._miss = false; |
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111 | // reg_stack [context][top_new]._address = PORT_READ(in_DECOD_ADDRESS_PUSH [i]); |
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112 | |
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113 | // // the stack is full, erase the most old stack |
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114 | // if (top_old == reg_BOTTOM [i]) |
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115 | // reg_BOTTOM [i] = top_new; |
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116 | // } |
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117 | // else |
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118 | // { |
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119 | // // pop |
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120 | // top_new = (top_old==0)?(_param->_size_queue[context]-1):(top_old-1); |
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121 | |
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122 | // //reg_stack [context][top_new]._val = ; |
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123 | // //reg_stack [context][top_new]._predict = ; |
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124 | // //reg_stack [context][top_new]._miss = ; |
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125 | // //reg_stack [context][top_new]._address = ; |
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126 | // } |
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127 | |
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128 | // reg_TOP [i] = top_new; |
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129 | |
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130 | // // have previous miss of ifetch ? |
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131 | // // 2 miss : |
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132 | // // 1) miss predict : is very limited (local at context), can be update very quickly |
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133 | // // 2) miss decod : result is in commit stage ... |
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134 | // if (miss) |
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135 | // { |
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136 | // reg_PREDICT_BOTTOM [i] = reg_BOTTOM [i]; |
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137 | // reg_PREDICT_TOP [i] = reg_TOP [i]; |
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138 | |
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139 | // for (uint32_t j=0; j<_param->_size_queue [i]; j++) |
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140 | // if (reg_stack [context][top_new]._predict) |
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141 | // { |
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142 | // reg_stack [context][top_new]._predict = false; |
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143 | // reg_stack [context][top_new]._miss = true; |
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144 | // } |
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145 | // } |
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146 | // } |
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147 | |
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148 | // =================================================================== |
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149 | // =====[ UPDATE ]=================================================== |
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150 | // =================================================================== |
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151 | for (uint32_t i=0; i<_param->_nb_inst_update; i++) |
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152 | if (PORT_READ(in_UPDATE_VAL [i]) and internal_UPDATE_ACK [i]) |
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153 | { |
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154 | Tcontrol_t context = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0; |
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155 | Tcontrol_t push = PORT_READ(in_UPDATE_PUSH [i]); |
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156 | Tptr_t index = PORT_READ(in_UPDATE_INDEX [i]); |
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157 | |
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158 | if (PORT_READ(in_UPDATE_MISS_PREDICTION [i])) |
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159 | { |
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160 | if (push) |
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161 | { |
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162 | // push |
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163 | top_new = (top_old+1)%_param->_size_queue[context]; |
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164 | |
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165 | reg_stack [context][index]._val = true; |
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166 | reg_stack [context][index]._predict = false; |
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167 | reg_stack [context][index]._miss = false; |
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168 | reg_stack [context][index]._address = PORT_READ(in_UPDATE_ADDRESS [i]); |
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169 | |
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170 | } |
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171 | else |
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172 | { |
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173 | //reg_stack [context][top_new]._val = ; |
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174 | //reg_stack [context][top_new]._predict = ; |
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175 | //reg_stack [context][top_new]._miss = ; |
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176 | //reg_stack [context][top_new]._address = ; |
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177 | } |
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178 | |
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179 | // Mouais bof ....... |
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180 | reg_PREDICT_TOP [i] = index; |
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181 | } |
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182 | } |
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183 | } |
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184 | |
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185 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
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186 | end_cycle (); |
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187 | #endif |
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188 | |
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189 | log_printf(FUNC,Return_Address_Stack,FUNCTION,"End"); |
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190 | }; |
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191 | |
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192 | }; // end namespace return_address_stack |
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193 | }; // end namespace prediction_unit |
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194 | }; // end namespace front_end |
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195 | }; // end namespace multi_front_end |
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196 | }; // end namespace core |
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197 | |
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198 | }; // end namespace behavioural |
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199 | }; // end namespace morpheo |
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200 | #endif |
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