[78] | 1 | /* |
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| 2 | * $Id: test.cpp 101 2009-01-15 17:19:08Z rosiere $ |
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| 3 | * |
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| 4 | * [ Description ] |
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| 5 | * |
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| 6 | * Test |
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| 7 | */ |
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| 8 | |
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[81] | 9 | #define NB_ITERATION 1 |
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[88] | 10 | #define CYCLE_MAX 1000000 |
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[81] | 11 | |
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[78] | 12 | #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/include/test.h" |
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| 13 | #include "Common/include/Test.h" |
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| 14 | #include "Behavioural/include/Allocation.h" |
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| 15 | |
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| 16 | void test (string name, |
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| 17 | morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::Parameters * _param) |
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| 18 | { |
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| 19 | msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); |
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| 20 | |
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| 21 | #ifdef STATISTICS |
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| 22 | morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50); |
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| 23 | #endif |
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| 24 | |
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[88] | 25 | Tusage_t _usage = USE_ALL; |
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| 26 | |
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| 27 | // _usage = usage_unset(_usage,USE_SYSTEMC ); |
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| 28 | // _usage = usage_unset(_usage,USE_VHDL ); |
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| 29 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); |
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| 30 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); |
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| 31 | // _usage = usage_unset(_usage,USE_POSITION ); |
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| 32 | // _usage = usage_unset(_usage,USE_STATISTICS ); |
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| 33 | // _usage = usage_unset(_usage,USE_INFORMATION ); |
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| 34 | |
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[82] | 35 | Prediction_unit * _Prediction_unit = new Prediction_unit |
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| 36 | (name.c_str(), |
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[78] | 37 | #ifdef STATISTICS |
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[82] | 38 | _parameters_statistics, |
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[78] | 39 | #endif |
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[82] | 40 | _param, |
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[88] | 41 | _usage); |
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[78] | 42 | |
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| 43 | #ifdef SYSTEMC |
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| 44 | /********************************************************************* |
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| 45 | * Déclarations des signaux |
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| 46 | *********************************************************************/ |
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| 47 | string rename; |
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| 48 | |
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| 49 | sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); |
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| 50 | sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); |
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[82] | 51 | |
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| 52 | |
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| 53 | ALLOC1_SC_SIGNAL( in_PREDICT_VAL ," in_PREDICT_VAL ",Tcontrol_t ,_param->_nb_context); |
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| 54 | ALLOC1_SC_SIGNAL(out_PREDICT_ACK ,"out_PREDICT_ACK ",Tcontrol_t ,_param->_nb_context); |
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| 55 | ALLOC1_SC_SIGNAL( in_PREDICT_PC_PREVIOUS ," in_PREDICT_PC_PREVIOUS ",Taddress_t ,_param->_nb_context); |
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| 56 | ALLOC1_SC_SIGNAL( in_PREDICT_PC_CURRENT ," in_PREDICT_PC_CURRENT ",Taddress_t ,_param->_nb_context); |
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| 57 | ALLOC1_SC_SIGNAL( in_PREDICT_PC_CURRENT_IS_DS_TAKE ," in_PREDICT_PC_CURRENT_IS_DS_TAKE ",Tcontrol_t ,_param->_nb_context); |
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| 58 | ALLOC1_SC_SIGNAL(out_PREDICT_PC_NEXT ,"out_PREDICT_PC_NEXT ",Taddress_t ,_param->_nb_context); |
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| 59 | ALLOC1_SC_SIGNAL(out_PREDICT_PC_NEXT_IS_DS_TAKE ,"out_PREDICT_PC_NEXT_IS_DS_TAKE ",Tcontrol_t ,_param->_nb_context); |
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[88] | 60 | ALLOC2_SC_SIGNAL(out_PREDICT_INSTRUCTION_ENABLE ,"out_PREDICT_INSTRUCTION_ENABLE ",Tcontrol_t ,_param->_nb_context,_param->_nb_instruction[it1]); |
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[82] | 61 | ALLOC1_SC_SIGNAL(out_PREDICT_INST_IFETCH_PTR ,"out_PREDICT_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t ,_param->_nb_context); |
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| 62 | ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_STATE ,"out_PREDICT_BRANCH_STATE ",Tbranch_state_t ,_param->_nb_context); |
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| 63 | ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"out_PREDICT_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ,_param->_nb_context); |
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| 64 | |
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[88] | 65 | ALLOC2_SC_SIGNAL( in_DECOD_VAL ," in_DECOD_VAL ",Tcontrol_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); |
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| 66 | ALLOC2_SC_SIGNAL(out_DECOD_ACK ,"out_DECOD_ACK ",Tcontrol_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); |
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| 67 | ALLOC2_SC_SIGNAL( in_DECOD_CONTEXT_ID ," in_DECOD_CONTEXT_ID ",Tcontext_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); |
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| 68 | ALLOC2_SC_SIGNAL( in_DECOD_MATCH_INST_IFETCH_PTR ," in_DECOD_MATCH_INST_IFETCH_PTR ",Tcontrol_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); |
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| 69 | ALLOC2_SC_SIGNAL( in_DECOD_BRANCH_STATE ," in_DECOD_BRANCH_STATE ",Tbranch_state_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); |
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| 70 | ALLOC2_SC_SIGNAL( in_DECOD_BRANCH_UPDATE_PREDICTION_ID ," in_DECOD_BRANCH_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); |
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| 71 | ALLOC2_SC_SIGNAL( in_DECOD_BRANCH_CONDITION ," in_DECOD_BRANCH_CONDITION ",Tbranch_condition_t,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); |
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| 72 | ALLOC2_SC_SIGNAL( in_DECOD_BRANCH_DIRECTION ," in_DECOD_BRANCH_DIRECTION ",Tcontrol_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); |
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| 73 | ALLOC2_SC_SIGNAL( in_DECOD_ADDRESS_SRC ," in_DECOD_ADDRESS_SRC ",Taddress_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); |
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| 74 | ALLOC2_SC_SIGNAL( in_DECOD_ADDRESS_DEST ," in_DECOD_ADDRESS_DEST ",Taddress_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); |
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[82] | 75 | |
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| 76 | ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ," in_BRANCH_COMPLETE_VAL ",Tcontrol_t ,_param->_nb_inst_branch_complete); |
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| 77 | ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,"out_BRANCH_COMPLETE_ACK ",Tcontrol_t ,_param->_nb_inst_branch_complete); |
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| 78 | ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ," in_BRANCH_COMPLETE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_branch_complete); |
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| 79 | ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ," in_BRANCH_COMPLETE_DEPTH ",Tdepth_t ,_param->_nb_inst_branch_complete); |
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| 80 | ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ," in_BRANCH_COMPLETE_ADDRESS ",Taddress_t ,_param->_nb_inst_branch_complete); |
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[98] | 81 | ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_NO_SEQUENCE ," in_BRANCH_COMPLETE_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_inst_branch_complete); |
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[82] | 82 | ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION ,"out_BRANCH_COMPLETE_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_inst_branch_complete); |
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| 83 | ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_TAKE ,"out_BRANCH_COMPLETE_TAKE ",Tcontrol_t ,_param->_nb_inst_branch_complete); |
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| 84 | ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_SRC ,"out_BRANCH_COMPLETE_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_branch_complete); |
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| 85 | ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_DEST ,"out_BRANCH_COMPLETE_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_branch_complete); |
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| 86 | |
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| 87 | ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_VAL ,"out_BRANCH_EVENT_VAL ",Tcontrol_t ,_param->_nb_context); |
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| 88 | ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ACK ," in_BRANCH_EVENT_ACK ",Tcontrol_t ,_param->_nb_context); |
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| 89 | //ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_CONTEXT_ID ,"out_BRANCH_EVENT_CONTEXT_ID ",Tcontext_t ,_param->_nb_context); |
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[98] | 90 | ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_DEPTH ,"out_BRANCH_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context); |
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[82] | 91 | //ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_MISS_PREDICTION ,"out_BRANCH_EVENT_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_context); |
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| 92 | ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC ,"out_BRANCH_EVENT_ADDRESS_SRC ",Taddress_t ,_param->_nb_context); |
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[95] | 93 | ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST_VAL ,"out_BRANCH_EVENT_ADDRESS_DEST_VAL ",Tcontrol_t ,_param->_nb_context); |
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[82] | 94 | ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,"out_BRANCH_EVENT_ADDRESS_DEST ",Taddress_t ,_param->_nb_context); |
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| 95 | |
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[97] | 96 | ALLOC1_SC_SIGNAL( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t ,_param->_nb_context); |
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| 97 | ALLOC1_SC_SIGNAL(out_EVENT_ACK ,"out_EVENT_ACK ",Tcontrol_t ,_param->_nb_context); |
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| 98 | ALLOC1_SC_SIGNAL( in_EVENT_TYPE ," in_EVENT_TYPE ",Tevent_type_t ,_param->_nb_context); |
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| 99 | ALLOC1_SC_SIGNAL( in_EVENT_DEPTH ," in_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context); |
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[95] | 100 | |
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[101] | 101 | ALLOC1_SC_SIGNAL(out_DEPTH_VAL ,"out_DEPTH_VAL ",Tcontrol_t ,_param->_nb_context); |
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[88] | 102 | ALLOC1_SC_SIGNAL(out_DEPTH_CURRENT ,"out_DEPTH_CURRENT ",Tdepth_t ,_param->_nb_context); |
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| 103 | ALLOC1_SC_SIGNAL(out_DEPTH_MIN ,"out_DEPTH_MIN ",Tdepth_t ,_param->_nb_context); |
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| 104 | ALLOC1_SC_SIGNAL(out_DEPTH_MAX ,"out_DEPTH_MAX ",Tdepth_t ,_param->_nb_context); |
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[101] | 105 | ALLOC1_SC_SIGNAL(out_DEPTH_FULL ,"out_DEPTH_FULL ",Tcontrol_t ,_param->_nb_context); |
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[78] | 106 | |
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| 107 | /******************************************************** |
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| 108 | * Instanciation |
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| 109 | ********************************************************/ |
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| 110 | |
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| 111 | msg(_("<%s> : Instanciation of _Prediction_unit.\n"),name.c_str()); |
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| 112 | |
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| 113 | (*(_Prediction_unit->in_CLOCK)) (*(in_CLOCK)); |
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| 114 | (*(_Prediction_unit->in_NRESET)) (*(in_NRESET)); |
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| 115 | |
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[82] | 116 | INSTANCE1_SC_SIGNAL(_Prediction_unit, in_PREDICT_VAL ,_param->_nb_context); |
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| 117 | INSTANCE1_SC_SIGNAL(_Prediction_unit,out_PREDICT_ACK ,_param->_nb_context); |
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| 118 | INSTANCE1_SC_SIGNAL(_Prediction_unit, in_PREDICT_PC_PREVIOUS ,_param->_nb_context); |
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| 119 | INSTANCE1_SC_SIGNAL(_Prediction_unit, in_PREDICT_PC_CURRENT ,_param->_nb_context); |
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| 120 | INSTANCE1_SC_SIGNAL(_Prediction_unit, in_PREDICT_PC_CURRENT_IS_DS_TAKE ,_param->_nb_context); |
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| 121 | INSTANCE1_SC_SIGNAL(_Prediction_unit,out_PREDICT_PC_NEXT ,_param->_nb_context); |
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| 122 | INSTANCE1_SC_SIGNAL(_Prediction_unit,out_PREDICT_PC_NEXT_IS_DS_TAKE ,_param->_nb_context); |
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[88] | 123 | INSTANCE2_SC_SIGNAL(_Prediction_unit,out_PREDICT_INSTRUCTION_ENABLE ,_param->_nb_context,_param->_nb_instruction[it1]); |
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[82] | 124 | INSTANCE1_SC_SIGNAL(_Prediction_unit,out_PREDICT_BRANCH_STATE ,_param->_nb_context); |
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[88] | 125 | if (_param->_have_port_inst_ifetch_ptr) |
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| 126 | INSTANCE1_SC_SIGNAL(_Prediction_unit,out_PREDICT_INST_IFETCH_PTR ,_param->_nb_context); |
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| 127 | if (_param->_have_port_depth) |
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| 128 | INSTANCE1_SC_SIGNAL(_Prediction_unit,out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_context); |
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| 129 | INSTANCE2_SC_SIGNAL(_Prediction_unit, in_DECOD_VAL ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); |
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| 130 | INSTANCE2_SC_SIGNAL(_Prediction_unit,out_DECOD_ACK ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); |
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[82] | 131 | if (_param->_have_port_context_id) |
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[88] | 132 | INSTANCE2_SC_SIGNAL(_Prediction_unit, in_DECOD_CONTEXT_ID ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); |
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| 133 | INSTANCE2_SC_SIGNAL(_Prediction_unit, in_DECOD_MATCH_INST_IFETCH_PTR ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); |
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| 134 | INSTANCE2_SC_SIGNAL(_Prediction_unit, in_DECOD_BRANCH_STATE ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); |
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| 135 | if (_param->_have_port_depth) |
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| 136 | INSTANCE2_SC_SIGNAL(_Prediction_unit, in_DECOD_BRANCH_UPDATE_PREDICTION_ID ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); |
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| 137 | INSTANCE2_SC_SIGNAL(_Prediction_unit, in_DECOD_BRANCH_CONDITION ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); |
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| 138 | INSTANCE2_SC_SIGNAL(_Prediction_unit, in_DECOD_BRANCH_DIRECTION ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); |
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| 139 | INSTANCE2_SC_SIGNAL(_Prediction_unit, in_DECOD_ADDRESS_SRC ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); |
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| 140 | INSTANCE2_SC_SIGNAL(_Prediction_unit, in_DECOD_ADDRESS_DEST ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); |
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[82] | 141 | |
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| 142 | INSTANCE1_SC_SIGNAL(_Prediction_unit, in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete); |
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| 143 | INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete); |
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| 144 | if (_param->_have_port_context_id) |
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| 145 | INSTANCE1_SC_SIGNAL(_Prediction_unit, in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete); |
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[88] | 146 | if (_param->_have_port_depth) |
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[82] | 147 | INSTANCE1_SC_SIGNAL(_Prediction_unit, in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete); |
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| 148 | INSTANCE1_SC_SIGNAL(_Prediction_unit, in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete); |
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[98] | 149 | INSTANCE1_SC_SIGNAL(_Prediction_unit, in_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete); |
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[82] | 150 | INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_COMPLETE_MISS_PREDICTION ,_param->_nb_inst_branch_complete); |
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| 151 | INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete); |
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| 152 | INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete); |
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| 153 | INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete); |
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| 154 | |
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| 155 | INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_EVENT_VAL ,_param->_nb_context); |
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| 156 | INSTANCE1_SC_SIGNAL(_Prediction_unit, in_BRANCH_EVENT_ACK ,_param->_nb_context); |
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| 157 | //if (_param->_have_port_context_id) |
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| 158 | //INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context); |
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[98] | 159 | if (_param->_have_port_depth) |
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| 160 | INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_EVENT_DEPTH ,_param->_nb_context); |
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[82] | 161 | //INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context); |
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| 162 | INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context); |
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[95] | 163 | INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_EVENT_ADDRESS_DEST_VAL ,_param->_nb_context); |
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[82] | 164 | INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context); |
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| 165 | |
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[97] | 166 | INSTANCE1_SC_SIGNAL(_Prediction_unit, in_EVENT_VAL ,_param->_nb_context); |
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| 167 | INSTANCE1_SC_SIGNAL(_Prediction_unit,out_EVENT_ACK ,_param->_nb_context); |
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[95] | 168 | INSTANCE1_SC_SIGNAL(_Prediction_unit, in_EVENT_TYPE ,_param->_nb_context); |
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[88] | 169 | if (_param->_have_port_depth) |
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| 170 | { |
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[95] | 171 | INSTANCE1_SC_SIGNAL(_Prediction_unit, in_EVENT_DEPTH ,_param->_nb_context); |
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[88] | 172 | INSTANCE1_SC_SIGNAL(_Prediction_unit,out_DEPTH_CURRENT ,_param->_nb_context); |
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| 173 | INSTANCE1_SC_SIGNAL(_Prediction_unit,out_DEPTH_MIN ,_param->_nb_context); |
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[101] | 174 | INSTANCE1_SC_SIGNAL(_Prediction_unit,out_DEPTH_MAX ,_param->_nb_context); |
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[88] | 175 | } |
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[101] | 176 | INSTANCE1_SC_SIGNAL(_Prediction_unit,out_DEPTH_VAL ,_param->_nb_context); |
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| 177 | INSTANCE1_SC_SIGNAL(_Prediction_unit,out_DEPTH_FULL ,_param->_nb_context); |
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[82] | 178 | |
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[78] | 179 | msg(_("<%s> : Start Simulation ............\n"),name.c_str()); |
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| 180 | |
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| 181 | Time * _time = new Time(); |
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| 182 | |
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| 183 | /******************************************************** |
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| 184 | * Simulation - Begin |
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| 185 | ********************************************************/ |
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| 186 | |
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| 187 | // Initialisation |
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| 188 | |
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| 189 | const uint32_t seed = 0; |
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| 190 | //const uint32_t seed = static_cast<uint32_t>(time(NULL)); |
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| 191 | |
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[88] | 192 | const int32_t percent_transaction_predict = 80; |
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| 193 | const int32_t percent_transaction_decod = 80; |
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| 194 | const int32_t percent_transaction_branch_complete = 80; |
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| 195 | const int32_t percent_transaction_branch_event = 80; |
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| 196 | |
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[78] | 197 | srand(seed); |
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[88] | 198 | |
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| 199 | uint32_t test1 = 1024; // TEST 1 : instruction without branch |
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| 200 | uint32_t test2 = 1024; // TEST 2 : sequence : 1 branch, 1 delayed slot |
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[78] | 201 | |
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| 202 | SC_START(0); |
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| 203 | LABEL("Initialisation"); |
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| 204 | |
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[88] | 205 | for (uint32_t i=0; i<_param->_nb_context; ++i) |
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| 206 | { |
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| 207 | in_PREDICT_VAL [i]->write(0); |
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| 208 | in_BRANCH_EVENT_ACK [i]->write(0); |
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| 209 | } |
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| 210 | |
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| 211 | for (uint32_t i=0; i<_param->_nb_decod_unit;++i) |
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| 212 | for (uint32_t j=0; j<_param->_nb_inst_decod[i]; ++j) |
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| 213 | { |
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| 214 | in_DECOD_VAL [i][j]->write(0); |
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| 215 | } |
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| 216 | |
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| 217 | for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i) |
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| 218 | { |
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| 219 | in_BRANCH_COMPLETE_VAL [i]->write(0); |
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| 220 | } |
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| 221 | |
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[78] | 222 | LABEL("Reset"); |
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| 223 | in_NRESET->write(0); |
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| 224 | SC_START(5); |
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| 225 | in_NRESET->write(1); |
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| 226 | |
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[88] | 227 | for (uint32_t i=0; i<_param->_nb_context; ++i) |
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| 228 | { |
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[95] | 229 | // TEST(Tcontrol_t,out_PREDICT_ACK [i]->read(),1); // Accept new request |
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[88] | 230 | TEST(Tcontrol_t,out_BRANCH_EVENT_VAL [i]->read(),0); |
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| 231 | TEST(Tdepth_t ,out_DEPTH_CURRENT [i]->read(),0); |
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| 232 | TEST(Tdepth_t ,out_DEPTH_MIN [i]->read(),0); |
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| 233 | TEST(Tdepth_t ,out_DEPTH_MAX [i]->read(),0); |
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| 234 | } |
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| 235 | |
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| 236 | for (uint32_t i=0; i<_param->_nb_decod_unit;++i) |
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| 237 | for (uint32_t j=0; j<_param->_nb_inst_decod[i]; ++j) |
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| 238 | { |
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| 239 | TEST(Tcontrol_t,out_DECOD_ACK [i][j]->read(),0); // No decod instruction |
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| 240 | } |
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| 241 | |
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| 242 | for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i) |
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| 243 | { |
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| 244 | TEST(Tcontrol_t,out_BRANCH_COMPLETE_ACK [i]->read(),1); // Accept new branch_complete |
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| 245 | } |
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| 246 | |
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[78] | 247 | LABEL("Loop of Test"); |
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| 248 | |
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[88] | 249 | Taddress_t PC_PREVIOUS [_param->_nb_context]; |
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| 250 | Taddress_t PC_CURRENT [_param->_nb_context]; |
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| 251 | Tcontrol_t PC_CURRENT_IS_DS_TAKE [_param->_nb_context]; |
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| 252 | |
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[78] | 253 | for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) |
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| 254 | { |
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| 255 | LABEL("Iteration %d",iteration); |
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| 256 | |
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[88] | 257 | // TEST 1 : instruction without branch |
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| 258 | for (uint32_t test=0; test<test1; ++test) |
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| 259 | { |
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| 260 | for (uint32_t i=0; i<_param->_nb_context; ++i) |
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| 261 | { |
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| 262 | PC_CURRENT [i] = (0x100000>>2); |
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| 263 | PC_CURRENT_IS_DS_TAKE [i] = 0; |
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| 264 | PC_PREVIOUS [i] = PC_CURRENT[i]-1; |
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| 265 | } |
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| 266 | |
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| 267 | for (uint32_t i=0; i<_param->_nb_context; ++i) |
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| 268 | { |
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| 269 | in_PREDICT_VAL [i]->write((rand()%100)<percent_transaction_predict); |
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| 270 | in_PREDICT_PC_PREVIOUS [i]->write(PC_PREVIOUS [i]); |
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| 271 | in_PREDICT_PC_CURRENT [i]->write(PC_CURRENT [i]); |
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| 272 | in_PREDICT_PC_CURRENT_IS_DS_TAKE [i]->write(PC_CURRENT_IS_DS_TAKE[i]); |
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| 273 | } |
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| 274 | |
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| 275 | SC_START(1); |
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| 276 | |
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| 277 | for (uint32_t i=0; i<_param->_nb_context; ++i) |
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| 278 | // Test if transaction |
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| 279 | if (in_PREDICT_VAL [i]->read() and out_PREDICT_ACK [i]->read()) |
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| 280 | { |
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| 281 | TEST(Taddress_t ,out_PREDICT_PC_NEXT [i]->read(),PC_CURRENT[i]+_param->_nb_instruction[i]); |
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| 282 | TEST(Tcontrol_t ,out_PREDICT_PC_NEXT_IS_DS_TAKE [i]->read(),0); |
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| 283 | for (uint32_t j=0; j<_param->_nb_instruction[i]; ++j) |
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| 284 | TEST(Tcontrol_t ,out_PREDICT_INSTRUCTION_ENABLE [i][j]->read(),1); |
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| 285 | TEST(Tinst_ifetch_ptr_t,out_PREDICT_INST_IFETCH_PTR [i]->read(),0); |
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| 286 | TEST(Tbranch_state_t ,out_PREDICT_BRANCH_STATE [i]->read(),BRANCH_STATE_NONE); |
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| 287 | TEST(Tprediction_ptr_t ,out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [i]->read(),0); |
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| 288 | |
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| 289 | PC_PREVIOUS [i] = PC_CURRENT [i]; |
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| 290 | PC_CURRENT [i] = out_PREDICT_PC_NEXT [i]->read(); |
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| 291 | PC_CURRENT_IS_DS_TAKE [i] = out_PREDICT_PC_NEXT_IS_DS_TAKE [i]->read(); |
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| 292 | } |
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| 293 | |
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| 294 | // Test another output |
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| 295 | for (uint32_t i=0; i<_param->_nb_context; ++i) |
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| 296 | { |
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| 297 | TEST(Tcontrol_t,out_BRANCH_EVENT_VAL [i]->read(),0); |
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| 298 | TEST(Tdepth_t ,out_DEPTH_CURRENT [i]->read(),0); |
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| 299 | TEST(Tdepth_t ,out_DEPTH_MIN [i]->read(),0); |
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| 300 | TEST(Tdepth_t ,out_DEPTH_MAX [i]->read(),0); |
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| 301 | } |
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| 302 | |
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| 303 | for (uint32_t i=0; i<_param->_nb_decod_unit;++i) |
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| 304 | for (uint32_t j=0; j<_param->_nb_inst_decod[i]; ++j) |
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| 305 | { |
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| 306 | TEST(Tcontrol_t,out_DECOD_ACK [i][j]->read(),0); // No decod instruction |
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| 307 | } |
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| 308 | |
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| 309 | for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i) |
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| 310 | { |
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| 311 | TEST(Tcontrol_t,out_BRANCH_COMPLETE_ACK [i]->read(),1); // Accept new branch_complete |
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| 312 | } |
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| 313 | } |
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| 314 | |
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[78] | 315 | SC_START(1); |
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| 316 | } |
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| 317 | |
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| 318 | /******************************************************** |
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| 319 | * Simulation - End |
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| 320 | ********************************************************/ |
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| 321 | |
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| 322 | TEST_OK ("End of Simulation"); |
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| 323 | delete _time; |
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| 324 | |
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| 325 | msg(_("<%s> : ............ Stop Simulation\n"),name.c_str()); |
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| 326 | |
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| 327 | delete in_CLOCK; |
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| 328 | delete in_NRESET; |
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[82] | 329 | |
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| 330 | DELETE1_SC_SIGNAL( in_PREDICT_VAL ,_param->_nb_context); |
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| 331 | DELETE1_SC_SIGNAL(out_PREDICT_ACK ,_param->_nb_context); |
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| 332 | DELETE1_SC_SIGNAL( in_PREDICT_PC_PREVIOUS ,_param->_nb_context); |
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| 333 | DELETE1_SC_SIGNAL( in_PREDICT_PC_CURRENT ,_param->_nb_context); |
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| 334 | DELETE1_SC_SIGNAL( in_PREDICT_PC_CURRENT_IS_DS_TAKE ,_param->_nb_context); |
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| 335 | DELETE1_SC_SIGNAL(out_PREDICT_PC_NEXT ,_param->_nb_context); |
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| 336 | DELETE1_SC_SIGNAL(out_PREDICT_PC_NEXT_IS_DS_TAKE ,_param->_nb_context); |
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| 337 | DELETE1_SC_SIGNAL(out_PREDICT_INST_IFETCH_PTR ,_param->_nb_context); |
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| 338 | DELETE1_SC_SIGNAL(out_PREDICT_BRANCH_STATE ,_param->_nb_context); |
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| 339 | DELETE1_SC_SIGNAL(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_context); |
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| 340 | |
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[88] | 341 | DELETE2_SC_SIGNAL(out_PREDICT_INSTRUCTION_ENABLE ,_param->_nb_context,_param->_nb_instruction[it1]); |
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| 342 | DELETE2_SC_SIGNAL( in_DECOD_VAL ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); |
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| 343 | DELETE2_SC_SIGNAL(out_DECOD_ACK ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); |
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| 344 | DELETE2_SC_SIGNAL( in_DECOD_CONTEXT_ID ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); |
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| 345 | DELETE2_SC_SIGNAL( in_DECOD_MATCH_INST_IFETCH_PTR ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); |
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| 346 | DELETE2_SC_SIGNAL( in_DECOD_BRANCH_STATE ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); |
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| 347 | DELETE2_SC_SIGNAL( in_DECOD_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); |
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| 348 | DELETE2_SC_SIGNAL( in_DECOD_BRANCH_CONDITION ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); |
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| 349 | DELETE2_SC_SIGNAL( in_DECOD_BRANCH_DIRECTION ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); |
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| 350 | DELETE2_SC_SIGNAL( in_DECOD_ADDRESS_SRC ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); |
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| 351 | DELETE2_SC_SIGNAL( in_DECOD_ADDRESS_DEST ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); |
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[82] | 352 | |
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| 353 | DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete); |
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| 354 | DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete); |
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| 355 | DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete); |
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| 356 | DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete); |
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| 357 | DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete); |
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[98] | 358 | DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete); |
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[82] | 359 | DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete); |
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| 360 | DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete); |
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| 361 | DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete); |
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| 362 | DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete); |
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| 363 | |
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[95] | 364 | DELETE1_SC_SIGNAL(out_BRANCH_EVENT_VAL ,_param->_nb_context); |
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| 365 | DELETE1_SC_SIGNAL( in_BRANCH_EVENT_ACK ,_param->_nb_context); |
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| 366 | //DELETE1_SC_SIGNAL(out_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context); |
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[98] | 367 | DELETE1_SC_SIGNAL(out_BRANCH_EVENT_DEPTH ,_param->_nb_context); |
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[95] | 368 | //DELETE1_SC_SIGNAL(out_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context); |
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| 369 | DELETE1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context); |
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| 370 | DELETE1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST_VAL ,_param->_nb_context); |
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| 371 | DELETE1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context); |
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[82] | 372 | |
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[97] | 373 | DELETE1_SC_SIGNAL( in_EVENT_VAL ,_param->_nb_context); |
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| 374 | DELETE1_SC_SIGNAL(out_EVENT_ACK ,_param->_nb_context); |
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[95] | 375 | DELETE1_SC_SIGNAL( in_EVENT_TYPE ,_param->_nb_context); |
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| 376 | DELETE1_SC_SIGNAL( in_EVENT_DEPTH ,_param->_nb_context); |
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| 377 | |
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[101] | 378 | DELETE1_SC_SIGNAL(out_DEPTH_VAL ,_param->_nb_context); |
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[88] | 379 | DELETE1_SC_SIGNAL(out_DEPTH_CURRENT ,_param->_nb_context); |
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| 380 | DELETE1_SC_SIGNAL(out_DEPTH_MIN ,_param->_nb_context); |
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| 381 | DELETE1_SC_SIGNAL(out_DEPTH_MAX ,_param->_nb_context); |
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[101] | 382 | DELETE1_SC_SIGNAL(out_DEPTH_FULL ,_param->_nb_context); |
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[78] | 383 | #endif |
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| 384 | |
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| 385 | delete _Prediction_unit; |
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| 386 | #ifdef STATISTICS |
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| 387 | delete _parameters_statistics; |
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| 388 | #endif |
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| 389 | } |
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