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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp @ 107

Last change on this file since 107 was 107, checked in by rosiere, 15 years ago
1) Fix test in Direction_Glue for Conditionnal Branch 2) Fix Instruction Address Compute
Property svn:keywords set to `Id`
File size: 141.1 KB

Line
1	/*
2	* $id: test.cpp 82 2008-05-01 16:48:45Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#define NB_ITERATION 16
10	#define CYCLE_MAX (1024*NB_ITERATION)
11
12	#include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/include/test.h"
13	#include "Common/include/Test.h"
14	#include "Behavioural/include/Allocation.h"
15
16	typedef struct
17	{
18	uint32_t ufpt_ptr ;
19	uint32_t upt_ptr ;
20
21	Tcontext_t context ;
22	Taddress_t address_src ;
23	Taddress_t address_dest;
24	Taddress_t address_good;
25	Tbranch_condition_t condition ;
26	Tcontrol_t take ;
27	Tcontrol_t take_good ;
28	Tcontrol_t flag ;
29	Tcontrol_t no_sequence ;
30	Tcontrol_t is_accurate ;
31	Thistory_t history ;
32	Taddress_t ras_address ;
33	Tptr_t ras_index ;
34	Tcontrol_t miss_ifetch ;
35	Tcontrol_t miss_decod ;
36	Tcontrol_t miss_commit ;
37	} request_t;
38
39	void test (string name,
40	morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::Parameters * _param)
41	{
42	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
43
44	#ifdef STATISTICS
45	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX);
46	#endif
47
48	Tusage_t _usage = USE_ALL;
49
50	// _usage = usage_unset(_usage,USE_SYSTEMC );
51	// _usage = usage_unset(_usage,USE_VHDL );
52	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
53	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
54	// _usage = usage_unset(_usage,USE_POSITION );
55	// _usage = usage_unset(_usage,USE_STATISTICS );
56	// _usage = usage_unset(_usage,USE_INFORMATION );
57
58	Update_Prediction_Table * _Update_Prediction_Table = new Update_Prediction_Table
59	(name.c_str(),
60	#ifdef STATISTICS
61	_parameters_statistics,
62	#endif
63	_param,
64	_usage);
65
66	#ifdef SYSTEMC
67	/*********************************************************************
68	* Déclarations des signaux
69	*********************************************************************/
70	string rename;
71
72	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
73	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
74
75	ALLOC1_SC_SIGNAL( in_PREDICT_VAL ," in_PREDICT_VAL ",Tcontrol_t ,_param->_nb_inst_predict);
76	ALLOC1_SC_SIGNAL(out_PREDICT_ACK ,"out_PREDICT_ACK ",Tcontrol_t ,_param->_nb_inst_predict);
77	ALLOC1_SC_SIGNAL( in_PREDICT_CONTEXT_ID ," in_PREDICT_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_predict);
78	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_ADDRESS_SRC ," in_PREDICT_BTB_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_predict);
79	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_ADDRESS_DEST ," in_PREDICT_BTB_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_predict);
80	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_CONDITION ," in_PREDICT_BTB_CONDITION ",Tbranch_condition_t,_param->_nb_inst_predict);
81	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_LAST_TAKE ," in_PREDICT_BTB_LAST_TAKE ",Tcontrol_t ,_param->_nb_inst_predict);
82	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_IS_ACCURATE ," in_PREDICT_BTB_IS_ACCURATE ",Tcontrol_t ,_param->_nb_inst_predict);
83	ALLOC1_SC_SIGNAL( in_PREDICT_DIR_HISTORY ," in_PREDICT_DIR_HISTORY ",Thistory_t ,_param->_nb_inst_predict);
84	ALLOC1_SC_SIGNAL( in_PREDICT_RAS_ADDRESS ," in_PREDICT_RAS_ADDRESS ",Taddress_t ,_param->_nb_inst_predict);
85	ALLOC1_SC_SIGNAL( in_PREDICT_RAS_INDEX ," in_PREDICT_RAS_INDEX ",Tptr_t ,_param->_nb_inst_predict);
86	ALLOC1_SC_SIGNAL(out_PREDICT_UPDATE_PREDICTION_ID ,"out_PREDICT_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_inst_predict);
87	ALLOC1_SC_SIGNAL( in_DECOD_VAL ," in_DECOD_VAL ",Tcontrol_t ,_param->_nb_inst_decod);
88	ALLOC1_SC_SIGNAL(out_DECOD_ACK ,"out_DECOD_ACK ",Tcontrol_t ,_param->_nb_inst_decod);
89	ALLOC1_SC_SIGNAL( in_DECOD_CONTEXT_ID ," in_DECOD_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_decod);
90	ALLOC1_SC_SIGNAL( in_DECOD_BTB_ADDRESS_SRC ," in_DECOD_BTB_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_decod);
91	ALLOC1_SC_SIGNAL( in_DECOD_BTB_ADDRESS_DEST ," in_DECOD_BTB_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_decod);
92	ALLOC1_SC_SIGNAL( in_DECOD_BTB_CONDITION ," in_DECOD_BTB_CONDITION ",Tbranch_condition_t,_param->_nb_inst_decod);
93	ALLOC1_SC_SIGNAL( in_DECOD_BTB_LAST_TAKE ," in_DECOD_BTB_LAST_TAKE ",Tcontrol_t ,_param->_nb_inst_decod);
94	ALLOC1_SC_SIGNAL( in_DECOD_RAS_ADDRESS ," in_DECOD_RAS_ADDRESS ",Taddress_t ,_param->_nb_inst_decod);
95	ALLOC1_SC_SIGNAL( in_DECOD_RAS_INDEX ," in_DECOD_RAS_INDEX ",Tptr_t ,_param->_nb_inst_decod);
96	ALLOC1_SC_SIGNAL( in_DECOD_MISS_IFETCH ," in_DECOD_MISS_IFETCH ",Tcontrol_t ,_param->_nb_inst_decod);
97	ALLOC1_SC_SIGNAL( in_DECOD_MISS_DECOD ," in_DECOD_MISS_DECOD ",Tcontrol_t ,_param->_nb_inst_decod);
98	ALLOC1_SC_SIGNAL( in_DECOD_UPDATE_PREDICTION_ID ," in_DECOD_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_inst_decod);
99	//ALLOC1_SC_SIGNAL(out_DECOD_DEPTH ,"out_DECOD_DEPTH ",Tdepth_t ,_param->_nb_inst_decod);
100	ALLOC1_SC_SIGNAL( in_DECOD_IS_ACCURATE ," in_DECOD_IS_ACCURATE ",Tcontrol_t ,_param->_nb_inst_decod);
101
102	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ," in_BRANCH_COMPLETE_VAL ",Tcontrol_t ,_param->_nb_inst_branch_complete);
103	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,"out_BRANCH_COMPLETE_ACK ",Tcontrol_t ,_param->_nb_inst_branch_complete);
104	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ," in_BRANCH_COMPLETE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_branch_complete);
105	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ," in_BRANCH_COMPLETE_DEPTH ",Tdepth_t ,_param->_nb_inst_branch_complete);
106	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ," in_BRANCH_COMPLETE_ADDRESS ",Taddress_t ,_param->_nb_inst_branch_complete);
107	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_NO_SEQUENCE ," in_BRANCH_COMPLETE_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_inst_branch_complete);
108	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION,"out_BRANCH_COMPLETE_MISS_PREDICTION",Tcontrol_t ,_param->_nb_inst_branch_complete);
109	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_TAKE ,"out_BRANCH_COMPLETE_TAKE ",Tcontrol_t ,_param->_nb_inst_branch_complete);
110	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_SRC ,"out_BRANCH_COMPLETE_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_branch_complete);
111	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_DEST ,"out_BRANCH_COMPLETE_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_branch_complete);
112
113	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_VAL ,"out_BRANCH_EVENT_VAL ",Tcontrol_t ,_param->_nb_context);
114	ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ACK ," in_BRANCH_EVENT_ACK ",Tcontrol_t ,_param->_nb_context);
115	// ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_CONTEXT_ID ,"out_BRANCH_EVENT_CONTEXT_ID ",Tcontext_t ,_param->_nb_context);
116	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_DEPTH ,"out_BRANCH_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context);
117	// ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_MISS_PREDICTION,"out_BRANCH_EVENT_MISS_PREDICTION",Tcontrol_t ,_param->_nb_context);
118	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC ,"out_BRANCH_EVENT_ADDRESS_SRC ",Taddress_t ,_param->_nb_context);
119	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST_VAL,"out_BRANCH_EVENT_ADDRESS_DEST_VAL",Tcontrol_t ,_param->_nb_context);
120	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,"out_BRANCH_EVENT_ADDRESS_DEST ",Taddress_t ,_param->_nb_context);
121
122	ALLOC1_SC_SIGNAL(out_UPDATE_VAL ,"out_UPDATE_VAL ",Tcontrol_t ,_param->_nb_inst_update);
123	ALLOC1_SC_SIGNAL( in_UPDATE_ACK ," in_UPDATE_ACK ",Tcontrol_t ,_param->_nb_inst_update);
124	ALLOC1_SC_SIGNAL(out_UPDATE_CONTEXT_ID ,"out_UPDATE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_update);
125	ALLOC1_SC_SIGNAL(out_UPDATE_MISS_PREDICTION ,"out_UPDATE_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_inst_update);
126	ALLOC1_SC_SIGNAL(out_UPDATE_DIRECTION_GOOD ,"out_UPDATE_DIRECTION_GOOD ",Tcontrol_t ,_param->_nb_inst_update);
127	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_VAL ,"out_UPDATE_BTB_VAL ",Tcontrol_t ,_param->_nb_inst_update);
128	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_ADDRESS_SRC ,"out_UPDATE_BTB_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_update);
129	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_ADDRESS_DEST ,"out_UPDATE_BTB_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_update);
130	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_CONDITION ,"out_UPDATE_BTB_CONDITION ",Tbranch_condition_t,_param->_nb_inst_update);
131	ALLOC1_SC_SIGNAL(out_UPDATE_DIR_VAL ,"out_UPDATE_DIR_VAL ",Tcontrol_t ,_param->_nb_inst_update);
132	ALLOC1_SC_SIGNAL(out_UPDATE_DIR_HISTORY ,"out_UPDATE_DIR_HISTORY ",Thistory_t ,_param->_nb_inst_update);
133	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_VAL ,"out_UPDATE_RAS_VAL ",Tcontrol_t ,_param->_nb_inst_update);
134	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_FLUSH ,"out_UPDATE_RAS_FLUSH ",Tcontrol_t ,_param->_nb_inst_update);
135	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_PUSH ,"out_UPDATE_RAS_PUSH ",Tcontrol_t ,_param->_nb_inst_update);
136	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_ADDRESS ,"out_UPDATE_RAS_ADDRESS ",Taddress_t ,_param->_nb_inst_update);
137	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_INDEX ,"out_UPDATE_RAS_INDEX ",Tptr_t ,_param->_nb_inst_update);
138	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_PREDICTION_IFETCH ,"out_UPDATE_RAS_PREDICTION_IFETCH ",Tcontrol_t ,_param->_nb_inst_update);
139
140	ALLOC1_SC_SIGNAL( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t ,_param->_nb_context);
141	ALLOC1_SC_SIGNAL(out_EVENT_ACK ,"out_EVENT_ACK ",Tcontrol_t ,_param->_nb_context);
142	ALLOC1_SC_SIGNAL( in_EVENT_TYPE ," in_EVENT_TYPE ",Tevent_type_t ,_param->_nb_context);
143	ALLOC1_SC_SIGNAL( in_EVENT_DEPTH ," in_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context);
144
145	ALLOC1_SC_SIGNAL(out_DEPTH_VAL ,"out_DEPTH_VAL ",Tcontrol_t ,_param->_nb_context);
146	ALLOC1_SC_SIGNAL(out_DEPTH_CURRENT ,"out_DEPTH_CURRENT ",Tdepth_t ,_param->_nb_context);
147	ALLOC1_SC_SIGNAL(out_DEPTH_MIN ,"out_DEPTH_MIN ",Tdepth_t ,_param->_nb_context);
148	ALLOC1_SC_SIGNAL(out_DEPTH_MAX ,"out_DEPTH_MAX ",Tdepth_t ,_param->_nb_context);
149	ALLOC1_SC_SIGNAL(out_DEPTH_FULL ,"out_DEPTH_FULL ",Tcontrol_t ,_param->_nb_context);
150
151	/********************************************************
152	* Instanciation
153	********************************************************/
154
155	msg(_("<%s> : Instanciation of _Update_Prediction_Table.\n"),name.c_str());
156
157	((_Update_Prediction_Table->in_CLOCK)) ((in_CLOCK));
158	((_Update_Prediction_Table->in_NRESET)) ((in_NRESET));
159
160	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_VAL ,_param->_nb_inst_predict);
161	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_PREDICT_ACK ,_param->_nb_inst_predict);
162	if (_param->_have_port_context_id)
163	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_CONTEXT_ID ,_param->_nb_inst_predict);
164	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_ADDRESS_SRC ,_param->_nb_inst_predict);
165	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_ADDRESS_DEST ,_param->_nb_inst_predict);
166	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_CONDITION ,_param->_nb_inst_predict);
167	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_LAST_TAKE ,_param->_nb_inst_predict);
168	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_IS_ACCURATE ,_param->_nb_inst_predict);
169	if (_param->_have_port_history)
170	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_DIR_HISTORY ,_param->_nb_inst_predict);
171	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_RAS_ADDRESS ,_param->_nb_inst_predict);
172	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_RAS_INDEX ,_param->_nb_inst_predict);
173	if (_param->_have_port_depth)
174	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_PREDICT_UPDATE_PREDICTION_ID ,_param->_nb_inst_predict);
175	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_VAL ,_param->_nb_inst_decod);
176	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DECOD_ACK ,_param->_nb_inst_decod);
177	if (_param->_have_port_context_id)
178	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_CONTEXT_ID ,_param->_nb_inst_decod);
179	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_ADDRESS_SRC ,_param->_nb_inst_decod);
180	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_ADDRESS_DEST ,_param->_nb_inst_decod);
181	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_CONDITION ,_param->_nb_inst_decod);
182	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_LAST_TAKE ,_param->_nb_inst_decod);
183	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_RAS_ADDRESS ,_param->_nb_inst_decod);
184	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_RAS_INDEX ,_param->_nb_inst_decod);
185	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_MISS_IFETCH ,_param->_nb_inst_decod);
186	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_MISS_DECOD ,_param->_nb_inst_decod);
187	if (_param->_have_port_depth)
188	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_UPDATE_PREDICTION_ID ,_param->_nb_inst_decod);
189	//if (_param->_have_port_depth)
190	//INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DECOD_DEPTH ,_param->_nb_inst_decod);
191	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_IS_ACCURATE ,_param->_nb_inst_decod);
192	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete);
193	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete);
194	if (_param->_have_port_context_id)
195	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete);
196	if (_param->_have_port_depth)
197	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete);
198	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete);
199	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete);
200	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete);
201	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete);
202	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete);
203	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete);
204
205	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_VAL ,_param->_nb_context);
206	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_EVENT_ACK ,_param->_nb_context);
207	//if (_param->_have_port_context_id)
208	//INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context);
209	if (_param->_have_port_depth)
210	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_DEPTH ,_param->_nb_context);
211	//INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_MISS_PREDICTION,_param->_nb_context);
212	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context);
213	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_DEST_VAL,_param->_nb_context);
214	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context);
215
216	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_VAL ,_param->_nb_inst_update);
217	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_UPDATE_ACK ,_param->_nb_inst_update);
218	if (_param->_have_port_context_id)
219	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_CONTEXT_ID ,_param->_nb_inst_update);
220	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_MISS_PREDICTION ,_param->_nb_inst_update);
221	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_DIRECTION_GOOD ,_param->_nb_inst_update);
222	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_VAL ,_param->_nb_inst_update);
223	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_ADDRESS_SRC ,_param->_nb_inst_update);
224	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_ADDRESS_DEST ,_param->_nb_inst_update);
225	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_CONDITION ,_param->_nb_inst_update);
226	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_DIR_VAL ,_param->_nb_inst_update);
227	if (_param->_have_port_history)
228	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_DIR_HISTORY ,_param->_nb_inst_update);
229	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_VAL ,_param->_nb_inst_update);
230	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_FLUSH ,_param->_nb_inst_update);
231	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_PUSH ,_param->_nb_inst_update);
232	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_ADDRESS ,_param->_nb_inst_update);
233	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_INDEX ,_param->_nb_inst_update);
234	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_PREDICTION_IFETCH ,_param->_nb_inst_update);
235	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_VAL ,_param->_nb_context);
236	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_EVENT_ACK ,_param->_nb_context);
237	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_TYPE ,_param->_nb_context);
238	if (_param->_have_port_depth)
239	{
240	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_DEPTH ,_param->_nb_context);
241	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_CURRENT ,_param->_nb_context);
242	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_MIN ,_param->_nb_context);
243	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_MAX ,_param->_nb_context);
244	}
245	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_VAL ,_param->_nb_context);
246	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_FULL ,_param->_nb_context);
247
248	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
249
250	Time * _time = new Time();
251
252	/********************************************************
253	* Simulation - Begin
254	********************************************************/
255
256	// Initialisation
257
258	const uint32_t seed = 0;
259	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
260
261	srand(seed);
262
263	const int32_t percent_transaction_predict = 75;
264	const int32_t percent_transaction_decod = 75;
265	const int32_t percent_transaction_branch_complete = 75;
266	const int32_t percent_transaction_update = 75;
267	const int32_t percent_transaction_branch_event = 75;
268	const int32_t percent_transaction_event = 75;
269
270	const bool test1 = true;
271	const bool test2 = true;
272	const bool test3 = true;
273	const bool test4 = true;
274	const bool test5 = true;
275
276	std::list<request_t> ufpt;
277	std::list<request_t> upt;
278	request_t event;
279
280	SC_START(0);
281	LABEL("Initialisation");
282
283	LABEL("Reset");
284	in_NRESET->write(0);
285	SC_START(5);
286	in_NRESET->write(1);
287
288	Tdepth_t ufpt_bottom [_param->_nb_context];
289	Tdepth_t ufpt_top [_param->_nb_context];
290
291	Tdepth_t upt_bottom [_param->_nb_context];
292	Tdepth_t upt_top [_param->_nb_context];
293	Tdepth_t upt_top_event[_param->_nb_context];
294
295	for (uint32_t i=0; i<_param->_nb_context; ++i)
296	{
297	ufpt_bottom [i] = 0;
298	ufpt_top [i] = 0;
299	upt_bottom [i] = 0;
300	upt_top [i] = 0;
301	upt_top_event[i] = 0;
302	}
303
304	for (uint32_t i=0; i<_param->_nb_context; ++i)
305	{
306	TEST(Tdepth_t,out_DEPTH_CURRENT [i]->read(),upt_top [i]);
307	TEST(Tdepth_t,out_DEPTH_MIN [i]->read(),upt_bottom [i]);
308	TEST(Tdepth_t,out_DEPTH_MAX [i]->read(),upt_top [i]);
309	}
310
311	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
312	{
313	LABEL("Iteration %d",iteration);
314
315	for (uint32_t i=0; i<_param->_nb_inst_predict; ++i)
316	in_PREDICT_VAL [i]->write(0);
317	for (uint32_t i=0; i<_param->_nb_inst_decod; ++i)
318	in_DECOD_VAL [i]->write(0);
319	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i)
320	in_BRANCH_COMPLETE_VAL [i]->write(0);
321	for (uint32_t i=0; i<_param->_nb_context; ++i)
322	in_BRANCH_EVENT_ACK [i]->write(0);
323	for (uint32_t i=0; i<_param->_nb_inst_update; ++i)
324	in_UPDATE_ACK [i]->write(0);
325	for (uint32_t i=0; i<_param->_nb_context; ++i)
326	in_EVENT_VAL [i]->write(0);
327
328	//---------------------------------------------------------------------
329	//---------------------------------------------------------------------
330	// COMMON CASE
331	//---------------------------------------------------------------------
332	//---------------------------------------------------------------------
333	if (test1)
334	{
335	uint32_t context = rand() % _param->_nb_context;
336
337	{
338	LABEL("PREDICT - fill the queue");
339	uint32_t port = rand() % _param->_nb_inst_predict;
340
341	LABEL(" * context : %d",context);
342	LABEL(" * port : %d",port);
343
344	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
345	{
346	request_t request;
347	request.context = context;
348	request.address_src = 0xdeadbeef+i;
349	request.address_dest = 0x21071981+i;
350	request.address_good = request.address_dest;
351	request.condition = BRANCH_CONDITION_FLAG_SET;
352	request.take = 1;
353	request.take_good = 1;
354	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
355	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
356	request.is_accurate = true;
357	request.miss_ifetch = false;
358	request.miss_decod = false;
359	request.miss_commit = false;
360	request.history = i;
361	request.ras_address = 0xdeaddead+i;
362	request.ras_index = (0x12345678+i)%_param->_size_ras_index[context];
363	request.ufpt_ptr = ufpt_top [context];
364	// request.upt_ptr;
365
366	bool have_transaction = false;
367	do
368	{
369	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
370	in_PREDICT_CONTEXT_ID [port]->write(request.context );
371	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
372	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
373	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
374	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
375	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
376	in_PREDICT_DIR_HISTORY [port]->write(request.history );
377	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
378	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
379
380	if (_param->_have_port_depth)
381	{
382	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
383	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
384	}
385	SC_START(0); // fct melay
386
387	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
388	port,
389	in_PREDICT_VAL [port]->read(),
390	out_PREDICT_ACK [port]->read(),
391	in_PREDICT_BTB_IS_ACCURATE [port]->read());
392
393	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
394	{
395	LABEL("PREDICT [%d] - Transaction accepted",port);
396	have_transaction = true;
397
398	if (_param->_have_port_depth)
399	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
400
401	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
402	}
403
404	SC_START(1); // transition
405
406	} while (not have_transaction);
407
408	ufpt.push_back(request);
409
410	in_PREDICT_VAL [port]->write(0);
411
412	if (_param->_have_port_depth)
413	{
414	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
415	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
416	}
417	}
418	}
419
420	{
421	LABEL("DECOD");
422	uint32_t port = rand() % _param->_nb_inst_decod;
423
424	LABEL(" * context : %d",context);
425	LABEL(" * port : %d",port);
426
427	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
428	{
429	request_t request = ufpt.front();
430
431	bool have_transaction = false;
432	do
433	{
434	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
435	in_DECOD_CONTEXT_ID [port]->write(request.context );
436	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
437	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
438	in_DECOD_BTB_CONDITION [port]->write(request.condition );
439	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
440	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
441	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
442	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
443	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
444	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
445	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
446
447	SC_START(0); // fct melay
448
449	LABEL("DECOD [%d] %d - %d",
450	port,
451	in_PREDICT_VAL [port]->read(),
452	out_PREDICT_ACK [port]->read());
453
454	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
455	{
456	LABEL("DECOD [%d] - Transaction accepted",port);
457	have_transaction = true;
458
459	request.upt_ptr = upt_top [context];
460	upt.push_back(request);
461	ufpt.pop_front();
462
463	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
464	}
465
466	SC_START(1); // transition
467
468	} while (not have_transaction);
469
470	in_DECOD_VAL [port]->write(0);
471
472	if (_param->_have_port_depth)
473	{
474	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
475	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
476	}
477	}
478	}
479
480	{
481	LABEL("BRANCH_COMPLETE - hit ifetch");
482
483	uint32_t port = rand() % _param->_nb_inst_branch_complete;
484
485	LABEL(" * port : %d",port);
486
487	std::list<request_t>::iterator it_upt = upt.begin();
488
489	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
490	for (uint32_t i=0; i<upt.size(); i++)
491	{
492	bool have_transaction = false;
493
494	do
495	{
496	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
497	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
498	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
499	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_good);
500	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence );
501
502	if (_param->_have_port_depth)
503	{
504	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
505	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
506	}
507
508	SC_START(0);
509
510	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
511
512	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
513	{
514	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
515	have_transaction = true;
516
517	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
518	TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take_good );
519	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
520	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_good);
521
522	it_upt ++;
523	}
524
525	SC_START(1);
526	} while (not have_transaction);
527
528	in_BRANCH_COMPLETE_VAL [port]->write(0);
529
530	if (_param->_have_port_depth)
531	{
532	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
533	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
534	}
535	}
536	}
537
538	{
539	LABEL("UPDATE - hit ifetch");
540
541	uint32_t port = 0;
542
543	LABEL(" * port : %d",port);
544	std::list<request_t>::iterator it_upt = upt.begin();
545
546	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
547	for (uint32_t i=0; i<upt.size(); i++)
548	{
549	bool have_transaction = false;
550
551	do
552	{
553	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
554
555	// if (_param->_have_port_depth)
556	// {
557	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
558	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
559	// }
560
561	SC_START(0);
562
563	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
564
565	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
566	{
567	LABEL("UPDATE [%d] - Transaction accepted",port);
568	have_transaction = true;
569
570	if (_param->_have_port_context_id)
571	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
572	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
573	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
574	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
575	if (update_btb(it_upt->condition))
576	{
577	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
578	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
579	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
580	}
581	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
582	if (update_dir(it_upt->condition))
583	if (_param->_have_port_history)
584	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
585	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
586	if (update_ras(it_upt->condition))
587	{
588	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
589	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
590	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
591	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
592	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
593	}
594	++ it_upt;
595	}
596
597	SC_START(1);
598	} while (not have_transaction);
599
600	in_UPDATE_ACK [port]->write(0);
601	// if (_param->_have_port_depth)
602	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
603	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
604	}
605	upt.clear();
606	}
607
608	// Wait Garbage Collector
609	{
610	upt_bottom [context] = (upt_bottom [context]+_param->_size_ufpt_queue[context])%_param->_size_upt_queue[context];
611	// upt_top [context] = (upt_top [context]);
612
613	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
614	(upt_top [context] != out_DEPTH_MAX [context]->read()))
615	SC_START(1);
616
617	}
618	}
619
620	//---------------------------------------------------------------------
621	//---------------------------------------------------------------------
622	// DECOD MISS : no RAS in ifetch
623	//---------------------------------------------------------------------
624	//---------------------------------------------------------------------
625	if (test2)
626	{
627	uint32_t context = rand() % _param->_nb_context;
628
629	{
630	LABEL("PREDICT - fill the queue");
631	uint32_t port = rand() % _param->_nb_inst_predict;
632
633	LABEL(" * context : %d",context);
634	LABEL(" * port : %d",port);
635
636	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
637	{
638	request_t request;
639	request.context = context;
640	request.address_src = 0xdeadbeef+i;
641	request.address_dest = 0x21071981+i;
642	request.address_good = request.address_dest;
643	request.condition = BRANCH_CONDITION_FLAG_SET;
644	request.take = 1;
645	request.take_good = 1;
646	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
647	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
648	request.is_accurate = true;
649	request.miss_ifetch = false;
650	request.miss_decod = false;
651	request.miss_commit = false;
652	request.history = i;
653	request.ras_address = 0xdeaddead+i;
654	request.ras_index = (0x12345678+i)%_param->_size_ras_index[context];
655	request.ufpt_ptr = ufpt_top [context];
656	// request.upt_ptr;
657
658	bool have_transaction = false;
659	do
660	{
661	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
662	in_PREDICT_CONTEXT_ID [port]->write(request.context );
663	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
664	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
665	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
666	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
667	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
668	in_PREDICT_DIR_HISTORY [port]->write(request.history );
669	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
670	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
671
672	if (_param->_have_port_depth)
673	{
674	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
675	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
676	}
677	SC_START(0); // fct melay
678
679	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
680	port,
681	in_PREDICT_VAL [port]->read(),
682	out_PREDICT_ACK [port]->read(),
683	in_PREDICT_BTB_IS_ACCURATE [port]->read());
684
685	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
686	{
687	LABEL("PREDICT [%d] - Transaction accepted",port);
688	have_transaction = true;
689
690	if (_param->_have_port_depth)
691	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
692
693	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
694	}
695
696	SC_START(1); // transition
697
698	} while (not have_transaction);
699
700	// ufpt.push_back(request);
701
702	in_PREDICT_VAL [port]->write(0);
703
704	if (_param->_have_port_depth)
705	{
706	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
707	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
708	}
709	}
710	}
711
712	{
713	LABEL("DECOD - Miss");
714	uint32_t port = rand() % _param->_nb_inst_decod;
715
716	LABEL(" * context : %d",context);
717	LABEL(" * port : %d",port);
718
719	request_t request;
720	request.context = context;
721	request.address_src = 0x14011959;
722	request.address_dest = 0x25071959; // after = not take
723	request.address_good = request.address_dest;
724	request.condition = BRANCH_CONDITION_FLAG_SET;
725	request.take = 0;
726	request.take_good = 0;
727	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
728	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
729	request.is_accurate = true;
730	request.miss_ifetch = false;
731	request.miss_decod = true ;
732	request.miss_commit = false;
733	request.history = 1;
734	request.ras_address = 0xbabababa;
735	request.ras_index = (0x87654321)%_param->_size_ras_index[context];
736	request.ufpt_ptr = ufpt_top [context];
737	request.upt_ptr = upt_top [context];
738
739	event = request;
740
741	// for (uint32_t i=0; i<upt.size(); i++)
742	// just one
743	{
744	bool have_transaction = false;
745	do
746	{
747	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
748	in_DECOD_CONTEXT_ID [port]->write(request.context );
749	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
750	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
751	in_DECOD_BTB_CONDITION [port]->write(request.condition );
752	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
753	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
754	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
755	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
756	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
757	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
758	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
759
760	SC_START(0); // fct melay
761
762	LABEL("DECOD [%d] %d - %d",
763	port,
764	in_PREDICT_VAL [port]->read(),
765	out_PREDICT_ACK [port]->read());
766
767	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
768	{
769	LABEL("DECOD [%d] - Transaction accepted",port);
770	have_transaction = true;
771
772	request.upt_ptr = upt_top [context];
773	upt.push_back(request);
774	// ufpt.pop_front();
775
776	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
777	}
778
779	SC_START(1); // transition
780
781	} while (not have_transaction);
782
783	in_DECOD_VAL [port]->write(0);
784
785	if (_param->_have_port_depth)
786	{
787	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
788	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
789	}
790	}
791	}
792
793	{
794	LABEL("BRANCH_COMPLETE - hit ifetch");
795
796	uint32_t port = rand() % _param->_nb_inst_branch_complete;
797
798	LABEL(" * port : %d",port);
799
800	std::list<request_t>::iterator it_upt = upt.begin();
801
802	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
803	// for (uint32_t i=0; i<upt.size(); i++)
804	// just one
805	{
806	bool have_transaction = false;
807
808	do
809	{
810	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
811	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
812	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
813	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_good);
814	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence );
815
816	if (_param->_have_port_depth)
817	{
818	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
819	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
820	}
821	SC_START(0);
822
823	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
824
825	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
826	{
827	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
828	have_transaction = true;
829
830	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
831	TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take_good );
832	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
833	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_good);
834
835	it_upt ++;
836	}
837
838	SC_START(1);
839	} while (not have_transaction);
840
841	in_BRANCH_COMPLETE_VAL [port]->write(0);
842
843	if (_param->_have_port_depth)
844	{
845	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
846	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
847	}
848	}
849	}
850
851	{
852	LABEL("UPDATE - hit ifetch");
853
854	uint32_t port = 0;
855
856	LABEL(" * port : %d",port);
857	std::list<request_t>::iterator it_upt = upt.begin();
858
859	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
860	// for (uint32_t i=0; i<upt.size(); i++)
861	// just one
862	{
863	bool have_transaction = false;
864
865	do
866	{
867	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
868
869	// if (_param->_have_port_depth)
870	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
871	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
872
873	SC_START(0);
874
875	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
876
877	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
878	{
879	LABEL("UPDATE [%d] - Transaction accepted",port);
880	have_transaction = true;
881
882	if (_param->_have_port_context_id)
883	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
884	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
885	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
886	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
887	if (update_btb(it_upt->condition))
888	{
889	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
890	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
891	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
892	}
893	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
894
895	if (update_dir(it_upt->condition))
896	if (_param->_have_port_history)
897	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
898	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
899	if (update_ras(it_upt->condition))
900	{
901	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
902	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
903	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
904	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
905	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
906	}
907	++ it_upt;
908	}
909
910	SC_START(1);
911	} while (not have_transaction);
912
913	in_UPDATE_ACK [port]->write(0);
914	// if (_param->_have_port_depth)
915	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
916	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
917	}
918	upt.clear();
919	}
920
921	{
922	LABEL("BRANCH_EVENT - have miss decod");
923
924	uint32_t port = context;
925
926	{
927	bool have_transaction = false;
928
929	do
930	{
931	in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event);
932
933	SC_START(0);
934
935	LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read());
936
937	if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read())
938	{
939	LABEL("BRANCH_EVENT [%d] - Transaction accepted",port);
940	have_transaction = true;
941
942	TEST(Tdepth_t ,out_BRANCH_EVENT_DEPTH [port]->read(),event.upt_ptr);
943	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src);
944	TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take);
945	if (event.take)
946	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good);
947
948	event.address_src = 0;
949	event.take = 0;
950	event.address_dest = 0;
951	}
952
953	SC_START(1);
954	} while (not have_transaction);
955
956	in_BRANCH_EVENT_ACK [port]->write(0);
957	}
958	}
959
960	{
961	LABEL("EVENT_STATE");
962
963	SC_START(1);
964	in_EVENT_VAL [context]->write(1);
965	in_EVENT_TYPE [context]->write(EVENT_TYPE_BRANCH_MISS_SPECULATION);
966
967	SC_START(1);
968	in_EVENT_VAL [context]->write(0);
969	in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE );
970	}
971
972	// Wait Garbage Collector
973	{
974	upt_bottom [context] = (upt_bottom [context]+1)%_param->_size_upt_queue[context];
975	// upt_top [context] = (upt_top [context]);
976
977	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
978	(upt_top [context] != out_DEPTH_MAX [context]->read()))
979	SC_START(1);
980
981	}
982	}
983
984	//---------------------------------------------------------------------
985	//---------------------------------------------------------------------
986	// DECOD MISS : with RAS in ifetch
987	//---------------------------------------------------------------------
988	//---------------------------------------------------------------------
989	if (test3)
990	{
991	uint32_t context = rand() % _param->_nb_context;
992	uint32_t have_ras = false;
993	{
994	LABEL("PREDICT - fill the queue");
995	uint32_t port = rand() % _param->_nb_inst_predict;
996
997	LABEL(" * context : %d",context);
998	LABEL(" * port : %d",port);
999
1000	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1001	{
1002	request_t request;
1003	request.context = context;
1004	request.address_src = 0xdeadbeef+i;
1005	request.address_dest = 0x21071981+i;
1006	request.address_good = request.address_dest;
1007	request.condition = // (rand()%2)?BRANCH_CONDITION_NONE_WITH_WRITE_STACK:
1008	BRANCH_CONDITION_FLAG_SET;
1009
1010	have_ras \|= (update_ras(request.condition));
1011
1012	request.take = 1;
1013	request.take_good = 1;
1014	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
1015	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
1016	request.is_accurate = true;
1017	request.miss_ifetch = false;
1018	request.miss_decod = true ;
1019	request.miss_commit = false;
1020	request.history = i;
1021	request.ras_address = 0x12344321+i;
1022	request.ras_index = (043211234+i)%_param->_size_ras_index[context];
1023	request.ufpt_ptr = ufpt_top [context];
1024	// request.upt_ptr;
1025
1026	bool have_transaction = false;
1027	do
1028	{
1029	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
1030	in_PREDICT_CONTEXT_ID [port]->write(request.context );
1031	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
1032	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1033	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
1034	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
1035	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
1036	in_PREDICT_DIR_HISTORY [port]->write(request.history );
1037	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
1038	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
1039
1040	if (_param->_have_port_depth)
1041	{
1042	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1043	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1044	}
1045	SC_START(0); // fct melay
1046
1047	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
1048	port,
1049	in_PREDICT_VAL [port]->read(),
1050	out_PREDICT_ACK [port]->read(),
1051	in_PREDICT_BTB_IS_ACCURATE [port]->read());
1052
1053	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
1054	{
1055	LABEL("PREDICT [%d] - Transaction accepted",port);
1056	have_transaction = true;
1057
1058	if (_param->_have_port_depth)
1059	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
1060
1061	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
1062	}
1063
1064	SC_START(1); // transition
1065
1066	} while (not have_transaction);
1067
1068	ufpt.push_back(request); // to update
1069
1070	in_PREDICT_VAL [port]->write(0);
1071
1072	if (_param->_have_port_depth)
1073	{
1074	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1075	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1076	}
1077	}
1078	}
1079
1080	{
1081	LABEL("DECOD - Miss");
1082	uint32_t port = rand() % _param->_nb_inst_decod;
1083
1084	LABEL(" * context : %d",context);
1085	LABEL(" * port : %d",port);
1086
1087	request_t request;
1088	request.context = context;
1089	request.address_src = 0x14011959;
1090	request.address_dest = 0x25071959; // after = not take
1091	request.address_good = request.address_dest;
1092	request.condition = BRANCH_CONDITION_FLAG_SET;
1093	request.take = 0;
1094	request.take_good = 0;
1095	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
1096	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
1097	request.is_accurate = true;
1098	request.miss_ifetch = false;
1099	request.miss_decod = true ;
1100	request.miss_commit = false;
1101	request.history = 1;
1102	request.ras_address = 0xbabababa;
1103	request.ras_index = (0x87654321)%_param->_size_ras_index[context];
1104	request.ufpt_ptr = ufpt_top [context];
1105	request.upt_ptr = upt_top [context];
1106
1107	event = request;
1108
1109	// for (uint32_t i=0; i<upt.size(); i++)
1110	// just one
1111	{
1112	bool have_transaction = false;
1113	do
1114	{
1115	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
1116	in_DECOD_CONTEXT_ID [port]->write(request.context );
1117	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
1118	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1119	in_DECOD_BTB_CONDITION [port]->write(request.condition );
1120	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
1121	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
1122	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
1123	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
1124	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
1125	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
1126	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
1127
1128	SC_START(0); // fct melay
1129
1130	LABEL("DECOD [%d] %d - %d",
1131	port,
1132	in_PREDICT_VAL [port]->read(),
1133	out_PREDICT_ACK [port]->read());
1134
1135	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
1136	{
1137	LABEL("DECOD [%d] - Transaction accepted",port);
1138	have_transaction = true;
1139
1140	request.upt_ptr = upt_top [context];
1141	upt.push_back(request);
1142	// ufpt.pop_front();
1143
1144	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
1145	}
1146
1147	SC_START(1); // transition
1148
1149	} while (not have_transaction);
1150
1151	in_DECOD_VAL [port]->write(0);
1152
1153	if (_param->_have_port_depth)
1154	{
1155	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1156	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1157	}
1158	}
1159	}
1160
1161	{
1162	LABEL("BRANCH_COMPLETE - hit ifetch");
1163
1164	uint32_t port = rand() % _param->_nb_inst_branch_complete;
1165
1166	LABEL(" * port : %d",port);
1167
1168	std::list<request_t>::iterator it_upt = upt.begin();
1169
1170	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1171	// for (uint32_t i=0; i<upt.size(); i++)
1172	// just one
1173	{
1174	bool have_transaction = false;
1175
1176	do
1177	{
1178	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
1179	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
1180	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
1181	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_good);
1182	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence );
1183
1184	if (_param->_have_port_depth)
1185	{
1186	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1187	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1188	}
1189	SC_START(0);
1190
1191	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
1192
1193	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
1194	{
1195	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
1196	have_transaction = true;
1197
1198	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
1199	TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take_good );
1200	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
1201	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_good);
1202
1203	it_upt ++;
1204	}
1205
1206	SC_START(1);
1207	} while (not have_transaction);
1208
1209	in_BRANCH_COMPLETE_VAL [port]->write(0);
1210
1211	if (_param->_have_port_depth)
1212	{
1213	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1214	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1215	}
1216	}
1217	}
1218
1219	if (have_ras)
1220	{
1221	LABEL("UPDATE - Update UPFT");
1222
1223	uint32_t port = 0;
1224
1225	LABEL(" * port : %d",port);
1226	std::list<request_t>::iterator it_ufpt = ufpt.end();
1227	-- it_ufpt;
1228
1229	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1230	{
1231	bool have_transaction = false;
1232
1233	do
1234	{
1235	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
1236
1237	// if (_param->_have_port_depth)
1238	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
1239	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
1240
1241	SC_START(0);
1242
1243	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
1244
1245	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
1246	{
1247	LABEL("UPDATE [%d] - Transaction accepted",port);
1248	have_transaction = true;
1249
1250	if (_param->_have_port_context_id)
1251	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_ufpt->context);
1252	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),(it_ufpt->miss_ifetch or
1253	it_ufpt->miss_decod or
1254	it_ufpt->miss_commit ));
1255	// if (update_btb(it_ufpt->condition) or
1256	// update_dir(it_ufpt->condition))
1257	// TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_ufpt->take_good);
1258	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),0);
1259	// if (update_btb(it_ufpt->condition))
1260	// {
1261	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_ufpt->address_src);
1262	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_ufpt->address_dest);
1263	// TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_ufpt->condition);
1264	// }
1265	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),0);
1266
1267	// if (update_dir(it_ufpt->condition))
1268	// if (_param->_have_port_history)
1269	// TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_ufpt->history);
1270	// TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_ufpt->condition));
1271	if (update_ras(it_ufpt->condition))
1272	{
1273	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
1274	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_ufpt->condition));
1275	LABEL("KANE : out_UPDATE_RAS_ADDRESS [port]->read() : %.8x",out_UPDATE_RAS_ADDRESS [port]->read());
1276	LABEL("KANE : it_ufpt->ras_address : %.8x",it_ufpt->ras_address);
1277
1278	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_ufpt->ras_address);
1279	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_ufpt->ras_index);
1280	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch);
1281	}
1282	}
1283
1284	SC_START(1);
1285	} while (not have_transaction);
1286
1287	-- it_ufpt;
1288
1289
1290	in_UPDATE_ACK [port]->write(0);
1291	// if (_param->_have_port_depth)
1292	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
1293	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
1294	}
1295	}
1296	ufpt.clear();
1297
1298	{
1299	LABEL("UPDATE - hit ifetch");
1300
1301	uint32_t port = 0;
1302
1303	LABEL(" * port : %d",port);
1304	std::list<request_t>::iterator it_upt = upt.begin();
1305
1306	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1307	// for (uint32_t i=0; i<upt.size(); i++)
1308	// just one
1309	{
1310	bool have_transaction = false;
1311
1312	do
1313	{
1314	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
1315
1316	// if (_param->_have_port_depth)
1317	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1318	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1319
1320	SC_START(0);
1321
1322	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
1323
1324	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
1325	{
1326	LABEL("UPDATE [%d] - Transaction accepted",port);
1327	have_transaction = true;
1328
1329	if (_param->_have_port_context_id)
1330	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
1331	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
1332	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
1333	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
1334	if (update_btb(it_upt->condition))
1335	{
1336	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
1337	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
1338	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
1339	}
1340	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
1341
1342	if (update_dir(it_upt->condition))
1343	if (_param->_have_port_history)
1344	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
1345	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
1346	if (update_ras(it_upt->condition))
1347	{
1348	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
1349	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
1350	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
1351	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
1352	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
1353	}
1354	++ it_upt;
1355	}
1356
1357	SC_START(1);
1358	} while (not have_transaction);
1359
1360	in_UPDATE_ACK [port]->write(0);
1361	// if (_param->_have_port_depth)
1362	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1363	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1364	}
1365	}
1366	upt.clear();
1367
1368	{
1369	LABEL("BRANCH_EVENT - have miss decod");
1370
1371	uint32_t port = context;
1372
1373	{
1374	bool have_transaction = false;
1375
1376	do
1377	{
1378	in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event);
1379
1380	SC_START(0);
1381
1382	LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read());
1383
1384	if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read())
1385	{
1386	LABEL("BRANCH_EVENT [%d] - Transaction accepted",port);
1387	have_transaction = true;
1388
1389	TEST(Tdepth_t ,out_BRANCH_EVENT_DEPTH [port]->read(),event.upt_ptr);
1390	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src);
1391	TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take);
1392	if (event.take)
1393	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good);
1394
1395	event.address_src = 0;
1396	event.take = 0;
1397	event.address_dest = 0;
1398	}
1399
1400	SC_START(1);
1401	} while (not have_transaction);
1402
1403	in_BRANCH_EVENT_ACK [port]->write(0);
1404	}
1405	}
1406
1407	{
1408	LABEL("EVENT_STATE");
1409
1410	SC_START(1);
1411	in_EVENT_VAL [context]->write(1);
1412	in_EVENT_TYPE [context]->write(EVENT_TYPE_BRANCH_MISS_SPECULATION);
1413
1414	SC_START(1);
1415	in_EVENT_VAL [context]->write(0);
1416	in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE );
1417	}
1418
1419	// Wait Garbage Collector
1420	{
1421	upt_bottom [context] = (upt_bottom [context]+1)%_param->_size_upt_queue[context];
1422	// upt_top [context] = (upt_top [context]);
1423
1424	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
1425	(upt_top [context] != out_DEPTH_MAX [context]->read()))
1426	SC_START(1);
1427	}
1428	}
1429
1430	//---------------------------------------------------------------------
1431	//---------------------------------------------------------------------
1432	// COMMIT MISS : with RAS in UPFT and UPT
1433	//---------------------------------------------------------------------
1434	//---------------------------------------------------------------------
1435	if (test4)
1436	{
1437	uint32_t context = rand() % _param->_nb_context;
1438	uint32_t have_ufpt_ras = false;
1439	uint32_t have_upt_ras = false;
1440	{
1441	LABEL("PREDICT - fill the queue");
1442	uint32_t port = rand() % _param->_nb_inst_predict;
1443
1444	LABEL(" * context : %d",context);
1445	LABEL(" * port : %d",port);
1446
1447	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1448	{
1449	request_t request;
1450	request.context = context;
1451	request.address_src = rand();
1452	request.address_dest = rand();
1453
1454	request.condition = // (rand()%2)?BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK:
1455	BRANCH_CONDITION_FLAG_SET;
1456
1457	request.take = 1;
1458	request.take_good = 1;
1459	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
1460	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
1461	request.is_accurate = true ;
1462	request.miss_ifetch = false;
1463	request.miss_decod = false;
1464	request.miss_commit = false;
1465	request.history = i;
1466	request.ras_address = rand();
1467	request.ras_index = rand()%_param->_size_ras_index[context];
1468	request.ufpt_ptr = ufpt_top [context];
1469	// request.upt_ptr;
1470
1471	bool have_transaction = false;
1472	do
1473	{
1474	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
1475	in_PREDICT_CONTEXT_ID [port]->write(request.context );
1476	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
1477	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1478	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
1479	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
1480	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
1481	in_PREDICT_DIR_HISTORY [port]->write(request.history );
1482	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
1483	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
1484
1485	if (_param->_have_port_depth)
1486	{
1487	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1488	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1489	}
1490	SC_START(0); // fct melay
1491
1492	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
1493	port,
1494	in_PREDICT_VAL [port]->read(),
1495	out_PREDICT_ACK [port]->read(),
1496	in_PREDICT_BTB_IS_ACCURATE [port]->read());
1497
1498	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
1499	{
1500	LABEL("PREDICT [%d] - Transaction accepted",port);
1501	have_transaction = true;
1502
1503	if (_param->_have_port_depth)
1504	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
1505
1506	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
1507	}
1508
1509	SC_START(1); // transition
1510
1511	} while (not have_transaction);
1512
1513	ufpt.push_back(request); // to update
1514
1515	in_PREDICT_VAL [port]->write(0);
1516
1517	if (_param->_have_port_depth)
1518	{
1519	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1520	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1521	}
1522	}
1523	}
1524
1525	{
1526	LABEL("DECOD");
1527	uint32_t port = rand() % _param->_nb_inst_decod;
1528
1529	LABEL(" * context : %d",context);
1530	LABEL(" * port : %d",port);
1531
1532	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1533	{
1534	request_t request = ufpt.front();
1535
1536	bool have_transaction = false;
1537	do
1538	{
1539	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
1540	in_DECOD_CONTEXT_ID [port]->write(request.context );
1541	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
1542	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1543	in_DECOD_BTB_CONDITION [port]->write(request.condition );
1544	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
1545	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
1546	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
1547	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
1548	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
1549	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
1550	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
1551
1552	have_upt_ras \|= (update_ras(request.condition));
1553
1554	SC_START(0); // fct melay
1555
1556	LABEL("DECOD [%d] %d - %d",
1557	port,
1558	in_DECOD_VAL [port]->read(),
1559	out_DECOD_ACK [port]->read());
1560
1561	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
1562	{
1563	LABEL("DECOD [%d] - Transaction accepted",port);
1564	have_transaction = true;
1565
1566	request.upt_ptr = upt_top [context];
1567	upt.push_back(request);
1568	ufpt.pop_front();
1569
1570	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
1571	}
1572
1573	SC_START(1); // transition
1574
1575	} while (not have_transaction);
1576
1577	in_DECOD_VAL [port]->write(0);
1578
1579	if (_param->_have_port_depth)
1580	{
1581	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1582	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1583	}
1584	}
1585	}
1586
1587	{
1588	LABEL("PREDICT - fill the queue");
1589	uint32_t port = rand() % _param->_nb_inst_predict;
1590
1591	LABEL(" * context : %d",context);
1592	LABEL(" * port : %d",port);
1593
1594	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1595	{
1596	request_t request;
1597	request.context = context;
1598	request.address_src = rand();
1599	request.address_dest = rand();
1600	request.address_good = request.address_dest;
1601	request.condition = // (rand()%2)?BRANCH_CONDITION_NONE_WITH_WRITE_STACK:
1602	BRANCH_CONDITION_FLAG_SET;
1603
1604	have_ufpt_ras \|= (update_ras(request.condition));
1605
1606	request.take = 1;
1607	request.take_good = 1;
1608	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
1609	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
1610	request.is_accurate = true ;
1611	request.miss_ifetch = false;
1612	request.miss_decod = false;
1613	request.miss_commit = true;
1614	request.history = i;
1615	request.ras_address = rand();
1616	request.ras_index = rand()%_param->_size_ras_index[context];
1617	request.ufpt_ptr = ufpt_top [context];
1618	// request.upt_ptr;
1619
1620	bool have_transaction = false;
1621	do
1622	{
1623	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
1624	in_PREDICT_CONTEXT_ID [port]->write(request.context );
1625	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
1626	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1627	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
1628	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
1629	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
1630	in_PREDICT_DIR_HISTORY [port]->write(request.history );
1631	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
1632	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
1633
1634	if (_param->_have_port_depth)
1635	{
1636	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1637	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1638	}
1639	SC_START(0); // fct melay
1640
1641	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
1642	port,
1643	in_PREDICT_VAL [port]->read(),
1644	out_PREDICT_ACK [port]->read(),
1645	in_PREDICT_BTB_IS_ACCURATE [port]->read());
1646
1647	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
1648	{
1649	LABEL("PREDICT [%d] - Transaction accepted",port);
1650	have_transaction = true;
1651
1652	if (_param->_have_port_depth)
1653	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
1654
1655	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
1656	}
1657
1658	SC_START(1); // transition
1659
1660	} while (not have_transaction);
1661
1662	ufpt.push_back(request); // to update
1663
1664	in_PREDICT_VAL [port]->write(0);
1665
1666	if (_param->_have_port_depth)
1667	{
1668	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1669	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1670	}
1671	}
1672	}
1673
1674	std::list<request_t>::iterator it_event;
1675	{
1676	LABEL("BRANCH_COMPLETE - Miss ifetch");
1677
1678	uint32_t port = rand() % _param->_nb_inst_branch_complete;
1679
1680	LABEL(" * port : %d",port);
1681
1682	// middle
1683	it_event = upt.begin();
1684	for (uint32_t i=0; i < (upt.size()>>1); ++i)
1685	it_event ++;
1686
1687	for (std::list<request_t>::iterator it_upt = it_event;
1688	it_upt != upt.end();
1689	++it_upt)
1690	it_upt->miss_commit = true;
1691
1692	if (update_ras(it_event->condition))
1693	{
1694	it_event->address_good = ~(it_event->address_dest);
1695	}
1696	else
1697	{
1698	it_event->address_good = it_event->address_dest;
1699	it_event->flag = not it_event->flag;
1700	it_event->no_sequence = not it_event->no_sequence;
1701	it_event->take_good = not it_event->take_good;
1702	}
1703
1704	event = *it_event;
1705
1706
1707	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1708	// for (uint32_t i=0; i<upt.size(); i++)
1709	// just one
1710	{
1711	bool have_transaction = false;
1712
1713	do
1714	{
1715	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
1716	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_event->context );
1717	in_BRANCH_COMPLETE_DEPTH [port]->write(it_event->upt_ptr );
1718	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_event->address_good);
1719	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_event->no_sequence );
1720
1721	if (_param->_have_port_depth)
1722	{
1723	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1724	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1725	}
1726
1727	SC_START(0);
1728
1729	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
1730
1731	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
1732	{
1733	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
1734	LABEL(" * CONTEXT_ID : %d" ,it_event->context );
1735	LABEL(" * DEPTH : %d" ,it_event->upt_ptr );
1736	LABEL(" * CONDITION : %d" ,it_event->condition );
1737	LABEL(" * ADDRESS : %.8x",it_event->address_good);
1738	LABEL(" * FLAG : %d" ,it_event->flag );
1739	LABEL(" * NO_SEQUENCE : %d" ,it_event->no_sequence );
1740
1741	have_transaction = true;
1742
1743	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_event->miss_commit );
1744	TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_event->take_good );
1745	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_event->address_src );
1746	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_event->address_good);
1747
1748	upt_top_event [it_event->context] = upt_top [it_event->context];
1749	upt_top [it_event->context] = it_event->upt_ptr;
1750	}
1751
1752	SC_START(1);
1753	} while (not have_transaction);
1754
1755	in_BRANCH_COMPLETE_VAL [port]->write(0);
1756
1757	if (_param->_have_port_depth)
1758	{
1759	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1760	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1761	}
1762	}
1763	}
1764
1765	{
1766	LABEL("BRANCH_COMPLETE - Hit ifetch");
1767
1768	uint32_t port = rand() % _param->_nb_inst_branch_complete;
1769
1770	LABEL(" * port : %d",port);
1771
1772	std::list<request_t>::iterator it_upt = upt.begin();
1773
1774	while (it_upt != it_event)
1775	{
1776	bool have_transaction = false;
1777
1778	do
1779	{
1780	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
1781	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
1782	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
1783	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_dest);
1784	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence );
1785
1786	if (_param->_have_port_depth)
1787	{
1788	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1789	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1790	}
1791	SC_START(0);
1792
1793	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
1794
1795	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
1796	{
1797	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
1798	LABEL(" * CONTEXT_ID : %d" ,it_upt->context );
1799	LABEL(" * DEPTH : %d" ,it_upt->upt_ptr );
1800	LABEL(" * CONDITION : %d" ,it_upt->condition );
1801	LABEL(" * ADDRESS : %.8x",it_upt->address_dest);
1802	LABEL(" * FLAG : %d" ,it_upt->flag );
1803	LABEL(" * NO_SEQUENCE : %d" ,it_event->no_sequence );
1804
1805	have_transaction = true;
1806
1807	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
1808	TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take );
1809	it_upt->take_good = it_upt->take;
1810	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
1811	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_dest);
1812
1813	it_upt++;
1814	}
1815
1816	SC_START(1);
1817	} while (not have_transaction);
1818
1819	in_BRANCH_COMPLETE_VAL [port]->write(0);
1820
1821	if (_param->_have_port_depth)
1822	{
1823	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1824	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1825	}
1826	}
1827	}
1828
1829	if (have_ufpt_ras)
1830	{
1831	LABEL("UPDATE - Update UPFT");
1832
1833	uint32_t port = 0;
1834
1835	LABEL(" * port : %d",port);
1836	std::list<request_t>::iterator it_ufpt = ufpt.end();
1837	-- it_ufpt;
1838
1839	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1840	{
1841	bool have_transaction = false;
1842
1843	do
1844	{
1845	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
1846
1847	// if (_param->_have_port_depth)
1848	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
1849	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
1850
1851	SC_START(0);
1852
1853	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
1854
1855	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
1856	{
1857	LABEL("UPDATE [%d] - Transaction accepted",port);
1858	have_transaction = true;
1859
1860	if (_param->_have_port_context_id)
1861	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_ufpt->context);
1862	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),(it_ufpt->miss_ifetch or
1863	it_ufpt->miss_decod or
1864	it_ufpt->miss_commit ));
1865	// if (update_btb(it_ufpt->condition) or
1866	// update_dir(it_ufpt->condition))
1867	// TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_ufpt->take_good);
1868	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),0);
1869	// if (update_btb(it_ufpt->condition))
1870	// {
1871	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_ufpt->address_src);
1872	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_ufpt->address_dest);
1873	// TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_ufpt->condition);
1874	// }
1875	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),0);
1876
1877	// if (update_dir(it_ufpt->condition))
1878	// if (_param->_have_port_history)
1879	// TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_ufpt->history);
1880	// TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_ufpt->condition));
1881	if (update_ras(it_ufpt->condition))
1882	{
1883	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
1884	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_ufpt->condition));
1885	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_ufpt->ras_address);
1886	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_ufpt->ras_index);
1887	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch);
1888	}
1889	}
1890
1891	SC_START(1);
1892	} while (not have_transaction);
1893
1894	-- it_ufpt;
1895
1896
1897	in_UPDATE_ACK [port]->write(0);
1898	// if (_param->_have_port_depth)
1899	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
1900	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
1901	}
1902	}
1903	ufpt.clear();
1904
1905	{
1906	LABEL("UPDATE - upt (after event)");
1907
1908	uint32_t port = 0;
1909
1910	LABEL(" * port : %d",port);
1911	std::list<request_t>::iterator it_upt = upt.end();
1912
1913	// for (uint32_t i=0; i<upt.size(); i++)
1914	do
1915	{
1916	--it_upt;
1917
1918	bool have_transaction = false;
1919
1920	if (need_update(it_upt->condition))
1921	do
1922	{
1923	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
1924
1925	// if (_param->_have_port_depth)
1926	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1927	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1928
1929	SC_START(0);
1930
1931	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
1932
1933	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
1934	{
1935	LABEL("UPDATE [%d] - Transaction accepted",port);
1936	LABEL(" * address_src : %.8x",it_upt->address_src);
1937	LABEL(" * out_UPDATE_BTB_ADDRESS_SRC : %.8x",out_UPDATE_BTB_ADDRESS_SRC[port]->read());
1938
1939	have_transaction = true;
1940
1941	bool btb_val = ((it_upt == it_event) and
1942	(update_btb(it_upt->condition)));
1943	bool dir_val = ((it_upt == it_event) and
1944	update_dir(it_upt->condition) and
1945	not (it_upt->miss_ifetch or it_upt->miss_decod));
1946	bool ras_val = update_ras(it_upt->condition);
1947
1948	if (_param->_have_port_context_id)
1949	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
1950	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
1951	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),btb_val);
1952
1953	if (btb_val)
1954	{
1955	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
1956	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
1957	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
1958	}
1959	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),dir_val);
1960
1961	if (dir_val)
1962	{
1963	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
1964	if (_param->_have_port_history)
1965	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
1966	}
1967	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),ras_val);
1968
1969	if (ras_val)
1970	{
1971	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
1972	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
1973	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
1974	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
1975	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
1976	}
1977
1978	// -- it_upt;
1979	}
1980
1981	SC_START(1);
1982	} while (not have_transaction);
1983
1984	upt.pop_back();
1985	in_UPDATE_ACK [port]->write(0);
1986	// if (_param->_have_port_depth)
1987	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1988	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1989	}
1990	while (it_upt != it_event);
1991
1992	}
1993
1994	{
1995	LABEL("BRANCH_EVENT - have miss decod");
1996
1997	uint32_t port = context;
1998
1999	{
2000	bool have_transaction = false;
2001
2002	do
2003	{
2004	in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event);
2005
2006	SC_START(0);
2007
2008	LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read());
2009
2010	if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read())
2011	{
2012	LABEL("BRANCH_EVENT [%d] - Transaction accepted",port);
2013	have_transaction = true;
2014
2015	LABEL(" * event.address_src : %.8x,",event.address_src );
2016	LABEL(" * event.address_good : %.8x,",event.address_good);
2017	LABEL(" * event.take : %.8x,",event.take );
2018
2019	TEST(Tdepth_t ,out_BRANCH_EVENT_DEPTH [port]->read(),event.upt_ptr);
2020	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src);
2021	TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take_good);
2022	if (event.take_good)
2023	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good);
2024
2025	event.address_src = 0;
2026	event.take = 0;
2027	event.address_dest = 0;
2028	}
2029
2030	SC_START(1);
2031	} while (not have_transaction);
2032
2033	in_BRANCH_EVENT_ACK [port]->write(0);
2034	}
2035	}
2036
2037	{
2038	LABEL("EVENT_STATE");
2039
2040	SC_START(1);
2041	in_EVENT_VAL [context]->write(1);
2042	in_EVENT_TYPE [context]->write(EVENT_TYPE_BRANCH_MISS_SPECULATION);
2043
2044	SC_START(1);
2045	in_EVENT_VAL [context]->write(0);
2046	in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE );
2047	}
2048
2049	{
2050	LABEL("UPDATE - upt (before event)");
2051
2052	uint32_t port = 0;
2053
2054	LABEL(" * port : %d",port);
2055	LABEL(" * size : %d",upt.size());
2056	std::list<request_t>::iterator it_upt = upt.begin();
2057
2058	for (uint32_t i=0; i<upt.size(); i++)
2059	{
2060	bool have_transaction = false;
2061
2062	do
2063	{
2064	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
2065
2066	// if (_param->_have_port_depth)
2067	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2068	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2069
2070	SC_START(0);
2071
2072	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
2073
2074	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
2075	{
2076	LABEL("UPDATE [%d] - Transaction accepted",port);
2077	have_transaction = true;
2078
2079	if (_param->_have_port_context_id)
2080	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
2081	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
2082	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
2083	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
2084	if (update_btb(it_upt->condition))
2085	{
2086	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
2087	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
2088	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
2089	}
2090	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
2091
2092	if (update_dir(it_upt->condition))
2093	if (_param->_have_port_history)
2094	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
2095	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
2096	if (update_ras(it_upt->condition))
2097	{
2098	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
2099	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
2100	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
2101	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
2102	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
2103	}
2104
2105	++ it_upt;
2106	}
2107
2108	SC_START(1);
2109	} while (not have_transaction);
2110
2111	in_UPDATE_ACK [port]->write(0);
2112	// if (_param->_have_port_depth)
2113	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2114	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2115	}
2116	}
2117	upt.clear();
2118
2119	// Wait Garbage Collector
2120	{
2121	LABEL("GARBAGE COLLECTOR");
2122	LABEL(" * upt bottom : %d",upt_bottom [context]);
2123	LABEL(" * upt top : %d",upt_top [context]);
2124
2125	upt_top [context] = (upt_top_event [context]);
2126	upt_bottom [context] = (upt_top [context]);
2127
2128	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
2129	(upt_top [context] != out_DEPTH_MAX [context]->read()))
2130	{
2131	SC_START(1);
2132	}
2133
2134	}
2135	}
2136
2137	//---------------------------------------------------------------------
2138	//---------------------------------------------------------------------
2139	// COMMIT MISS : with RAS in UPFT and UPT
2140	//---------------------------------------------------------------------
2141	//---------------------------------------------------------------------
2142	if (test5)
2143	{
2144	uint32_t context = rand() % _param->_nb_context;
2145	uint32_t have_ufpt_ras = false;
2146	uint32_t have_upt_ras = false;
2147
2148	{
2149	LABEL("PREDICT - fill the queue");
2150	uint32_t port = rand() % _param->_nb_inst_predict;
2151
2152	LABEL(" * context : %d",context);
2153	LABEL(" * port : %d",port);
2154
2155	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
2156	{
2157	request_t request;
2158	request.context = context;
2159	request.address_src = rand();
2160	request.address_dest = rand();
2161
2162	request.condition = // (rand()%2)?BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK:
2163	BRANCH_CONDITION_FLAG_SET;
2164
2165	request.take = 1;
2166	request.take_good = 1;
2167	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
2168	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
2169	request.is_accurate = true ;
2170	request.miss_ifetch = false;
2171	request.miss_decod = false;
2172	request.miss_commit = false;
2173	request.history = i;
2174	request.ras_address = rand();
2175	request.ras_index = rand()%_param->_size_ras_index[context];
2176	request.ufpt_ptr = ufpt_top [context];
2177	// request.upt_ptr;
2178
2179	bool have_transaction = false;
2180	do
2181	{
2182	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
2183	in_PREDICT_CONTEXT_ID [port]->write(request.context );
2184	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
2185	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
2186	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
2187	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
2188	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
2189	in_PREDICT_DIR_HISTORY [port]->write(request.history );
2190	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
2191	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
2192
2193	if (_param->_have_port_depth)
2194	{
2195	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2196	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2197	}
2198	SC_START(0); // fct melay
2199
2200	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
2201	port,
2202	in_PREDICT_VAL [port]->read(),
2203	out_PREDICT_ACK [port]->read(),
2204	in_PREDICT_BTB_IS_ACCURATE [port]->read());
2205
2206	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
2207	{
2208	LABEL("PREDICT [%d] - Transaction accepted",port);
2209	have_transaction = true;
2210
2211	if (_param->_have_port_depth)
2212	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
2213
2214	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
2215	}
2216
2217	SC_START(1); // transition
2218
2219	} while (not have_transaction);
2220
2221	ufpt.push_back(request); // to update
2222
2223	in_PREDICT_VAL [port]->write(0);
2224
2225	if (_param->_have_port_depth)
2226	{
2227	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2228	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2229	}
2230	}
2231	}
2232
2233	{
2234	LABEL("DECOD");
2235	uint32_t port = rand() % _param->_nb_inst_decod;
2236
2237	LABEL(" * context : %d",context);
2238	LABEL(" * port : %d",port);
2239
2240	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
2241	{
2242	request_t request = ufpt.front();
2243
2244	bool have_transaction = false;
2245	do
2246	{
2247	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
2248	in_DECOD_CONTEXT_ID [port]->write(request.context );
2249	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
2250	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
2251	in_DECOD_BTB_CONDITION [port]->write(request.condition );
2252	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
2253	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
2254	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
2255	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
2256	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
2257	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
2258	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
2259
2260	have_upt_ras \|= (update_ras(request.condition));
2261
2262	SC_START(0); // fct melay
2263
2264	LABEL("DECOD [%d] %d - %d",
2265	port,
2266	in_DECOD_VAL [port]->read(),
2267	out_DECOD_ACK [port]->read());
2268
2269	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
2270	{
2271	LABEL("DECOD [%d] - Transaction accepted",port);
2272	have_transaction = true;
2273
2274	request.upt_ptr = upt_top [context];
2275	upt.push_back(request);
2276	ufpt.pop_front();
2277
2278	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
2279	}
2280
2281	SC_START(1); // transition
2282
2283	} while (not have_transaction);
2284
2285	in_DECOD_VAL [port]->write(0);
2286
2287	if (_param->_have_port_depth)
2288	{
2289	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2290	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2291	}
2292	}
2293	}
2294
2295	{
2296	LABEL("PREDICT - fill the queue");
2297	uint32_t port = rand() % _param->_nb_inst_predict;
2298
2299	LABEL(" * context : %d",context);
2300	LABEL(" * port : %d",port);
2301
2302	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
2303	{
2304	request_t request;
2305	request.context = context;
2306	request.address_src = rand();
2307	request.address_dest = rand();
2308	request.address_good = request.address_dest;
2309	request.condition = // (rand()%2)?BRANCH_CONDITION_NONE_WITH_WRITE_STACK:
2310	BRANCH_CONDITION_FLAG_SET;
2311
2312	have_ufpt_ras \|= (update_ras(request.condition));
2313
2314	request.take = 1;
2315	request.take_good = 1;
2316	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
2317	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
2318	request.is_accurate = true ;
2319	request.miss_ifetch = false;
2320	request.miss_decod = false;
2321	request.miss_commit = true;
2322	request.history = i;
2323	request.ras_address = rand();
2324	request.ras_index = rand()%_param->_size_ras_index[context];
2325	request.ufpt_ptr = ufpt_top [context];
2326	// request.upt_ptr;
2327
2328	bool have_transaction = false;
2329	do
2330	{
2331	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
2332	in_PREDICT_CONTEXT_ID [port]->write(request.context );
2333	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
2334	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
2335	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
2336	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
2337	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
2338	in_PREDICT_DIR_HISTORY [port]->write(request.history );
2339	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
2340	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
2341
2342	if (_param->_have_port_depth)
2343	{
2344	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2345	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2346	}
2347	SC_START(0); // fct melay
2348
2349	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
2350	port,
2351	in_PREDICT_VAL [port]->read(),
2352	out_PREDICT_ACK [port]->read(),
2353	in_PREDICT_BTB_IS_ACCURATE [port]->read());
2354
2355	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
2356	{
2357	LABEL("PREDICT [%d] - Transaction accepted",port);
2358	have_transaction = true;
2359
2360	if (_param->_have_port_depth)
2361	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
2362
2363	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
2364	}
2365
2366	SC_START(1); // transition
2367
2368	} while (not have_transaction);
2369
2370	ufpt.push_back(request); // to update
2371
2372	in_PREDICT_VAL [port]->write(0);
2373
2374	if (_param->_have_port_depth)
2375	{
2376	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2377	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2378	}
2379	}
2380	}
2381
2382	uint32_t nb_branch_before_event = 0;
2383	{
2384	// middle
2385	std::list<request_t>::iterator it_event = upt.begin();
2386	for (uint32_t i=0; i < (upt.size()>>1); ++i)
2387	{
2388	nb_branch_before_event ++;
2389	it_event ++;
2390	}
2391	for (std::list<request_t>::iterator it = it_event; it != upt.end(); ++it)
2392	it->miss_commit = true;
2393
2394	bool have_transaction = false;
2395
2396	do
2397	{
2398	PORT_WRITE(in_EVENT_VAL [context],(rand()%100)<percent_transaction_event);
2399	PORT_WRITE(in_EVENT_TYPE [context],EVENT_TYPE_LOAD_MISS_SPECULATION);
2400	PORT_WRITE(in_EVENT_DEPTH [context],it_event->upt_ptr);
2401
2402	SC_START(0);
2403
2404	if (PORT_READ(in_EVENT_VAL [context]) and PORT_READ(out_EVENT_ACK [context]))
2405	{
2406	LABEL("EVENT [%d] - Transaction accepted",context);
2407
2408	have_transaction = true;
2409	}
2410
2411	SC_START(1);
2412	}
2413	while (not have_transaction);
2414	PORT_WRITE(in_EVENT_VAL [context],0);
2415
2416	upt_top_event [it_event->context] = upt_top [it_event->context];
2417	upt_top [it_event->context] = it_event->upt_ptr;
2418	}
2419
2420	{
2421	LABEL("BRANCH_COMPLETE - Hit ifetch");
2422
2423	uint32_t port = rand() % _param->_nb_inst_branch_complete;
2424
2425	LABEL(" * port : %d",port);
2426
2427	std::list<request_t>::iterator it_upt = upt.begin();
2428
2429	for (uint32_t i=0; i<nb_branch_before_event; ++i)
2430	{
2431	bool have_transaction = false;
2432
2433	do
2434	{
2435	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
2436	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
2437	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
2438	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_dest);
2439	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence );
2440
2441	if (_param->_have_port_depth)
2442	{
2443	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2444	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2445	}
2446	SC_START(0);
2447
2448	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
2449
2450	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
2451	{
2452	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
2453	LABEL(" * CONTEXT_ID : %d" ,it_upt->context );
2454	LABEL(" * DEPTH : %d" ,it_upt->upt_ptr );
2455	LABEL(" * CONDITION : %d" ,it_upt->condition );
2456	LABEL(" * ADDRESS : %.8x",it_upt->address_dest);
2457	LABEL(" * FLAG : %d" ,it_upt->flag );
2458	LABEL(" * NO_SEQUENCE : %d" ,it_upt->no_sequence );
2459
2460	have_transaction = true;
2461
2462	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
2463	TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take );
2464	it_upt->take_good = it_upt->take;
2465	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
2466	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_dest);
2467
2468	it_upt++;
2469	}
2470
2471	SC_START(1);
2472
2473	} while (not have_transaction);
2474
2475	in_BRANCH_COMPLETE_VAL [port]->write(0);
2476
2477	if (_param->_have_port_depth)
2478	{
2479	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2480	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2481	}
2482	}
2483	}
2484
2485	if (have_ufpt_ras)
2486	{
2487	LABEL("UPDATE - Update UPFT");
2488
2489	uint32_t port = 0;
2490
2491	LABEL(" * port : %d",port);
2492	std::list<request_t>::iterator it_ufpt = ufpt.end();
2493	-- it_ufpt;
2494
2495	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
2496	{
2497	bool have_transaction = false;
2498
2499	do
2500	{
2501	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
2502
2503	// if (_param->_have_port_depth)
2504	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
2505	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
2506
2507	SC_START(0);
2508
2509	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
2510
2511	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
2512	{
2513	LABEL("UPDATE [%d] - Transaction accepted",port);
2514	have_transaction = true;
2515
2516	if (_param->_have_port_context_id)
2517	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_ufpt->context);
2518	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),(it_ufpt->miss_ifetch or
2519	it_ufpt->miss_decod or
2520	it_ufpt->miss_commit ));
2521	// if (update_btb(it_ufpt->condition) or
2522	// update_dir(it_ufpt->condition))
2523	// TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_ufpt->take_good);
2524	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),0);
2525	// if (update_btb(it_ufpt->condition))
2526	// {
2527	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_ufpt->address_src);
2528	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_ufpt->address_dest);
2529	// TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_ufpt->condition);
2530	// }
2531	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),0);
2532
2533	// if (update_dir(it_ufpt->condition))
2534	// if (_param->_have_port_history)
2535	// TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_ufpt->history);
2536	// TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_ufpt->condition));
2537	if (update_ras(it_ufpt->condition))
2538	{
2539	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
2540	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_ufpt->condition));
2541	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_ufpt->ras_address);
2542	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_ufpt->ras_index);
2543	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch);
2544	}
2545	}
2546
2547	SC_START(1);
2548	} while (not have_transaction);
2549
2550	-- it_ufpt;
2551
2552
2553	in_UPDATE_ACK [port]->write(0);
2554	// if (_param->_have_port_depth)
2555	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
2556	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
2557	}
2558	}
2559	ufpt.clear();
2560
2561	{
2562	LABEL("UPDATE - upt (after event)");
2563
2564	uint32_t port = 0;
2565
2566	LABEL(" * port : %d",port);
2567
2568	std::list<request_t>::iterator it_upt = upt.end();
2569
2570	// for (uint32_t i=0; i<upt.size(); i++)
2571
2572	uint32_t size = upt.size();
2573
2574	LABEL(" * size : %d",size);
2575	LABEL(" * nb_branch_before_event : %d",nb_branch_before_event);
2576
2577	for (uint32_t i=nb_branch_before_event; i<size; ++i)
2578	{
2579	--it_upt;
2580
2581	bool have_transaction = false;
2582
2583	if (need_update(it_upt->condition))
2584	do
2585	{
2586	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
2587
2588	// if (_param->_have_port_depth)
2589	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2590	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2591
2592	SC_START(0);
2593
2594	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
2595
2596	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
2597	{
2598	LABEL("UPDATE [%d] - Transaction accepted",port);
2599	LABEL(" * address_src : %.8x",it_upt->address_src);
2600	LABEL(" * out_UPDATE_BTB_ADDRESS_SRC : %.8x",out_UPDATE_BTB_ADDRESS_SRC[port]->read());
2601
2602	have_transaction = true;
2603
2604	bool btb_val = ((update_btb(it_upt->condition)));
2605	bool dir_val = (update_dir(it_upt->condition) and
2606	not (it_upt->miss_ifetch or it_upt->miss_decod));
2607	bool ras_val = update_ras(it_upt->condition);
2608
2609	if (_param->_have_port_context_id)
2610	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
2611	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
2612	// TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),btb_val);
2613
2614	// if (btb_val)
2615	// {
2616	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
2617	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
2618	// TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
2619	// }
2620	// TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),dir_val);
2621
2622	// if (dir_val)
2623	// {
2624	// TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
2625	// if (_param->_have_port_history)
2626	// TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
2627	// }
2628	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),ras_val);
2629
2630	if (ras_val)
2631	{
2632	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
2633	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
2634	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
2635	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
2636	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
2637	}
2638	// -- it_upt;
2639	}
2640
2641	SC_START(1);
2642	} while (not have_transaction);
2643
2644	upt.pop_back();
2645	in_UPDATE_ACK [port]->write(0);
2646	// if (_param->_have_port_depth)
2647	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2648	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2649	}
2650	}
2651
2652	/*
2653	{
2654	LABEL("BRANCH_EVENT - have miss decod");
2655
2656	uint32_t port = context;
2657
2658	{
2659	bool have_transaction = false;
2660
2661	do
2662	{
2663	in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event);
2664
2665	SC_START(0);
2666
2667	LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read());
2668
2669	if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read())
2670	{
2671	LABEL("BRANCH_EVENT [%d] - Transaction accepted",port);
2672	have_transaction = true;
2673
2674	LABEL(" * event.address_src : %.8x,",event.address_src );
2675	LABEL(" * event.address_good : %.8x,",event.address_good);
2676	LABEL(" * event.take : %.8x,",event.take );
2677
2678	TEST(Tdepth_t ,out_BRANCH_EVENT_DEPTH [port]->read(),event.upt_ptr);
2679	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src);
2680	TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take_good);
2681	if (event.take_good)
2682	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good);
2683
2684	event.address_src = 0;
2685	event.take = 0;
2686	event.address_dest = 0;
2687	}
2688
2689	SC_START(1);
2690	} while (not have_transaction);
2691
2692	in_BRANCH_EVENT_ACK [port]->write(0);
2693	}
2694	}
2695
2696	{
2697	LABEL("EVENT_STATE");
2698
2699	SC_START(1);
2700	in_EVENT_VAL [context]->write(1);
2701	in_EVENT_TYPE [context]->write(EVENT_TYPE_BRANCH_MISS_SPECULATION);
2702
2703	SC_START(1);
2704	in_EVENT_VAL [context]->write(0);
2705	in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE );
2706	}
2707	*/
2708
2709	{
2710	LABEL("UPDATE - upt (before event)");
2711
2712	uint32_t port = 0;
2713
2714	LABEL(" * port : %d",port);
2715	LABEL(" * size : %d",upt.size());
2716	std::list<request_t>::iterator it_upt = upt.begin();
2717
2718	for (uint32_t i=0; i<upt.size(); i++)
2719	{
2720	bool have_transaction = false;
2721
2722	do
2723	{
2724	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
2725
2726	// if (_param->_have_port_depth)
2727	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2728	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2729
2730	SC_START(0);
2731
2732	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
2733
2734	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
2735	{
2736	LABEL("UPDATE [%d] - Transaction accepted",port);
2737	have_transaction = true;
2738
2739	if (_param->_have_port_context_id)
2740	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
2741	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
2742	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
2743	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
2744	if (update_btb(it_upt->condition))
2745	{
2746	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
2747	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
2748	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
2749	}
2750	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
2751
2752	if (update_dir(it_upt->condition))
2753	if (_param->_have_port_history)
2754	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
2755	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
2756	if (update_ras(it_upt->condition))
2757	{
2758	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
2759	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
2760	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
2761	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
2762	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
2763	}
2764
2765	++ it_upt;
2766	}
2767
2768	SC_START(1);
2769	} while (not have_transaction);
2770
2771	in_UPDATE_ACK [port]->write(0);
2772	// if (_param->_have_port_depth)
2773	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2774	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2775	}
2776	}
2777
2778	upt.clear();
2779
2780	// Wait Garbage Collector
2781	{
2782	LABEL("GARBAGE COLLECTOR");
2783	LABEL(" * upt bottom : %d",upt_bottom [context]);
2784	LABEL(" * upt top : %d",upt_top [context]);
2785
2786	upt_top [context] = (upt_top_event [context]);
2787	upt_bottom [context] = (upt_top [context]);
2788
2789	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
2790	(upt_top [context] != out_DEPTH_MAX [context]->read()))
2791	{
2792	SC_START(1);
2793	}
2794	}
2795	}
2796
2797	}// ITERATION
2798
2799	/********************************************************
2800	* Simulation - End
2801	********************************************************/
2802
2803	TEST_OK ("End of Simulation");
2804	delete _time;
2805
2806	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
2807
2808	delete in_CLOCK;
2809	delete in_NRESET;
2810
2811	// ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2812	delete [] in_PREDICT_VAL ;
2813	delete [] out_PREDICT_ACK ;
2814	delete [] in_PREDICT_CONTEXT_ID ;
2815	delete [] in_PREDICT_BTB_ADDRESS_SRC ;
2816	delete [] in_PREDICT_BTB_ADDRESS_DEST ;
2817	delete [] in_PREDICT_BTB_CONDITION ;
2818	delete [] in_PREDICT_BTB_LAST_TAKE ;
2819	delete [] in_PREDICT_BTB_IS_ACCURATE ;
2820	delete [] in_PREDICT_DIR_HISTORY ;
2821	delete [] in_PREDICT_RAS_ADDRESS ;
2822	delete [] in_PREDICT_RAS_INDEX ;
2823	delete [] out_PREDICT_UPDATE_PREDICTION_ID;
2824
2825	// ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2826	delete [] in_DECOD_VAL ;
2827	delete [] out_DECOD_ACK ;
2828	delete [] in_DECOD_CONTEXT_ID ;
2829	delete [] in_DECOD_BTB_ADDRESS_SRC ;
2830	delete [] in_DECOD_BTB_ADDRESS_DEST ;
2831	delete [] in_DECOD_BTB_CONDITION ;
2832	delete [] in_DECOD_BTB_LAST_TAKE ;
2833	delete [] in_DECOD_RAS_ADDRESS ;
2834	delete [] in_DECOD_RAS_INDEX ;
2835	delete [] in_DECOD_MISS_IFETCH ;
2836	delete [] in_DECOD_MISS_DECOD ;
2837	delete [] in_DECOD_UPDATE_PREDICTION_ID ;
2838	//delete [] out_DECOD_DEPTH ;
2839	delete [] in_DECOD_IS_ACCURATE ;
2840
2841	// ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2842	delete [] in_BRANCH_COMPLETE_VAL ;
2843	delete [] out_BRANCH_COMPLETE_ACK ;
2844	delete [] in_BRANCH_COMPLETE_CONTEXT_ID ;
2845	delete [] in_BRANCH_COMPLETE_DEPTH ;
2846	delete [] in_BRANCH_COMPLETE_ADDRESS ;
2847	delete [] in_BRANCH_COMPLETE_NO_SEQUENCE ;
2848	delete [] out_BRANCH_COMPLETE_MISS_PREDICTION;
2849	delete [] out_BRANCH_COMPLETE_TAKE ;
2850	delete [] out_BRANCH_COMPLETE_ADDRESS_SRC ;
2851	delete [] out_BRANCH_COMPLETE_ADDRESS_DEST ;
2852
2853	// ~~~~~[ Interface : "branch_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2854	delete [] out_BRANCH_EVENT_VAL ;
2855	delete [] in_BRANCH_EVENT_ACK ;
2856	//delete [] out_BRANCH_EVENT_CONTEXT_ID ;
2857	delete [] out_BRANCH_EVENT_DEPTH ;
2858	//delete [] out_BRANCH_EVENT_MISS_PREDICTION;
2859	delete [] out_BRANCH_EVENT_ADDRESS_SRC ;
2860	delete [] out_BRANCH_EVENT_ADDRESS_DEST_VAL;
2861	delete [] out_BRANCH_EVENT_ADDRESS_DEST ;
2862
2863	// ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2864	delete [] out_UPDATE_VAL ;
2865	delete [] in_UPDATE_ACK ;
2866	delete [] out_UPDATE_CONTEXT_ID ;
2867	delete [] out_UPDATE_MISS_PREDICTION ;
2868	delete [] out_UPDATE_DIRECTION_GOOD ;
2869	delete [] out_UPDATE_BTB_VAL ;
2870	delete [] out_UPDATE_BTB_ADDRESS_SRC ;
2871	delete [] out_UPDATE_BTB_ADDRESS_DEST ;
2872	delete [] out_UPDATE_BTB_CONDITION ;
2873	delete [] out_UPDATE_DIR_VAL ;
2874	delete [] out_UPDATE_DIR_HISTORY ;
2875	delete [] out_UPDATE_RAS_VAL ;
2876	delete [] out_UPDATE_RAS_FLUSH ;
2877	delete [] out_UPDATE_RAS_PUSH ;
2878	delete [] out_UPDATE_RAS_ADDRESS ;
2879	delete [] out_UPDATE_RAS_INDEX ;
2880	delete [] out_UPDATE_RAS_PREDICTION_IFETCH;
2881
2882	DELETE1_SC_SIGNAL( in_EVENT_VAL ,_param->_nb_context);
2883	DELETE1_SC_SIGNAL(out_EVENT_ACK ,_param->_nb_context);
2884	DELETE1_SC_SIGNAL( in_EVENT_TYPE ,_param->_nb_context);
2885	DELETE1_SC_SIGNAL( in_EVENT_DEPTH ,_param->_nb_context);
2886
2887	// ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2888	delete [] out_DEPTH_VAL;
2889	delete [] out_DEPTH_CURRENT;
2890	delete [] out_DEPTH_MIN;
2891	delete [] out_DEPTH_MAX;
2892	delete [] out_DEPTH_FULL;
2893
2894	#endif
2895
2896	delete _Update_Prediction_Table;
2897	#ifdef STATISTICS
2898	delete _parameters_statistics;
2899	#endif
2900	}

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