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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp @ 98

Last change on this file since 98 was 98, checked in by rosiere, 16 years ago
1) Fix bug (read unit, RAT -> write in R0, SPR desallocation ...) 2) Change VHDL Execute_queue -> use Generic/Queue? 3) Complete document on VHDL generation 4) Add soc test
Property svn:keywords set to `Id`
File size: 107.1 KB

Line
1	/*
2	* $id: test.cpp 82 2008-05-01 16:48:45Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#define NB_ITERATION 16
10	#define CYCLE_MAX (1024*NB_ITERATION)
11
12	#include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/include/test.h"
13	#include "Common/include/Test.h"
14	#include "Behavioural/include/Allocation.h"
15
16	typedef struct
17	{
18	uint32_t ufpt_ptr ;
19	uint32_t upt_ptr ;
20
21	Tcontext_t context ;
22	Taddress_t address_src ;
23	Taddress_t address_dest;
24	Taddress_t address_good;
25	Tbranch_condition_t condition ;
26	Tcontrol_t take ;
27	Tcontrol_t take_good ;
28	Tcontrol_t flag ;
29	Tcontrol_t no_sequence ;
30	Tcontrol_t is_accurate ;
31	Thistory_t history ;
32	Taddress_t ras_address ;
33	Tptr_t ras_index ;
34	Tcontrol_t miss_ifetch ;
35	Tcontrol_t miss_decod ;
36	Tcontrol_t miss_commit ;
37	} request_t;
38
39	void test (string name,
40	morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::Parameters * _param)
41	{
42	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
43
44	#ifdef STATISTICS
45	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX);
46	#endif
47
48	Tusage_t _usage = USE_ALL;
49
50	// _usage = usage_unset(_usage,USE_SYSTEMC );
51	// _usage = usage_unset(_usage,USE_VHDL );
52	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
53	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
54	// _usage = usage_unset(_usage,USE_POSITION );
55	// _usage = usage_unset(_usage,USE_STATISTICS );
56	// _usage = usage_unset(_usage,USE_INFORMATION );
57
58	Update_Prediction_Table * _Update_Prediction_Table = new Update_Prediction_Table
59	(name.c_str(),
60	#ifdef STATISTICS
61	_parameters_statistics,
62	#endif
63	_param,
64	_usage);
65
66	#ifdef SYSTEMC
67	/*********************************************************************
68	* Déclarations des signaux
69	*********************************************************************/
70	string rename;
71
72	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
73	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
74
75	ALLOC1_SC_SIGNAL( in_PREDICT_VAL ," in_PREDICT_VAL ",Tcontrol_t ,_param->_nb_inst_predict);
76	ALLOC1_SC_SIGNAL(out_PREDICT_ACK ,"out_PREDICT_ACK ",Tcontrol_t ,_param->_nb_inst_predict);
77	ALLOC1_SC_SIGNAL( in_PREDICT_CONTEXT_ID ," in_PREDICT_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_predict);
78	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_ADDRESS_SRC ," in_PREDICT_BTB_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_predict);
79	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_ADDRESS_DEST ," in_PREDICT_BTB_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_predict);
80	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_CONDITION ," in_PREDICT_BTB_CONDITION ",Tbranch_condition_t,_param->_nb_inst_predict);
81	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_LAST_TAKE ," in_PREDICT_BTB_LAST_TAKE ",Tcontrol_t ,_param->_nb_inst_predict);
82	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_IS_ACCURATE ," in_PREDICT_BTB_IS_ACCURATE ",Tcontrol_t ,_param->_nb_inst_predict);
83	ALLOC1_SC_SIGNAL( in_PREDICT_DIR_HISTORY ," in_PREDICT_DIR_HISTORY ",Thistory_t ,_param->_nb_inst_predict);
84	ALLOC1_SC_SIGNAL( in_PREDICT_RAS_ADDRESS ," in_PREDICT_RAS_ADDRESS ",Taddress_t ,_param->_nb_inst_predict);
85	ALLOC1_SC_SIGNAL( in_PREDICT_RAS_INDEX ," in_PREDICT_RAS_INDEX ",Tptr_t ,_param->_nb_inst_predict);
86	ALLOC1_SC_SIGNAL(out_PREDICT_UPDATE_PREDICTION_ID ,"out_PREDICT_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_inst_predict);
87	ALLOC1_SC_SIGNAL( in_DECOD_VAL ," in_DECOD_VAL ",Tcontrol_t ,_param->_nb_inst_decod);
88	ALLOC1_SC_SIGNAL(out_DECOD_ACK ,"out_DECOD_ACK ",Tcontrol_t ,_param->_nb_inst_decod);
89	ALLOC1_SC_SIGNAL( in_DECOD_CONTEXT_ID ," in_DECOD_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_decod);
90	ALLOC1_SC_SIGNAL( in_DECOD_BTB_ADDRESS_SRC ," in_DECOD_BTB_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_decod);
91	ALLOC1_SC_SIGNAL( in_DECOD_BTB_ADDRESS_DEST ," in_DECOD_BTB_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_decod);
92	ALLOC1_SC_SIGNAL( in_DECOD_BTB_CONDITION ," in_DECOD_BTB_CONDITION ",Tbranch_condition_t,_param->_nb_inst_decod);
93	ALLOC1_SC_SIGNAL( in_DECOD_BTB_LAST_TAKE ," in_DECOD_BTB_LAST_TAKE ",Tcontrol_t ,_param->_nb_inst_decod);
94	ALLOC1_SC_SIGNAL( in_DECOD_RAS_ADDRESS ," in_DECOD_RAS_ADDRESS ",Taddress_t ,_param->_nb_inst_decod);
95	ALLOC1_SC_SIGNAL( in_DECOD_RAS_INDEX ," in_DECOD_RAS_INDEX ",Tptr_t ,_param->_nb_inst_decod);
96	ALLOC1_SC_SIGNAL( in_DECOD_MISS_IFETCH ," in_DECOD_MISS_IFETCH ",Tcontrol_t ,_param->_nb_inst_decod);
97	ALLOC1_SC_SIGNAL( in_DECOD_MISS_DECOD ," in_DECOD_MISS_DECOD ",Tcontrol_t ,_param->_nb_inst_decod);
98	ALLOC1_SC_SIGNAL( in_DECOD_UPDATE_PREDICTION_ID ," in_DECOD_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_inst_decod);
99	//ALLOC1_SC_SIGNAL(out_DECOD_DEPTH ,"out_DECOD_DEPTH ",Tdepth_t ,_param->_nb_inst_decod);
100	ALLOC1_SC_SIGNAL( in_DECOD_IS_ACCURATE ," in_DECOD_IS_ACCURATE ",Tcontrol_t ,_param->_nb_inst_decod);
101
102	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ," in_BRANCH_COMPLETE_VAL ",Tcontrol_t ,_param->_nb_inst_branch_complete);
103	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,"out_BRANCH_COMPLETE_ACK ",Tcontrol_t ,_param->_nb_inst_branch_complete);
104	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ," in_BRANCH_COMPLETE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_branch_complete);
105	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ," in_BRANCH_COMPLETE_DEPTH ",Tdepth_t ,_param->_nb_inst_branch_complete);
106	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ," in_BRANCH_COMPLETE_ADDRESS ",Taddress_t ,_param->_nb_inst_branch_complete);
107	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_NO_SEQUENCE ," in_BRANCH_COMPLETE_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_inst_branch_complete);
108	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION,"out_BRANCH_COMPLETE_MISS_PREDICTION",Tcontrol_t ,_param->_nb_inst_branch_complete);
109	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_TAKE ,"out_BRANCH_COMPLETE_TAKE ",Tcontrol_t ,_param->_nb_inst_branch_complete);
110	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_SRC ,"out_BRANCH_COMPLETE_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_branch_complete);
111	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_DEST ,"out_BRANCH_COMPLETE_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_branch_complete);
112
113	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_VAL ,"out_BRANCH_EVENT_VAL ",Tcontrol_t ,_param->_nb_context);
114	ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ACK ," in_BRANCH_EVENT_ACK ",Tcontrol_t ,_param->_nb_context);
115	// ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_CONTEXT_ID ,"out_BRANCH_EVENT_CONTEXT_ID ",Tcontext_t ,_param->_nb_context);
116	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_DEPTH ,"out_BRANCH_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context);
117	// ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_MISS_PREDICTION,"out_BRANCH_EVENT_MISS_PREDICTION",Tcontrol_t ,_param->_nb_context);
118	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC ,"out_BRANCH_EVENT_ADDRESS_SRC ",Taddress_t ,_param->_nb_context);
119	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST_VAL,"out_BRANCH_EVENT_ADDRESS_DEST_VAL",Tcontrol_t ,_param->_nb_context);
120	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,"out_BRANCH_EVENT_ADDRESS_DEST ",Taddress_t ,_param->_nb_context);
121
122	ALLOC1_SC_SIGNAL(out_UPDATE_VAL ,"out_UPDATE_VAL ",Tcontrol_t ,_param->_nb_inst_update);
123	ALLOC1_SC_SIGNAL( in_UPDATE_ACK ," in_UPDATE_ACK ",Tcontrol_t ,_param->_nb_inst_update);
124	ALLOC1_SC_SIGNAL(out_UPDATE_CONTEXT_ID ,"out_UPDATE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_update);
125	ALLOC1_SC_SIGNAL(out_UPDATE_MISS_PREDICTION ,"out_UPDATE_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_inst_update);
126	ALLOC1_SC_SIGNAL(out_UPDATE_DIRECTION_GOOD ,"out_UPDATE_DIRECTION_GOOD ",Tcontrol_t ,_param->_nb_inst_update);
127	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_VAL ,"out_UPDATE_BTB_VAL ",Tcontrol_t ,_param->_nb_inst_update);
128	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_ADDRESS_SRC ,"out_UPDATE_BTB_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_update);
129	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_ADDRESS_DEST ,"out_UPDATE_BTB_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_update);
130	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_CONDITION ,"out_UPDATE_BTB_CONDITION ",Tbranch_condition_t,_param->_nb_inst_update);
131	ALLOC1_SC_SIGNAL(out_UPDATE_DIR_VAL ,"out_UPDATE_DIR_VAL ",Tcontrol_t ,_param->_nb_inst_update);
132	ALLOC1_SC_SIGNAL(out_UPDATE_DIR_HISTORY ,"out_UPDATE_DIR_HISTORY ",Thistory_t ,_param->_nb_inst_update);
133	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_VAL ,"out_UPDATE_RAS_VAL ",Tcontrol_t ,_param->_nb_inst_update);
134	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_FLUSH ,"out_UPDATE_RAS_FLUSH ",Tcontrol_t ,_param->_nb_inst_update);
135	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_PUSH ,"out_UPDATE_RAS_PUSH ",Tcontrol_t ,_param->_nb_inst_update);
136	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_ADDRESS ,"out_UPDATE_RAS_ADDRESS ",Taddress_t ,_param->_nb_inst_update);
137	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_INDEX ,"out_UPDATE_RAS_INDEX ",Tptr_t ,_param->_nb_inst_update);
138	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_PREDICTION_IFETCH ,"out_UPDATE_RAS_PREDICTION_IFETCH ",Tcontrol_t ,_param->_nb_inst_update);
139
140	ALLOC1_SC_SIGNAL( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t ,_param->_nb_context);
141	ALLOC1_SC_SIGNAL(out_EVENT_ACK ,"out_EVENT_ACK ",Tcontrol_t ,_param->_nb_context);
142	ALLOC1_SC_SIGNAL( in_EVENT_TYPE ," in_EVENT_TYPE ",Tevent_type_t ,_param->_nb_context);
143	ALLOC1_SC_SIGNAL( in_EVENT_DEPTH ," in_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context);
144
145	ALLOC1_SC_SIGNAL(out_DEPTH_CURRENT ,"out_DEPTH_CURRENT ",Tdepth_t ,_param->_nb_context);
146	ALLOC1_SC_SIGNAL(out_DEPTH_MIN ,"out_DEPTH_MIN ",Tdepth_t ,_param->_nb_context);
147	ALLOC1_SC_SIGNAL(out_DEPTH_MAX ,"out_DEPTH_MAX ",Tdepth_t ,_param->_nb_context);
148
149	/********************************************************
150	* Instanciation
151	********************************************************/
152
153	msg(_("<%s> : Instanciation of _Update_Prediction_Table.\n"),name.c_str());
154
155	((_Update_Prediction_Table->in_CLOCK)) ((in_CLOCK));
156	((_Update_Prediction_Table->in_NRESET)) ((in_NRESET));
157
158	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_VAL ,_param->_nb_inst_predict);
159	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_PREDICT_ACK ,_param->_nb_inst_predict);
160	if (_param->_have_port_context_id)
161	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_CONTEXT_ID ,_param->_nb_inst_predict);
162	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_ADDRESS_SRC ,_param->_nb_inst_predict);
163	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_ADDRESS_DEST ,_param->_nb_inst_predict);
164	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_CONDITION ,_param->_nb_inst_predict);
165	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_LAST_TAKE ,_param->_nb_inst_predict);
166	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_IS_ACCURATE ,_param->_nb_inst_predict);
167	if (_param->_have_port_history)
168	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_DIR_HISTORY ,_param->_nb_inst_predict);
169	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_RAS_ADDRESS ,_param->_nb_inst_predict);
170	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_RAS_INDEX ,_param->_nb_inst_predict);
171	if (_param->_have_port_depth)
172	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_PREDICT_UPDATE_PREDICTION_ID ,_param->_nb_inst_predict);
173	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_VAL ,_param->_nb_inst_decod);
174	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DECOD_ACK ,_param->_nb_inst_decod);
175	if (_param->_have_port_context_id)
176	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_CONTEXT_ID ,_param->_nb_inst_decod);
177	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_ADDRESS_SRC ,_param->_nb_inst_decod);
178	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_ADDRESS_DEST ,_param->_nb_inst_decod);
179	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_CONDITION ,_param->_nb_inst_decod);
180	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_LAST_TAKE ,_param->_nb_inst_decod);
181	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_RAS_ADDRESS ,_param->_nb_inst_decod);
182	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_RAS_INDEX ,_param->_nb_inst_decod);
183	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_MISS_IFETCH ,_param->_nb_inst_decod);
184	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_MISS_DECOD ,_param->_nb_inst_decod);
185	if (_param->_have_port_depth)
186	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_UPDATE_PREDICTION_ID ,_param->_nb_inst_decod);
187	//if (_param->_have_port_depth)
188	//INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DECOD_DEPTH ,_param->_nb_inst_decod);
189	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_IS_ACCURATE ,_param->_nb_inst_decod);
190	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete);
191	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete);
192	if (_param->_have_port_context_id)
193	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete);
194	if (_param->_have_port_depth)
195	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete);
196	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete);
197	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete);
198	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete);
199	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete);
200	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete);
201	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete);
202
203	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_VAL ,_param->_nb_context);
204	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_EVENT_ACK ,_param->_nb_context);
205	//if (_param->_have_port_context_id)
206	//INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context);
207	if (_param->_have_port_depth)
208	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_DEPTH ,_param->_nb_context);
209	//INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_MISS_PREDICTION,_param->_nb_context);
210	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context);
211	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_DEST_VAL,_param->_nb_context);
212	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context);
213
214	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_VAL ,_param->_nb_inst_update);
215	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_UPDATE_ACK ,_param->_nb_inst_update);
216	if (_param->_have_port_context_id)
217	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_CONTEXT_ID ,_param->_nb_inst_update);
218	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_MISS_PREDICTION ,_param->_nb_inst_update);
219	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_DIRECTION_GOOD ,_param->_nb_inst_update);
220	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_VAL ,_param->_nb_inst_update);
221	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_ADDRESS_SRC ,_param->_nb_inst_update);
222	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_ADDRESS_DEST ,_param->_nb_inst_update);
223	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_CONDITION ,_param->_nb_inst_update);
224	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_DIR_VAL ,_param->_nb_inst_update);
225	if (_param->_have_port_history)
226	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_DIR_HISTORY ,_param->_nb_inst_update);
227	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_VAL ,_param->_nb_inst_update);
228	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_FLUSH ,_param->_nb_inst_update);
229	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_PUSH ,_param->_nb_inst_update);
230	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_ADDRESS ,_param->_nb_inst_update);
231	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_INDEX ,_param->_nb_inst_update);
232	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_PREDICTION_IFETCH ,_param->_nb_inst_update);
233	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_VAL ,_param->_nb_context);
234	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_EVENT_ACK ,_param->_nb_context);
235	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_TYPE ,_param->_nb_context);
236	if (_param->_have_port_depth)
237	{
238	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_DEPTH ,_param->_nb_context);
239	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_CURRENT ,_param->_nb_context);
240	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_MIN ,_param->_nb_context);
241	}
242	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_MAX ,_param->_nb_context);
243
244	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
245
246	Time * _time = new Time();
247
248	/********************************************************
249	* Simulation - Begin
250	********************************************************/
251
252	// Initialisation
253
254	const uint32_t seed = 0;
255	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
256
257	srand(seed);
258
259	const int32_t percent_transaction_predict = 75;
260	const int32_t percent_transaction_decod = 75;
261	const int32_t percent_transaction_branch_complete = 75;
262	const int32_t percent_transaction_update = 75;
263	const int32_t percent_transaction_branch_event = 75;
264
265	const bool test1 = true;
266	const bool test2 = true;
267	const bool test3 = true;
268	const bool test4 = true;
269
270	std::list<request_t> ufpt;
271	std::list<request_t> upt;
272	request_t event;
273
274	SC_START(0);
275	LABEL("Initialisation");
276
277	LABEL("Reset");
278	in_NRESET->write(0);
279	SC_START(5);
280	in_NRESET->write(1);
281
282	Tdepth_t ufpt_bottom [_param->_nb_context];
283	Tdepth_t ufpt_top [_param->_nb_context];
284
285	Tdepth_t upt_bottom [_param->_nb_context];
286	Tdepth_t upt_top [_param->_nb_context];
287	Tdepth_t upt_top_event[_param->_nb_context];
288
289	for (uint32_t i=0; i<_param->_nb_context; ++i)
290	{
291	ufpt_bottom [i] = 0;
292	ufpt_top [i] = 0;
293	upt_bottom [i] = 0;
294	upt_top [i] = 0;
295	upt_top_event[i] = 0;
296	}
297
298	for (uint32_t i=0; i<_param->_nb_context; ++i)
299	{
300	TEST(Tdepth_t,out_DEPTH_CURRENT [i]->read(),upt_top [i]);
301	TEST(Tdepth_t,out_DEPTH_MIN [i]->read(),upt_bottom [i]);
302	TEST(Tdepth_t,out_DEPTH_MAX [i]->read(),upt_top [i]);
303	}
304
305	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
306	{
307	LABEL("Iteration %d",iteration);
308
309	for (uint32_t i=0; i<_param->_nb_inst_predict; ++i)
310	in_PREDICT_VAL [i]->write(0);
311	for (uint32_t i=0; i<_param->_nb_inst_decod; ++i)
312	in_DECOD_VAL [i]->write(0);
313	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i)
314	in_BRANCH_COMPLETE_VAL [i]->write(0);
315	for (uint32_t i=0; i<_param->_nb_context; ++i)
316	in_BRANCH_EVENT_ACK [i]->write(0);
317	for (uint32_t i=0; i<_param->_nb_inst_update; ++i)
318	in_UPDATE_ACK [i]->write(0);
319	for (uint32_t i=0; i<_param->_nb_context; ++i)
320	in_EVENT_VAL [i]->write(0);
321
322	//---------------------------------------------------------------------
323	//---------------------------------------------------------------------
324	// COMMON CASE
325	//---------------------------------------------------------------------
326	//---------------------------------------------------------------------
327	if (test1)
328	{
329	uint32_t context = rand() % _param->_nb_context;
330
331	{
332	LABEL("PREDICT - fill the queue");
333	uint32_t port = rand() % _param->_nb_inst_predict;
334
335	LABEL(" * context : %d",context);
336	LABEL(" * port : %d",port);
337
338	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
339	{
340	request_t request;
341	request.context = context;
342	request.address_src = 0xdeadbeef+i;
343	request.address_dest = 0x21071981+i;
344	request.address_good = request.address_dest;
345	request.condition = BRANCH_CONDITION_FLAG_SET;
346	request.take = 1;
347	request.take_good = 1;
348	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
349	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
350	request.is_accurate = true;
351	request.miss_ifetch = false;
352	request.miss_decod = false;
353	request.miss_commit = false;
354	request.history = i;
355	request.ras_address = 0xdeaddead+i;
356	request.ras_index = (0x12345678+i)%_param->_size_ras_index[context];
357	request.ufpt_ptr = ufpt_top [context];
358	// request.upt_ptr;
359
360	bool have_transaction = false;
361	do
362	{
363	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
364	in_PREDICT_CONTEXT_ID [port]->write(request.context );
365	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
366	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
367	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
368	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
369	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
370	in_PREDICT_DIR_HISTORY [port]->write(request.history );
371	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
372	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
373
374	if (_param->_have_port_depth)
375	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
376	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
377
378	SC_START(0); // fct melay
379
380	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
381	port,
382	in_PREDICT_VAL [port]->read(),
383	out_PREDICT_ACK [port]->read(),
384	in_PREDICT_BTB_IS_ACCURATE [port]->read());
385
386	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
387	{
388	LABEL("PREDICT [%d] - Transaction accepted",port);
389	have_transaction = true;
390
391	if (_param->_have_port_depth)
392	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
393
394	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
395	}
396
397	SC_START(1); // transition
398
399	} while (not have_transaction);
400
401	ufpt.push_back(request);
402
403	in_PREDICT_VAL [port]->write(0);
404
405	if (_param->_have_port_depth)
406	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
407	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
408	}
409	}
410
411	{
412	LABEL("DECOD");
413	uint32_t port = rand() % _param->_nb_inst_decod;
414
415	LABEL(" * context : %d",context);
416	LABEL(" * port : %d",port);
417
418	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
419	{
420	request_t request = ufpt.front();
421
422	bool have_transaction = false;
423	do
424	{
425	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
426	in_DECOD_CONTEXT_ID [port]->write(request.context );
427	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
428	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
429	in_DECOD_BTB_CONDITION [port]->write(request.condition );
430	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
431	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
432	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
433	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
434	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
435	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
436	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
437
438	SC_START(0); // fct melay
439
440	LABEL("DECOD [%d] %d - %d",
441	port,
442	in_PREDICT_VAL [port]->read(),
443	out_PREDICT_ACK [port]->read());
444
445	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
446	{
447	LABEL("DECOD [%d] - Transaction accepted",port);
448	have_transaction = true;
449
450	request.upt_ptr = upt_top [context];
451	upt.push_back(request);
452	ufpt.pop_front();
453
454	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
455	}
456
457	SC_START(1); // transition
458
459	} while (not have_transaction);
460
461	in_DECOD_VAL [port]->write(0);
462
463	if (_param->_have_port_depth)
464	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
465	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
466	}
467	}
468
469	{
470	LABEL("BRANCH_COMPLETE - hit ifetch");
471
472	uint32_t port = rand() % _param->_nb_inst_branch_complete;
473
474	LABEL(" * port : %d",port);
475
476	std::list<request_t>::iterator it_upt = upt.begin();
477
478	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
479	for (uint32_t i=0; i<upt.size(); i++)
480	{
481	bool have_transaction = false;
482
483	do
484	{
485	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
486	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
487	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
488	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_good);
489	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence );
490
491	if (_param->_have_port_depth)
492	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
493	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
494
495	SC_START(0);
496
497	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
498
499	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
500	{
501	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
502	have_transaction = true;
503
504	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
505	TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take_good );
506	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
507	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_good);
508
509	it_upt ++;
510	}
511
512	SC_START(1);
513	} while (not have_transaction);
514
515	in_BRANCH_COMPLETE_VAL [port]->write(0);
516
517	if (_param->_have_port_depth)
518	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
519	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
520	}
521	}
522
523	{
524	LABEL("UPDATE - hit ifetch");
525
526	uint32_t port = 0;
527
528	LABEL(" * port : %d",port);
529	std::list<request_t>::iterator it_upt = upt.begin();
530
531	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
532	for (uint32_t i=0; i<upt.size(); i++)
533	{
534	bool have_transaction = false;
535
536	do
537	{
538	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
539
540	// if (_param->_have_port_depth)
541	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
542	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
543
544	SC_START(0);
545
546	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
547
548	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
549	{
550	LABEL("UPDATE [%d] - Transaction accepted",port);
551	have_transaction = true;
552
553	if (_param->_have_port_context_id)
554	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
555	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
556	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
557	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
558	if (update_btb(it_upt->condition))
559	{
560	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
561	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
562	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
563	}
564	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
565	if (update_dir(it_upt->condition))
566	if (_param->_have_port_history)
567	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
568	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
569	if (update_ras(it_upt->condition))
570	{
571	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
572	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
573	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
574	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
575	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
576	}
577	++ it_upt;
578	}
579
580	SC_START(1);
581	} while (not have_transaction);
582
583	in_UPDATE_ACK [port]->write(0);
584	// if (_param->_have_port_depth)
585	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
586	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
587	}
588	upt.clear();
589	}
590
591	// Wait Garbage Collector
592	{
593	upt_bottom [context] = (upt_bottom [context]+_param->_size_ufpt_queue[context])%_param->_size_upt_queue[context];
594	// upt_top [context] = (upt_top [context]);
595
596	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
597	(upt_top [context] != out_DEPTH_MAX [context]->read()))
598	SC_START(1);
599
600	}
601	}
602
603	//---------------------------------------------------------------------
604	//---------------------------------------------------------------------
605	// DECOD MISS : no RAS in ifetch
606	//---------------------------------------------------------------------
607	//---------------------------------------------------------------------
608	if (test2)
609	{
610	uint32_t context = rand() % _param->_nb_context;
611
612	{
613	LABEL("PREDICT - fill the queue");
614	uint32_t port = rand() % _param->_nb_inst_predict;
615
616	LABEL(" * context : %d",context);
617	LABEL(" * port : %d",port);
618
619	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
620	{
621	request_t request;
622	request.context = context;
623	request.address_src = 0xdeadbeef+i;
624	request.address_dest = 0x21071981+i;
625	request.address_good = request.address_dest;
626	request.condition = BRANCH_CONDITION_FLAG_SET;
627	request.take = 1;
628	request.take_good = 1;
629	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
630	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
631	request.is_accurate = true;
632	request.miss_ifetch = false;
633	request.miss_decod = false;
634	request.miss_commit = false;
635	request.history = i;
636	request.ras_address = 0xdeaddead+i;
637	request.ras_index = (0x12345678+i)%_param->_size_ras_index[context];
638	request.ufpt_ptr = ufpt_top [context];
639	// request.upt_ptr;
640
641	bool have_transaction = false;
642	do
643	{
644	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
645	in_PREDICT_CONTEXT_ID [port]->write(request.context );
646	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
647	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
648	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
649	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
650	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
651	in_PREDICT_DIR_HISTORY [port]->write(request.history );
652	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
653	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
654
655	if (_param->_have_port_depth)
656	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
657	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
658
659	SC_START(0); // fct melay
660
661	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
662	port,
663	in_PREDICT_VAL [port]->read(),
664	out_PREDICT_ACK [port]->read(),
665	in_PREDICT_BTB_IS_ACCURATE [port]->read());
666
667	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
668	{
669	LABEL("PREDICT [%d] - Transaction accepted",port);
670	have_transaction = true;
671
672	if (_param->_have_port_depth)
673	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
674
675	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
676	}
677
678	SC_START(1); // transition
679
680	} while (not have_transaction);
681
682	// ufpt.push_back(request);
683
684	in_PREDICT_VAL [port]->write(0);
685
686	if (_param->_have_port_depth)
687	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
688	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
689	}
690	}
691
692	{
693	LABEL("DECOD - Miss");
694	uint32_t port = rand() % _param->_nb_inst_decod;
695
696	LABEL(" * context : %d",context);
697	LABEL(" * port : %d",port);
698
699	request_t request;
700	request.context = context;
701	request.address_src = 0x14011959;
702	request.address_dest = 0x25071959; // after = not take
703	request.address_good = request.address_dest;
704	request.condition = BRANCH_CONDITION_FLAG_SET;
705	request.take = 0;
706	request.take_good = 0;
707	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
708	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
709	request.is_accurate = true;
710	request.miss_ifetch = false;
711	request.miss_decod = true ;
712	request.miss_commit = false;
713	request.history = 1;
714	request.ras_address = 0xbabababa;
715	request.ras_index = (0x87654321)%_param->_size_ras_index[context];
716	request.ufpt_ptr = ufpt_top [context];
717	request.upt_ptr = upt_top [context];
718
719	event = request;
720
721	// for (uint32_t i=0; i<upt.size(); i++)
722	// just one
723	{
724	bool have_transaction = false;
725	do
726	{
727	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
728	in_DECOD_CONTEXT_ID [port]->write(request.context );
729	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
730	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
731	in_DECOD_BTB_CONDITION [port]->write(request.condition );
732	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
733	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
734	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
735	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
736	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
737	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
738	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
739
740	SC_START(0); // fct melay
741
742	LABEL("DECOD [%d] %d - %d",
743	port,
744	in_PREDICT_VAL [port]->read(),
745	out_PREDICT_ACK [port]->read());
746
747	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
748	{
749	LABEL("DECOD [%d] - Transaction accepted",port);
750	have_transaction = true;
751
752	request.upt_ptr = upt_top [context];
753	upt.push_back(request);
754	// ufpt.pop_front();
755
756	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
757	}
758
759	SC_START(1); // transition
760
761	} while (not have_transaction);
762
763	in_DECOD_VAL [port]->write(0);
764
765	if (_param->_have_port_depth)
766	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
767	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
768	}
769	}
770
771	{
772	LABEL("BRANCH_COMPLETE - hit ifetch");
773
774	uint32_t port = rand() % _param->_nb_inst_branch_complete;
775
776	LABEL(" * port : %d",port);
777
778	std::list<request_t>::iterator it_upt = upt.begin();
779
780	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
781	// for (uint32_t i=0; i<upt.size(); i++)
782	// just one
783	{
784	bool have_transaction = false;
785
786	do
787	{
788	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
789	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
790	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
791	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_good);
792	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence );
793
794	if (_param->_have_port_depth)
795	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
796	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
797
798	SC_START(0);
799
800	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
801
802	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
803	{
804	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
805	have_transaction = true;
806
807	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
808	TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take_good );
809	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
810	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_good);
811
812	it_upt ++;
813	}
814
815	SC_START(1);
816	} while (not have_transaction);
817
818	in_BRANCH_COMPLETE_VAL [port]->write(0);
819
820	if (_param->_have_port_depth)
821	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
822	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
823	}
824	}
825
826	{
827	LABEL("UPDATE - hit ifetch");
828
829	uint32_t port = 0;
830
831	LABEL(" * port : %d",port);
832	std::list<request_t>::iterator it_upt = upt.begin();
833
834	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
835	// for (uint32_t i=0; i<upt.size(); i++)
836	// just one
837	{
838	bool have_transaction = false;
839
840	do
841	{
842	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
843
844	// if (_param->_have_port_depth)
845	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
846	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
847
848	SC_START(0);
849
850	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
851
852	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
853	{
854	LABEL("UPDATE [%d] - Transaction accepted",port);
855	have_transaction = true;
856
857	if (_param->_have_port_context_id)
858	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
859	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
860	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
861	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
862	if (update_btb(it_upt->condition))
863	{
864	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
865	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
866	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
867	}
868	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
869
870	if (update_dir(it_upt->condition))
871	if (_param->_have_port_history)
872	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
873	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
874	if (update_ras(it_upt->condition))
875	{
876	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
877	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
878	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
879	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
880	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
881	}
882	++ it_upt;
883	}
884
885	SC_START(1);
886	} while (not have_transaction);
887
888	in_UPDATE_ACK [port]->write(0);
889	// if (_param->_have_port_depth)
890	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
891	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
892	}
893	upt.clear();
894	}
895
896	{
897	LABEL("BRANCH_EVENT - have miss decod");
898
899	uint32_t port = context;
900
901	{
902	bool have_transaction = false;
903
904	do
905	{
906	in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event);
907
908	SC_START(0);
909
910	LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read());
911
912	if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read())
913	{
914	LABEL("BRANCH_EVENT [%d] - Transaction accepted",port);
915	have_transaction = true;
916
917	TEST(Tdepth_t ,out_BRANCH_EVENT_DEPTH [port]->read(),event.upt_ptr);
918	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src);
919	TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take);
920	if (event.take)
921	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good);
922
923	event.address_src = 0;
924	event.take = 0;
925	event.address_dest = 0;
926	}
927
928	SC_START(1);
929	} while (not have_transaction);
930
931	in_BRANCH_EVENT_ACK [port]->write(0);
932	}
933	}
934
935	{
936	LABEL("EVENT_STATE");
937
938	SC_START(1);
939	in_EVENT_VAL [context]->write(1);
940	in_EVENT_TYPE [context]->write(EVENT_TYPE_MISS_SPECULATION);
941
942	SC_START(1);
943	in_EVENT_VAL [context]->write(0);
944	in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE );
945	}
946
947	// Wait Garbage Collector
948	{
949	upt_bottom [context] = (upt_bottom [context]+1)%_param->_size_upt_queue[context];
950	// upt_top [context] = (upt_top [context]);
951
952	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
953	(upt_top [context] != out_DEPTH_MAX [context]->read()))
954	SC_START(1);
955
956	}
957	}
958
959	//---------------------------------------------------------------------
960	//---------------------------------------------------------------------
961	// DECOD MISS : with RAS in ifetch
962	//---------------------------------------------------------------------
963	//---------------------------------------------------------------------
964	if (test3)
965	{
966	uint32_t context = rand() % _param->_nb_context;
967	uint32_t have_ras = false;
968	{
969	LABEL("PREDICT - fill the queue");
970	uint32_t port = rand() % _param->_nb_inst_predict;
971
972	LABEL(" * context : %d",context);
973	LABEL(" * port : %d",port);
974
975	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
976	{
977	request_t request;
978	request.context = context;
979	request.address_src = 0xdeadbeef+i;
980	request.address_dest = 0x21071981+i;
981	request.address_good = request.address_dest;
982	request.condition = (rand()%2)?BRANCH_CONDITION_NONE_WITH_WRITE_STACK:BRANCH_CONDITION_FLAG_SET;
983
984	have_ras \|= (update_ras(request.condition));
985
986	request.take = 1;
987	request.take_good = 1;
988	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
989	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
990	request.is_accurate = true;
991	request.miss_ifetch = false;
992	request.miss_decod = true ;
993	request.miss_commit = false;
994	request.history = i;
995	request.ras_address = 0x12344321+i;
996	request.ras_index = (043211234+i)%_param->_size_ras_index[context];
997	request.ufpt_ptr = ufpt_top [context];
998	// request.upt_ptr;
999
1000	bool have_transaction = false;
1001	do
1002	{
1003	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
1004	in_PREDICT_CONTEXT_ID [port]->write(request.context );
1005	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
1006	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1007	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
1008	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
1009	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
1010	in_PREDICT_DIR_HISTORY [port]->write(request.history );
1011	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
1012	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
1013
1014	if (_param->_have_port_depth)
1015	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1016	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1017
1018	SC_START(0); // fct melay
1019
1020	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
1021	port,
1022	in_PREDICT_VAL [port]->read(),
1023	out_PREDICT_ACK [port]->read(),
1024	in_PREDICT_BTB_IS_ACCURATE [port]->read());
1025
1026	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
1027	{
1028	LABEL("PREDICT [%d] - Transaction accepted",port);
1029	have_transaction = true;
1030
1031	if (_param->_have_port_depth)
1032	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
1033
1034	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
1035	}
1036
1037	SC_START(1); // transition
1038
1039	} while (not have_transaction);
1040
1041	ufpt.push_back(request); // to update
1042
1043	in_PREDICT_VAL [port]->write(0);
1044
1045	if (_param->_have_port_depth)
1046	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1047	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1048	}
1049	}
1050
1051	{
1052	LABEL("DECOD - Miss");
1053	uint32_t port = rand() % _param->_nb_inst_decod;
1054
1055	LABEL(" * context : %d",context);
1056	LABEL(" * port : %d",port);
1057
1058	request_t request;
1059	request.context = context;
1060	request.address_src = 0x14011959;
1061	request.address_dest = 0x25071959; // after = not take
1062	request.address_good = request.address_dest;
1063	request.condition = BRANCH_CONDITION_FLAG_SET;
1064	request.take = 0;
1065	request.take_good = 0;
1066	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
1067	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
1068	request.is_accurate = true;
1069	request.miss_ifetch = false;
1070	request.miss_decod = true ;
1071	request.miss_commit = false;
1072	request.history = 1;
1073	request.ras_address = 0xbabababa;
1074	request.ras_index = (0x87654321)%_param->_size_ras_index[context];
1075	request.ufpt_ptr = ufpt_top [context];
1076	request.upt_ptr = upt_top [context];
1077
1078	event = request;
1079
1080	// for (uint32_t i=0; i<upt.size(); i++)
1081	// just one
1082	{
1083	bool have_transaction = false;
1084	do
1085	{
1086	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
1087	in_DECOD_CONTEXT_ID [port]->write(request.context );
1088	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
1089	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1090	in_DECOD_BTB_CONDITION [port]->write(request.condition );
1091	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
1092	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
1093	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
1094	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
1095	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
1096	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
1097	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
1098
1099	SC_START(0); // fct melay
1100
1101	LABEL("DECOD [%d] %d - %d",
1102	port,
1103	in_PREDICT_VAL [port]->read(),
1104	out_PREDICT_ACK [port]->read());
1105
1106	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
1107	{
1108	LABEL("DECOD [%d] - Transaction accepted",port);
1109	have_transaction = true;
1110
1111	request.upt_ptr = upt_top [context];
1112	upt.push_back(request);
1113	// ufpt.pop_front();
1114
1115	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
1116	}
1117
1118	SC_START(1); // transition
1119
1120	} while (not have_transaction);
1121
1122	in_DECOD_VAL [port]->write(0);
1123
1124	if (_param->_have_port_depth)
1125	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1126	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1127	}
1128	}
1129
1130	{
1131	LABEL("BRANCH_COMPLETE - hit ifetch");
1132
1133	uint32_t port = rand() % _param->_nb_inst_branch_complete;
1134
1135	LABEL(" * port : %d",port);
1136
1137	std::list<request_t>::iterator it_upt = upt.begin();
1138
1139	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1140	// for (uint32_t i=0; i<upt.size(); i++)
1141	// just one
1142	{
1143	bool have_transaction = false;
1144
1145	do
1146	{
1147	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
1148	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
1149	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
1150	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_good);
1151	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence );
1152
1153	if (_param->_have_port_depth)
1154	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1155	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1156
1157	SC_START(0);
1158
1159	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
1160
1161	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
1162	{
1163	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
1164	have_transaction = true;
1165
1166	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
1167	TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take_good );
1168	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
1169	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_good);
1170
1171	it_upt ++;
1172	}
1173
1174	SC_START(1);
1175	} while (not have_transaction);
1176
1177	in_BRANCH_COMPLETE_VAL [port]->write(0);
1178
1179	if (_param->_have_port_depth)
1180	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1181	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1182	}
1183	}
1184
1185	if (have_ras)
1186	{
1187	LABEL("UPDATE - Update UPFT");
1188
1189	uint32_t port = 0;
1190
1191	LABEL(" * port : %d",port);
1192	std::list<request_t>::iterator it_ufpt = ufpt.end();
1193	-- it_ufpt;
1194
1195	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1196	{
1197	bool have_transaction = false;
1198
1199	do
1200	{
1201	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
1202
1203	// if (_param->_have_port_depth)
1204	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
1205	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
1206
1207	SC_START(0);
1208
1209	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
1210
1211	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
1212	{
1213	LABEL("UPDATE [%d] - Transaction accepted",port);
1214	have_transaction = true;
1215
1216	if (_param->_have_port_context_id)
1217	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_ufpt->context);
1218	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),(it_ufpt->miss_ifetch or
1219	it_ufpt->miss_decod or
1220	it_ufpt->miss_commit ));
1221	// if (update_btb(it_ufpt->condition) or
1222	// update_dir(it_ufpt->condition))
1223	// TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_ufpt->take_good);
1224	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),0);
1225	// if (update_btb(it_ufpt->condition))
1226	// {
1227	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_ufpt->address_src);
1228	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_ufpt->address_dest);
1229	// TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_ufpt->condition);
1230	// }
1231	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),0);
1232
1233	// if (update_dir(it_ufpt->condition))
1234	// if (_param->_have_port_history)
1235	// TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_ufpt->history);
1236	// TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_ufpt->condition));
1237	if (update_ras(it_ufpt->condition))
1238	{
1239	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
1240	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_ufpt->condition));
1241	LABEL("KANE : out_UPDATE_RAS_ADDRESS [port]->read() : %.8x",out_UPDATE_RAS_ADDRESS [port]->read());
1242	LABEL("KANE : it_ufpt->ras_address : %.8x",it_ufpt->ras_address);
1243
1244	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_ufpt->ras_address);
1245	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_ufpt->ras_index);
1246	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch);
1247	}
1248	}
1249
1250	SC_START(1);
1251	} while (not have_transaction);
1252
1253	-- it_ufpt;
1254
1255
1256	in_UPDATE_ACK [port]->write(0);
1257	// if (_param->_have_port_depth)
1258	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
1259	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
1260	}
1261	}
1262	ufpt.clear();
1263
1264	{
1265	LABEL("UPDATE - hit ifetch");
1266
1267	uint32_t port = 0;
1268
1269	LABEL(" * port : %d",port);
1270	std::list<request_t>::iterator it_upt = upt.begin();
1271
1272	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1273	// for (uint32_t i=0; i<upt.size(); i++)
1274	// just one
1275	{
1276	bool have_transaction = false;
1277
1278	do
1279	{
1280	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
1281
1282	// if (_param->_have_port_depth)
1283	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1284	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1285
1286	SC_START(0);
1287
1288	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
1289
1290	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
1291	{
1292	LABEL("UPDATE [%d] - Transaction accepted",port);
1293	have_transaction = true;
1294
1295	if (_param->_have_port_context_id)
1296	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
1297	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
1298	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
1299	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
1300	if (update_btb(it_upt->condition))
1301	{
1302	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
1303	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
1304	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
1305	}
1306	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
1307
1308	if (update_dir(it_upt->condition))
1309	if (_param->_have_port_history)
1310	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
1311	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
1312	if (update_ras(it_upt->condition))
1313	{
1314	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
1315	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
1316	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
1317	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
1318	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
1319	}
1320	++ it_upt;
1321	}
1322
1323	SC_START(1);
1324	} while (not have_transaction);
1325
1326	in_UPDATE_ACK [port]->write(0);
1327	// if (_param->_have_port_depth)
1328	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1329	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1330	}
1331	}
1332	upt.clear();
1333
1334	{
1335	LABEL("BRANCH_EVENT - have miss decod");
1336
1337	uint32_t port = context;
1338
1339	{
1340	bool have_transaction = false;
1341
1342	do
1343	{
1344	in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event);
1345
1346	SC_START(0);
1347
1348	LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read());
1349
1350	if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read())
1351	{
1352	LABEL("BRANCH_EVENT [%d] - Transaction accepted",port);
1353	have_transaction = true;
1354
1355	TEST(Tdepth_t ,out_BRANCH_EVENT_DEPTH [port]->read(),event.upt_ptr);
1356	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src);
1357	TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take);
1358	if (event.take)
1359	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good);
1360
1361	event.address_src = 0;
1362	event.take = 0;
1363	event.address_dest = 0;
1364	}
1365
1366	SC_START(1);
1367	} while (not have_transaction);
1368
1369	in_BRANCH_EVENT_ACK [port]->write(0);
1370	}
1371	}
1372
1373	{
1374	LABEL("EVENT_STATE");
1375
1376	SC_START(1);
1377	in_EVENT_VAL [context]->write(1);
1378	in_EVENT_TYPE [context]->write(EVENT_TYPE_MISS_SPECULATION);
1379
1380	SC_START(1);
1381	in_EVENT_VAL [context]->write(0);
1382	in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE );
1383	}
1384
1385	// Wait Garbage Collector
1386	{
1387	upt_bottom [context] = (upt_bottom [context]+1)%_param->_size_upt_queue[context];
1388	// upt_top [context] = (upt_top [context]);
1389
1390	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
1391	(upt_top [context] != out_DEPTH_MAX [context]->read()))
1392	SC_START(1);
1393
1394	}
1395	}
1396
1397	//---------------------------------------------------------------------
1398	//---------------------------------------------------------------------
1399	// COMMIT MISS : with RAS in UPFT and UPT
1400	//---------------------------------------------------------------------
1401	//---------------------------------------------------------------------
1402	if (test4)
1403	{
1404	uint32_t context = rand() % _param->_nb_context;
1405	uint32_t have_ufpt_ras = false;
1406	uint32_t have_upt_ras = false;
1407	{
1408	LABEL("PREDICT - fill the queue");
1409	uint32_t port = rand() % _param->_nb_inst_predict;
1410
1411	LABEL(" * context : %d",context);
1412	LABEL(" * port : %d",port);
1413
1414	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1415	{
1416	request_t request;
1417	request.context = context;
1418	request.address_src = rand();
1419	request.address_dest = rand();
1420
1421	request.condition = (rand()%2)?BRANCH_CONDITION_READ_STACK:BRANCH_CONDITION_FLAG_SET;
1422
1423	request.take = 1;
1424	request.take_good = 1;
1425	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
1426	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
1427	request.is_accurate = true ;
1428	request.miss_ifetch = false;
1429	request.miss_decod = false;
1430	request.miss_commit = false;
1431	request.history = i;
1432	request.ras_address = rand();
1433	request.ras_index = rand()%_param->_size_ras_index[context];
1434	request.ufpt_ptr = ufpt_top [context];
1435	// request.upt_ptr;
1436
1437	bool have_transaction = false;
1438	do
1439	{
1440	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
1441	in_PREDICT_CONTEXT_ID [port]->write(request.context );
1442	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
1443	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1444	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
1445	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
1446	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
1447	in_PREDICT_DIR_HISTORY [port]->write(request.history );
1448	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
1449	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
1450
1451	if (_param->_have_port_depth)
1452	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1453	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1454
1455	SC_START(0); // fct melay
1456
1457	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
1458	port,
1459	in_PREDICT_VAL [port]->read(),
1460	out_PREDICT_ACK [port]->read(),
1461	in_PREDICT_BTB_IS_ACCURATE [port]->read());
1462
1463	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
1464	{
1465	LABEL("PREDICT [%d] - Transaction accepted",port);
1466	have_transaction = true;
1467
1468	if (_param->_have_port_depth)
1469	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
1470
1471	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
1472	}
1473
1474	SC_START(1); // transition
1475
1476	} while (not have_transaction);
1477
1478	ufpt.push_back(request); // to update
1479
1480	in_PREDICT_VAL [port]->write(0);
1481
1482	if (_param->_have_port_depth)
1483	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1484	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1485	}
1486	}
1487
1488	{
1489	LABEL("DECOD");
1490	uint32_t port = rand() % _param->_nb_inst_decod;
1491
1492	LABEL(" * context : %d",context);
1493	LABEL(" * port : %d",port);
1494
1495	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1496	{
1497	request_t request = ufpt.front();
1498
1499	bool have_transaction = false;
1500	do
1501	{
1502	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
1503	in_DECOD_CONTEXT_ID [port]->write(request.context );
1504	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
1505	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1506	in_DECOD_BTB_CONDITION [port]->write(request.condition );
1507	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
1508	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
1509	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
1510	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
1511	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
1512	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
1513	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
1514
1515	have_upt_ras \|= (update_ras(request.condition));
1516
1517	SC_START(0); // fct melay
1518
1519	LABEL("DECOD [%d] %d - %d",
1520	port,
1521	in_DECOD_VAL [port]->read(),
1522	out_DECOD_ACK [port]->read());
1523
1524	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
1525	{
1526	LABEL("DECOD [%d] - Transaction accepted",port);
1527	have_transaction = true;
1528
1529	request.upt_ptr = upt_top [context];
1530	upt.push_back(request);
1531	ufpt.pop_front();
1532
1533	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
1534	}
1535
1536	SC_START(1); // transition
1537
1538	} while (not have_transaction);
1539
1540	in_DECOD_VAL [port]->write(0);
1541
1542	if (_param->_have_port_depth)
1543	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1544	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1545	}
1546	}
1547
1548	{
1549	LABEL("PREDICT - fill the queue");
1550	uint32_t port = rand() % _param->_nb_inst_predict;
1551
1552	LABEL(" * context : %d",context);
1553	LABEL(" * port : %d",port);
1554
1555	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1556	{
1557	request_t request;
1558	request.context = context;
1559	request.address_src = rand();
1560	request.address_dest = rand();
1561	request.address_good = request.address_dest;
1562	request.condition = (rand()%2)?BRANCH_CONDITION_NONE_WITH_WRITE_STACK:BRANCH_CONDITION_FLAG_SET;
1563
1564	have_ufpt_ras \|= (update_ras(request.condition));
1565
1566	request.take = 1;
1567	request.take_good = 1;
1568	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
1569	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
1570	request.is_accurate = true ;
1571	request.miss_ifetch = false;
1572	request.miss_decod = false;
1573	request.miss_commit = true;
1574	request.history = i;
1575	request.ras_address = rand();
1576	request.ras_index = rand()%_param->_size_ras_index[context];
1577	request.ufpt_ptr = ufpt_top [context];
1578	// request.upt_ptr;
1579
1580	bool have_transaction = false;
1581	do
1582	{
1583	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
1584	in_PREDICT_CONTEXT_ID [port]->write(request.context );
1585	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
1586	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1587	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
1588	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
1589	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
1590	in_PREDICT_DIR_HISTORY [port]->write(request.history );
1591	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
1592	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
1593
1594	if (_param->_have_port_depth)
1595	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1596	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1597
1598	SC_START(0); // fct melay
1599
1600	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
1601	port,
1602	in_PREDICT_VAL [port]->read(),
1603	out_PREDICT_ACK [port]->read(),
1604	in_PREDICT_BTB_IS_ACCURATE [port]->read());
1605
1606	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
1607	{
1608	LABEL("PREDICT [%d] - Transaction accepted",port);
1609	have_transaction = true;
1610
1611	if (_param->_have_port_depth)
1612	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
1613
1614	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
1615	}
1616
1617	SC_START(1); // transition
1618
1619	} while (not have_transaction);
1620
1621	ufpt.push_back(request); // to update
1622
1623	in_PREDICT_VAL [port]->write(0);
1624
1625	if (_param->_have_port_depth)
1626	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1627	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1628	}
1629	}
1630
1631	std::list<request_t>::iterator it_event;
1632	{
1633	LABEL("BRANCH_COMPLETE - Miss ifetch");
1634
1635	uint32_t port = rand() % _param->_nb_inst_branch_complete;
1636
1637	LABEL(" * port : %d",port);
1638
1639	// middle
1640	it_event = upt.begin();
1641	for (uint32_t i=0; i < (upt.size()>>1); ++i)
1642	it_event ++;
1643
1644	for (std::list<request_t>::iterator it_upt = it_event;
1645	it_upt != upt.end();
1646	++it_upt)
1647	it_upt->miss_commit = true;
1648
1649	if (update_ras(it_event->condition))
1650	{
1651	it_event->address_good = ~(it_event->address_dest);
1652	}
1653	else
1654	{
1655	it_event->address_good = it_event->address_dest;
1656	it_event->flag = not it_event->flag;
1657	it_event->no_sequence = not it_event->no_sequence;
1658	it_event->take_good = not it_event->take_good;
1659	}
1660
1661	event = *it_event;
1662
1663
1664	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1665	// for (uint32_t i=0; i<upt.size(); i++)
1666	// just one
1667	{
1668	bool have_transaction = false;
1669
1670	do
1671	{
1672	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
1673	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_event->context );
1674	in_BRANCH_COMPLETE_DEPTH [port]->write(it_event->upt_ptr );
1675	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_event->address_good);
1676	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_event->no_sequence );
1677
1678	if (_param->_have_port_depth)
1679	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1680	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1681
1682	SC_START(0);
1683
1684	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
1685
1686	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
1687	{
1688	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
1689	LABEL(" * CONTEXT_ID : %d" ,it_event->context );
1690	LABEL(" * DEPTH : %d" ,it_event->upt_ptr );
1691	LABEL(" * CONDITION : %d" ,it_event->condition );
1692	LABEL(" * ADDRESS : %.8x",it_event->address_good);
1693	LABEL(" * FLAG : %d" ,it_event->flag );
1694	LABEL(" * NO_SEQUENCE : %d" ,it_event->no_sequence );
1695
1696	have_transaction = true;
1697
1698	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_event->miss_commit );
1699	TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_event->take_good );
1700	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_event->address_src );
1701	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_event->address_good);
1702
1703	upt_top_event [it_event->context] = upt_top [it_event->context];
1704	upt_top [it_event->context] = it_event->upt_ptr;
1705	}
1706
1707	SC_START(1);
1708	} while (not have_transaction);
1709
1710	in_BRANCH_COMPLETE_VAL [port]->write(0);
1711
1712	if (_param->_have_port_depth)
1713	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1714	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1715	}
1716	}
1717
1718	{
1719	LABEL("BRANCH_COMPLETE - Hit ifetch");
1720
1721	uint32_t port = rand() % _param->_nb_inst_branch_complete;
1722
1723	LABEL(" * port : %d",port);
1724
1725	std::list<request_t>::iterator it_upt = upt.begin();
1726
1727	while (it_upt != it_event)
1728	{
1729	bool have_transaction = false;
1730
1731	do
1732	{
1733	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
1734	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
1735	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
1736	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_dest);
1737	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence );
1738
1739	if (_param->_have_port_depth)
1740	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1741	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1742
1743	SC_START(0);
1744
1745	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
1746
1747	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
1748	{
1749	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
1750	LABEL(" * CONTEXT_ID : %d" ,it_upt->context );
1751	LABEL(" * DEPTH : %d" ,it_upt->upt_ptr );
1752	LABEL(" * CONDITION : %d" ,it_upt->condition );
1753	LABEL(" * ADDRESS : %.8x",it_upt->address_dest);
1754	LABEL(" * FLAG : %d" ,it_upt->flag );
1755	LABEL(" * NO_SEQUENCE : %d" ,it_event->no_sequence );
1756
1757	have_transaction = true;
1758
1759	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
1760	TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take );
1761	it_upt->take_good = it_upt->take;
1762	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
1763	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_dest);
1764
1765	it_upt++;
1766	}
1767
1768	SC_START(1);
1769	} while (not have_transaction);
1770
1771	in_BRANCH_COMPLETE_VAL [port]->write(0);
1772
1773	if (_param->_have_port_depth)
1774	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1775	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1776	}
1777	}
1778
1779	if (have_ufpt_ras)
1780	{
1781	LABEL("UPDATE - Update UPFT");
1782
1783	uint32_t port = 0;
1784
1785	LABEL(" * port : %d",port);
1786	std::list<request_t>::iterator it_ufpt = ufpt.end();
1787	-- it_ufpt;
1788
1789	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1790	{
1791	bool have_transaction = false;
1792
1793	do
1794	{
1795	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
1796
1797	// if (_param->_have_port_depth)
1798	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
1799	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
1800
1801	SC_START(0);
1802
1803	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
1804
1805	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
1806	{
1807	LABEL("UPDATE [%d] - Transaction accepted",port);
1808	have_transaction = true;
1809
1810	if (_param->_have_port_context_id)
1811	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_ufpt->context);
1812	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),(it_ufpt->miss_ifetch or
1813	it_ufpt->miss_decod or
1814	it_ufpt->miss_commit ));
1815	// if (update_btb(it_ufpt->condition) or
1816	// update_dir(it_ufpt->condition))
1817	// TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_ufpt->take_good);
1818	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),0);
1819	// if (update_btb(it_ufpt->condition))
1820	// {
1821	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_ufpt->address_src);
1822	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_ufpt->address_dest);
1823	// TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_ufpt->condition);
1824	// }
1825	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),0);
1826
1827	// if (update_dir(it_ufpt->condition))
1828	// if (_param->_have_port_history)
1829	// TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_ufpt->history);
1830	// TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_ufpt->condition));
1831	if (update_ras(it_ufpt->condition))
1832	{
1833	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
1834	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_ufpt->condition));
1835	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_ufpt->ras_address);
1836	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_ufpt->ras_index);
1837	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch);
1838	}
1839	}
1840
1841	SC_START(1);
1842	} while (not have_transaction);
1843
1844	-- it_ufpt;
1845
1846
1847	in_UPDATE_ACK [port]->write(0);
1848	// if (_param->_have_port_depth)
1849	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
1850	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
1851	}
1852	}
1853	ufpt.clear();
1854
1855	{
1856	LABEL("UPDATE - upt (after event)");
1857
1858	uint32_t port = 0;
1859
1860	LABEL(" * port : %d",port);
1861	std::list<request_t>::iterator it_upt = upt.end();
1862
1863	// for (uint32_t i=0; i<upt.size(); i++)
1864	do
1865	{
1866	--it_upt;
1867
1868	bool have_transaction = false;
1869
1870	if (need_update(it_upt->condition))
1871	do
1872	{
1873	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
1874
1875	// if (_param->_have_port_depth)
1876	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1877	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1878
1879	SC_START(0);
1880
1881	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
1882
1883	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
1884	{
1885	LABEL("UPDATE [%d] - Transaction accepted",port);
1886	LABEL(" * address_src : %.8x",it_upt->address_src);
1887	LABEL(" * out_UPDATE_BTB_ADDRESS_SRC : %.8x",out_UPDATE_BTB_ADDRESS_SRC[port]->read());
1888
1889	have_transaction = true;
1890
1891	bool btb_val = ((it_upt == it_event) and
1892	(update_btb(it_upt->condition)));
1893	bool dir_val = ((it_upt == it_event) and
1894	update_dir(it_upt->condition) and
1895	not (it_upt->miss_ifetch or it_upt->miss_decod));
1896	bool ras_val = update_ras(it_upt->condition);
1897
1898	if (_param->_have_port_context_id)
1899	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
1900	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
1901	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),btb_val);
1902
1903	if (btb_val)
1904	{
1905	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
1906	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
1907	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
1908	}
1909	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),dir_val);
1910
1911	if (dir_val)
1912	{
1913	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
1914	if (_param->_have_port_history)
1915	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
1916	}
1917	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),ras_val);
1918
1919	if (ras_val)
1920	{
1921	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
1922	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
1923	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
1924	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
1925	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
1926	}
1927
1928	// -- it_upt;
1929	}
1930
1931	SC_START(1);
1932	} while (not have_transaction);
1933
1934	upt.pop_back();
1935	in_UPDATE_ACK [port]->write(0);
1936	// if (_param->_have_port_depth)
1937	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1938	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1939	}
1940	while (it_upt != it_event);
1941
1942	}
1943
1944	{
1945	LABEL("BRANCH_EVENT - have miss decod");
1946
1947	uint32_t port = context;
1948
1949	{
1950	bool have_transaction = false;
1951
1952	do
1953	{
1954	in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event);
1955
1956	SC_START(0);
1957
1958	LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read());
1959
1960	if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read())
1961	{
1962	LABEL("BRANCH_EVENT [%d] - Transaction accepted",port);
1963	have_transaction = true;
1964
1965	LABEL(" * event.address_src : %.8x,",event.address_src );
1966	LABEL(" * event.address_good : %.8x,",event.address_good);
1967	LABEL(" * event.take : %.8x,",event.take );
1968
1969	TEST(Tdepth_t ,out_BRANCH_EVENT_DEPTH [port]->read(),event.upt_ptr);
1970	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src);
1971	TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take_good);
1972	if (event.take_good)
1973	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good);
1974
1975	event.address_src = 0;
1976	event.take = 0;
1977	event.address_dest = 0;
1978	}
1979
1980	SC_START(1);
1981	} while (not have_transaction);
1982
1983	in_BRANCH_EVENT_ACK [port]->write(0);
1984	}
1985	}
1986
1987	{
1988	LABEL("EVENT_STATE");
1989
1990	SC_START(1);
1991	in_EVENT_VAL [context]->write(1);
1992	in_EVENT_TYPE [context]->write(EVENT_TYPE_MISS_SPECULATION);
1993
1994	SC_START(1);
1995	in_EVENT_VAL [context]->write(0);
1996	in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE );
1997	}
1998
1999	{
2000	LABEL("UPDATE - upt (before event)");
2001
2002	uint32_t port = 0;
2003
2004	LABEL(" * port : %d",port);
2005	LABEL(" * size : %d",upt.size());
2006	std::list<request_t>::iterator it_upt = upt.begin();
2007
2008	for (uint32_t i=0; i<upt.size(); i++)
2009	{
2010	bool have_transaction = false;
2011
2012	do
2013	{
2014	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
2015
2016	// if (_param->_have_port_depth)
2017	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2018	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2019
2020	SC_START(0);
2021
2022	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
2023
2024	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
2025	{
2026	LABEL("UPDATE [%d] - Transaction accepted",port);
2027	have_transaction = true;
2028
2029	if (_param->_have_port_context_id)
2030	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
2031	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
2032	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
2033	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
2034	if (update_btb(it_upt->condition))
2035	{
2036	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
2037	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
2038	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
2039	}
2040	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
2041
2042	if (update_dir(it_upt->condition))
2043	if (_param->_have_port_history)
2044	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
2045	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
2046	if (update_ras(it_upt->condition))
2047	{
2048	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
2049	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
2050	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
2051	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
2052	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
2053	}
2054
2055	++ it_upt;
2056	}
2057
2058	SC_START(1);
2059	} while (not have_transaction);
2060
2061	in_UPDATE_ACK [port]->write(0);
2062	// if (_param->_have_port_depth)
2063	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2064	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2065	}
2066	}
2067	upt.clear();
2068
2069	// Wait Garbage Collector
2070	{
2071	LABEL("GARBAGE COLLECTOR");
2072	LABEL(" * upt bottom : %d",upt_bottom [context]);
2073	LABEL(" * upt top : %d",upt_top [context]);
2074
2075	upt_top [context] = (upt_top_event [context]);
2076	upt_bottom [context] = (upt_top [context]);
2077
2078	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
2079	(upt_top [context] != out_DEPTH_MAX [context]->read()))
2080	{
2081	SC_START(1);
2082	}
2083
2084	}
2085	}
2086
2087	}// ITERATION
2088
2089	/********************************************************
2090	* Simulation - End
2091	********************************************************/
2092
2093	TEST_OK ("End of Simulation");
2094	delete _time;
2095
2096	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
2097
2098	delete in_CLOCK;
2099	delete in_NRESET;
2100
2101	// ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2102	delete [] in_PREDICT_VAL ;
2103	delete [] out_PREDICT_ACK ;
2104	delete [] in_PREDICT_CONTEXT_ID ;
2105	delete [] in_PREDICT_BTB_ADDRESS_SRC ;
2106	delete [] in_PREDICT_BTB_ADDRESS_DEST ;
2107	delete [] in_PREDICT_BTB_CONDITION ;
2108	delete [] in_PREDICT_BTB_LAST_TAKE ;
2109	delete [] in_PREDICT_BTB_IS_ACCURATE ;
2110	delete [] in_PREDICT_DIR_HISTORY ;
2111	delete [] in_PREDICT_RAS_ADDRESS ;
2112	delete [] in_PREDICT_RAS_INDEX ;
2113	delete [] out_PREDICT_UPDATE_PREDICTION_ID;
2114
2115	// ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2116	delete [] in_DECOD_VAL ;
2117	delete [] out_DECOD_ACK ;
2118	delete [] in_DECOD_CONTEXT_ID ;
2119	delete [] in_DECOD_BTB_ADDRESS_SRC ;
2120	delete [] in_DECOD_BTB_ADDRESS_DEST ;
2121	delete [] in_DECOD_BTB_CONDITION ;
2122	delete [] in_DECOD_BTB_LAST_TAKE ;
2123	delete [] in_DECOD_RAS_ADDRESS ;
2124	delete [] in_DECOD_RAS_INDEX ;
2125	delete [] in_DECOD_MISS_IFETCH ;
2126	delete [] in_DECOD_MISS_DECOD ;
2127	delete [] in_DECOD_UPDATE_PREDICTION_ID ;
2128	//delete [] out_DECOD_DEPTH ;
2129	delete [] in_DECOD_IS_ACCURATE ;
2130
2131	// ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2132	delete [] in_BRANCH_COMPLETE_VAL ;
2133	delete [] out_BRANCH_COMPLETE_ACK ;
2134	delete [] in_BRANCH_COMPLETE_CONTEXT_ID ;
2135	delete [] in_BRANCH_COMPLETE_DEPTH ;
2136	delete [] in_BRANCH_COMPLETE_ADDRESS ;
2137	delete [] in_BRANCH_COMPLETE_NO_SEQUENCE ;
2138	delete [] out_BRANCH_COMPLETE_MISS_PREDICTION;
2139	delete [] out_BRANCH_COMPLETE_TAKE ;
2140	delete [] out_BRANCH_COMPLETE_ADDRESS_SRC ;
2141	delete [] out_BRANCH_COMPLETE_ADDRESS_DEST ;
2142
2143	// ~~~~~[ Interface : "branch_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2144	delete [] out_BRANCH_EVENT_VAL ;
2145	delete [] in_BRANCH_EVENT_ACK ;
2146	//delete [] out_BRANCH_EVENT_CONTEXT_ID ;
2147	delete [] out_BRANCH_EVENT_DEPTH ;
2148	//delete [] out_BRANCH_EVENT_MISS_PREDICTION;
2149	delete [] out_BRANCH_EVENT_ADDRESS_SRC ;
2150	delete [] out_BRANCH_EVENT_ADDRESS_DEST_VAL;
2151	delete [] out_BRANCH_EVENT_ADDRESS_DEST ;
2152
2153	// ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2154	delete [] out_UPDATE_VAL ;
2155	delete [] in_UPDATE_ACK ;
2156	delete [] out_UPDATE_CONTEXT_ID ;
2157	delete [] out_UPDATE_MISS_PREDICTION ;
2158	delete [] out_UPDATE_DIRECTION_GOOD ;
2159	delete [] out_UPDATE_BTB_VAL ;
2160	delete [] out_UPDATE_BTB_ADDRESS_SRC ;
2161	delete [] out_UPDATE_BTB_ADDRESS_DEST ;
2162	delete [] out_UPDATE_BTB_CONDITION ;
2163	delete [] out_UPDATE_DIR_VAL ;
2164	delete [] out_UPDATE_DIR_HISTORY ;
2165	delete [] out_UPDATE_RAS_VAL ;
2166	delete [] out_UPDATE_RAS_FLUSH ;
2167	delete [] out_UPDATE_RAS_PUSH ;
2168	delete [] out_UPDATE_RAS_ADDRESS ;
2169	delete [] out_UPDATE_RAS_INDEX ;
2170	delete [] out_UPDATE_RAS_PREDICTION_IFETCH;
2171
2172	DELETE1_SC_SIGNAL( in_EVENT_VAL ,_param->_nb_context);
2173	DELETE1_SC_SIGNAL(out_EVENT_ACK ,_param->_nb_context);
2174	DELETE1_SC_SIGNAL( in_EVENT_TYPE ,_param->_nb_context);
2175	DELETE1_SC_SIGNAL( in_EVENT_DEPTH ,_param->_nb_context);
2176
2177	// ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2178	delete [] out_DEPTH_CURRENT;
2179	delete [] out_DEPTH_MIN;
2180	delete [] out_DEPTH_MAX;
2181
2182	#endif
2183
2184	delete _Update_Prediction_Table;
2185	#ifdef STATISTICS
2186	delete _parameters_statistics;
2187	#endif
2188	}

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