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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp @ 107

Last change on this file since 107 was 107, checked in by rosiere, 15 years ago
1) Fix test in Direction_Glue for Conditionnal Branch 2) Fix Instruction Address Compute
Property svn:keywords set to `Id`
File size: 50.2 KB

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1	#ifdef SYSTEMC
2	/*
3	* $Id: Update_Prediction_Table_transition.cpp 107 2009-02-10 23:03:25Z rosiere $
4	*
5	* [ Description ]
6	*
7	*/
8
9	#include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_front_end {
15	namespace front_end {
16	namespace prediction_unit {
17	namespace update_prediction_table {
18
19	#undef FUNCTION
20	#define FUNCTION "Update_Prediction_Table::transition"
21	void Update_Prediction_Table::transition (void)
22	{
23	log_begin(Update_Prediction_Table,FUNCTION);
24	log_function(Update_Prediction_Table,FUNCTION,_name.c_str());
25
26	if (PORT_READ(in_NRESET) == 0)
27	{
28	// Initialisation
29
30	reg_UPDATE_PRIORITY = 0;
31
32	// All pointer is set at 0
33	for (uint32_t i=0; i<_param->_nb_context; i++)
34	{
35	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j)
36	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY;
37	reg_UFPT_BOTTOM [i] = 0;
38	reg_UFPT_TOP [i] = 0;
39	reg_UFPT_UPDATE [i] = 0;
40	reg_UFPT_NB_NEED_UPDATE [i] = 0;
41	reg_UFPT_NB_UPDATE [i] = 0;
42
43	for (uint32_t j=0; j<_param->_size_upt_queue[i]; ++j)
44	reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EMPTY;
45	reg_UPT_BOTTOM [i] = 0;
46	reg_UPT_TOP [i] = 0;
47	reg_UPT_TOP_EVENT [i] = 0;
48	reg_UPT_UPDATE [i] = 0;
49	reg_UPT_EMPTY [i] = true;
50
51	reg_IS_ACCURATE [i] = true;
52
53	reg_EVENT_VAL [i] = false;
54	reg_EVENT_STATE [i] = EVENT_STATE_OK;
55	}
56	}
57	else
58	{
59	bool flush_UFPT [_param->_nb_context];
60	for (uint32_t i=0; i<_param->_nb_context; i++)
61	{
62	flush_UFPT [i] = false;
63	}
64
65	// ===================================================================
66	// =====[ GARBAGE COLLECTOR ]=========================================
67	// ===================================================================
68
69	// Each cycle, if the most lastest branch have update all prediction struction (state = end), free this slot
70	// * Update state -> new status is "empty"
71	// * Update pointer (bottom and accurate)
72	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * GARBAGE COLLECTOR (BEGIN)");
73	for (uint32_t i=0; i<_param->_nb_context; i++)
74	{
75	// UPDATE_FETCH_PREDICTION_TABLE
76	{
77	uint32_t bottom = reg_UFPT_BOTTOM [i];
78
79	// Test if state is end
80	if (reg_UPDATE_FETCH_PREDICTION_TABLE [i][bottom]._state == UPDATE_FETCH_PREDICTION_STATE_END)
81	{
82	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d]",i,bottom);
83	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state = UPDATE_FETCH_PREDICTION_STATE_EMPTY",i,bottom);
84
85	// Free slot
86	reg_UPDATE_FETCH_PREDICTION_TABLE [i][bottom]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY;
87	// Update pointer
88	reg_UFPT_BOTTOM [i] = (bottom+1)%_param->_size_ufpt_queue[i];
89	}
90	}
91
92	// UPDATE_PREDICTION_TABLE
93	{
94	uint32_t bottom = reg_UPT_BOTTOM [i];
95	bool end = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END);
96	// bool end_ok = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END_OK);
97	// bool end_ko = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END_KO);
98	// event_state_t event_state = reg_EVENT_STATE [i];
99
100	// Test if state is end
101	// if (end_ok or end_ko)
102	if (end)
103	{
104	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d]",i,bottom);
105	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d]._state = UPDATE_PREDICTION_STATE_EMPTY",i,bottom);
106	// Free slot
107	reg_UPDATE_PREDICTION_TABLE [i][bottom]._state = UPDATE_PREDICTION_STATE_EMPTY;
108
109	// Update pointer
110	reg_UPT_BOTTOM [i] = (bottom+1)%_param->_size_upt_queue[i];
111
112	if (reg_UPT_BOTTOM [i] == reg_UPT_TOP [i])
113	reg_UPT_EMPTY [i] = true; // free a slot
114
115	// if (bottom = reg_UPT_UPDATE [i])
116	// reg_UPT_UPDATE [i] = reg_UPT_BOTTOM [i];
117
118	if (reg_EVENT_VAL [i] and (reg_EVENT_UPT_PTR [i] == bottom))
119	{
120	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * END EVENT");
121
122	reg_EVENT_VAL [i] = false;
123	reg_UPT_TOP [i] = reg_UPT_TOP_EVENT [i];
124	reg_UPT_UPDATE [i] = reg_UPT_TOP_EVENT [i];
125
126	if (reg_UPT_BOTTOM [i] != reg_UPT_TOP [i])
127	reg_UPT_EMPTY [i] = false;
128	}
129
130	}
131	}
132	}
133
134	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * GARBAGE COLLECTOR (END)");
135
136	// ===================================================================
137	// =====[ PREDICT ]===================================================
138	// ===================================================================
139
140	// An ifetch_unit compute next cycle and have an branch : predict_val is set
141	// * Alloc new entry -> new status is "wait decod"
142	// * Save input (to restore in miss or error)
143	// * Update pointer
144
145	for (uint32_t i=0; i<_param->_nb_inst_predict; i++)
146	if (PORT_READ(in_PREDICT_VAL[i]) and internal_PREDICT_ACK [i])
147	{
148	Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_PREDICT_CONTEXT_ID [i]):0;
149	uint32_t top = internal_PREDICT_UPDATE_PREDICTION_ID [i];
150
151	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * PREDICT[%d] - Accepted",i);
152	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);
153	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top);
154
155	#ifdef DEBUG_TEST
156	if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._state != UPDATE_FETCH_PREDICTION_STATE_EMPTY)
157	throw ERRORMORPHEO(FUNCTION,_("Predict : invalid state."));
158	#endif
159
160	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD (predict)",context,top);
161	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._state = UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD;
162
163	Tbranch_condition_t condition = PORT_READ(in_PREDICT_BTB_CONDITION [i]);
164
165	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._condition = condition;
166	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_src = PORT_READ(in_PREDICT_BTB_ADDRESS_SRC [i]);
167	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_dest = PORT_READ(in_PREDICT_BTB_ADDRESS_DEST [i]);
168	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._last_take = PORT_READ(in_PREDICT_BTB_LAST_TAKE [i]);
169	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._is_accurate = PORT_READ(in_PREDICT_BTB_IS_ACCURATE [i]);
170	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._history = (_param->_have_port_history)?PORT_READ(in_PREDICT_DIR_HISTORY [i]):0;
171	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_ras = PORT_READ(in_PREDICT_RAS_ADDRESS [i]);
172	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._index_ras = PORT_READ(in_PREDICT_RAS_INDEX [i]);
173
174	reg_UFPT_TOP [context] = (top+1)%_param->_size_ufpt_queue [context];
175	// reg_UFPT_UPDATE [context] = reg_UFPT_TOP [context];
176	if (need_update(condition))
177	reg_UFPT_NB_NEED_UPDATE [context] ++;
178	}
179
180	// ===================================================================
181	// =====[ DECOD ]=====================================================
182	// ===================================================================
183
184
185	// An decod is detected by decod stage
186	// 1) Hit prediction : The instruction bundle have a branch predicted in ifetch stage and it is this branch
187	// * Update state, wait_decod -> wait_end
188	// * Pop ufpt -> push upt
189	// * Update accurate register : if the predict stage have tagged this branch as not accurate, stop decod
190	// 2) Miss : The instruction bundle have a branch but it is not predicted
191	// * Flush ufpt
192	// * decod information is write in upt
193
194	for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
195	if (PORT_READ(in_DECOD_VAL[i]) and internal_DECOD_ACK [i])
196	{
197	Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0;
198	Tcontrol_t miss_ifetch = PORT_READ(in_DECOD_MISS_IFETCH [i]);
199	Tcontrol_t miss_decod = PORT_READ(in_DECOD_MISS_DECOD [i]);
200	uint32_t upt_ptr_write = internal_DECOD_UPT_PTR_WRITE [i];
201	Tbranch_condition_t condition ;
202	Tcontrol_t is_accurate;
203	Taddress_t address_src = PORT_READ(in_DECOD_BTB_ADDRESS_SRC [i]);
204	Taddress_t address_dest = PORT_READ(in_DECOD_BTB_ADDRESS_DEST [i]);
205	Tcontrol_t last_take = PORT_READ(in_DECOD_BTB_LAST_TAKE [i]);
206
207	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * DECOD[%d] - Accepted",i);
208	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);
209	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_ifetch : %d",miss_ifetch);
210	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_decod : %d",miss_decod);
211	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * upt_ptr_write : %d",upt_ptr_write);
212
213	if (miss_ifetch or miss_decod)
214	{
215	// Have a miss !!!
216	#ifdef DEBUG_TEST
217	if (reg_EVENT_STATE [context] != EVENT_STATE_OK)
218	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid event state."));
219	#endif
220
221	if (reg_UFPT_NB_NEED_UPDATE [context] == 0)
222	{
223	// Change state
224	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_UPDATE_CONTEXT (decod - miss - no flush ufpt)",context);
225	reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT;
226	}
227	else
228	{
229	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UFPT (decod - miss - flush ufpt)",context);
230	reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UFPT;
231	}
232
233	// Flush UPFT
234	flush_UFPT [context] = true;
235
236	reg_EVENT_DEPTH [context] = upt_ptr_write;
237	reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State
238	reg_EVENT_ADDRESS_DEST_VAL[context] = last_take;
239	reg_EVENT_ADDRESS_DEST [context] = address_dest;
240
241	// Push upt (from decod interface)
242	condition = PORT_READ(in_DECOD_BTB_CONDITION [i]);
243	is_accurate = PORT_READ(in_DECOD_IS_ACCURATE [i]);
244
245	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._condition = condition;
246	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_src = address_src ;
247	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_dest = address_dest;
248	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._last_take = last_take ;
249	// reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._good_take;
250	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._is_accurate = is_accurate;
251	// reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._history = ; // static prediction
252	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_ras = PORT_READ(in_DECOD_RAS_ADDRESS [i]);
253	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._index_ras = PORT_READ(in_DECOD_RAS_INDEX [i]);
254	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._ifetch_prediction = false; // static prediction
255	}
256	else
257	{
258	// Normal case : branch is previous predicated, change state of branch
259	uint32_t ufpt_ptr_read = (_param->_have_port_depth)?PORT_READ(in_DECOD_UPDATE_PREDICTION_ID [i]):0;
260
261	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * ufpt_ptr_read : %d",ufpt_ptr_read);
262
263	#ifdef DEBUG_TEST
264	if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._state != UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD)
265	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid ufpt state."));
266	#endif
267	// Change state
268	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_END (decod - hit)",context,ufpt_ptr_read);
269	reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._state = UPDATE_FETCH_PREDICTION_STATE_END;
270
271	// Push upt (from Pop ufpt)
272	condition = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._condition;
273	is_accurate = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._is_accurate;
274
275	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._condition = condition;
276	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_src = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_src ;
277	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_dest = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_dest;
278	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._last_take = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._last_take ;
279	// reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._good_take;
280	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._is_accurate = is_accurate;
281	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._history = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._history ;
282	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_ras = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_ras ;
283	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._index_ras = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._index_ras ;
284	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._ifetch_prediction = true ; // prediction from ifetch
285
286	// Update pointer
287	if (need_update(condition))
288	{
289	reg_UFPT_NB_NEED_UPDATE [context] --;
290	}
291	}
292
293	// All case !!!
294	#ifdef DEBUG_TEST
295	if (reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._state != UPDATE_PREDICTION_STATE_EMPTY)
296	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid upt state."));
297	#endif
298
299	// Change state
300	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_WAIT_END (decod - hit)",context,upt_ptr_write);
301	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._state = UPDATE_PREDICTION_STATE_WAIT_END;
302
303	// Write new accurate
304	#ifdef DEBUG_TEST
305	if (not reg_IS_ACCURATE [context] and not is_accurate)
306	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid accurate flag."));
307	#endif
308	reg_IS_ACCURATE [context] = is_accurate;
309
310	// Update pointer
311	reg_UPT_TOP [context] = (upt_ptr_write+1)%_param->_size_upt_queue [context];
312	reg_UPT_EMPTY [context] = false;
313	// reg_UPT_UPDATE [context] = reg_UPT_TOP [context];
314	}
315
316	// ===================================================================
317	// =====[ BRANCH_COMPLETE ]===========================================
318	// ===================================================================
319
320	// The branch is complete
321	// * Hit prediction :
322	// * update status
323	// * Miss prediction :
324	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
325	if (PORT_READ(in_BRANCH_COMPLETE_VAL[i]) and internal_BRANCH_COMPLETE_ACK [i])
326	{
327	Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0;
328	Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0;
329	Tcontrol_t miss = internal_BRANCH_COMPLETE_MISS_PREDICTION [i];
330	Tcontrol_t good_take = internal_BRANCH_COMPLETE_TAKE [i];
331	Taddress_t good_addr = internal_BRANCH_COMPLETE_ADDRESS_DEST [i];
332
333	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_COMPLETE[%d] - Accepted",i);
334	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);
335	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth);
336	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss);
337
338	if (miss)
339	{
340	// Have a miss !!!
341	// Flush UPFT
342	flush_UFPT [context] = true;
343
344	// Flush UPT
345	uint32_t top = reg_UPT_TOP [context];
346	uint32_t new_update = ((top==0)?_param->_size_upt_queue[context]:top)-1;
347
348	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top);
349	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * new_update : %d",new_update);
350
351	for (uint32_t j=(depth+1)%_param->_size_upt_queue[context];
352	j!=top;
353	j=(j+1)%_param->_size_upt_queue[context])
354	reg_UPDATE_PREDICTION_TABLE [context][j]._state = UPDATE_PREDICTION_STATE_EVENT;
355
356
357	// reg_UPT_BOTTOM [context];
358	reg_UPT_TOP [context] = depth;
359	reg_UPT_TOP_EVENT [context] = top;
360
361	if (reg_UPT_BOTTOM [context] == reg_UPT_TOP [context])
362	reg_UPT_EMPTY [context] = true;
363
364	#ifdef DEBUG_TEST
365	if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END)
366	throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state."));
367	#endif
368
369	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_KO (branch_complete, ifetch hit)",context,depth);
370	reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_KO;
371
372	Taddress_t address_src = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src;
373	event_state_t event_state = reg_EVENT_STATE [context];
374	bool previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or
375	(event_state == EVENT_STATE_MISS_FLUSH_UPT ) or
376	(event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or
377	(event_state == EVENT_STATE_EVENT_FLUSH_UPT));
378	// bool update_ras = (new_update != depth);
379
380	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update_ras : %d",update_ras);
381
382	if (reg_UFPT_NB_NEED_UPDATE [context] > 0)
383	{
384	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT (branch_complete - miss)",context);
385	reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT;
386	}
387	else
388	{
389	// if (not previous_update_ras)
390	{
391	// have ras prediction ?
392	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UPT (branch_complete - miss)",context);
393
394	reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UPT;
395
396	}
397	}
398
399	if (not previous_update_ras)
400	{
401	reg_UPT_UPDATE [context] = new_update;
402	}
403	// else no update
404
405	reg_EVENT_DEPTH [context] = depth;
406	reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State
407	reg_EVENT_ADDRESS_DEST_VAL[context] = good_take;
408	reg_EVENT_ADDRESS_DEST [context] = good_addr;
409	}
410	else
411	{
412	// Hit case
413
414	#ifdef DEBUG_TEST
415	if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END)
416	throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state."));
417	#endif
418
419	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_OK (branch_complete, ifetch hit)",context,depth);
420	reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_OK;
421	}
422
423	// In all case : update good_take
424	reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take = good_take;
425
426	// Write address_dest if need read register
427	Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition;
428
429	if ((condition == BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK) or
430	(condition == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK ) or
431	(condition == BRANCH_CONDITION_READ_STACK ) )
432	reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest = good_addr;
433	}
434
435	// ===================================================================
436	// =====[ UPDATE ]====================================================
437	// ===================================================================
438	{
439	bool can_continue [_param->_nb_context];
440	for (uint32_t i=0; i<_param->_nb_context; ++i)
441	can_continue [i] = true;
442
443	for (uint32_t i=0; i<_param->_nb_inst_update; i++)
444	{
445	Tcontext_t context = internal_UPDATE_CONTEXT_ID [i];
446
447	if ((internal_UPDATE_VAL[i] and PORT_READ(in_UPDATE_ACK [i])) or
448	(internal_UPDATE_VAL_WITHOUT_ACK [i] and can_continue [context]))
449	{
450	Tdepth_t depth = internal_UPDATE_DEPTH [i];
451
452	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPDATE[%d] - Accepted",i);
453	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);
454	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth);
455
456	if (internal_UPDATE_FROM_UFPT [i])
457	{
458	// if free a slot, also all queue is updated
459	// Last slot ?
460	// if (reg_UFPT_UPDATE [context] == reg_UFPT_BOTTOM [context])
461	if ((--reg_UFPT_NB_UPDATE [context])==0)
462	switch (reg_EVENT_STATE [context])
463	{
464	case EVENT_STATE_MISS_FLUSH_UFPT : reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; break;
465	// impossible to have an update on ufpt and reg_upt_update>reg_upt_top
466	case EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT : reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UPT ; break;
467	case EVENT_STATE_EVENT_FLUSH_UFPT : reg_EVENT_STATE [context] = EVENT_STATE_OK ; break;
468	case EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT: reg_EVENT_STATE [context] = EVENT_STATE_EVENT_FLUSH_UPT; break;
469	default : break;
470	}
471
472	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Fetch Prediction Table");
473
474	// Change state
475	#ifdef DEBUG_TEST
476	if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state != UPDATE_FETCH_PREDICTION_STATE_EVENT)
477	throw ERRORMORPHEO(FUNCTION,_("Update : invalid ufpt state."));
478	#endif
479
480	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_END (update)",context,depth);
481
482	reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state = UPDATE_FETCH_PREDICTION_STATE_END;
483
484	// Update pointer
485	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (before) : %d",reg_UFPT_UPDATE [context]);
486	reg_UFPT_UPDATE [context] = ((depth==0)?_param->_size_ufpt_queue[context]:depth)-1;
487	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (after ) : %d",reg_UFPT_UPDATE [context]);
488	// Free a register that need update ?
489	if (need_update(reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._condition))
490	reg_UFPT_NB_NEED_UPDATE [context] --;
491	}
492	else
493	{
494	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Prediction Table");
495
496	// Change state
497	#ifdef DEBUG_TEST
498	if (internal_UPDATE_RAS [i])
499	{
500	if ((reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_EVENT) and
501	(reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_KO ) )
502	throw ERRORMORPHEO(FUNCTION,_("Update : invalid upt state."));
503	}
504	else
505	{
506	if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_OK )
507	throw ERRORMORPHEO(FUNCTION,_("Update : invalid upt state."));
508	}
509	#endif
510
511	// bool have_event = ((reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_KO) or
512	// (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_EVENT));
513	#ifdef STATISTICS
514	Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition;
515	bool ok = (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_OK);
516	#endif
517	bool ko = (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_KO);
518
519	// Have an update, test the state to transiste to the good state
520	if (ko)
521	{
522	// Ko : wait end of all instruction
523	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END_KO_WAIT_END (update)",context,depth);
524
525	// reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_KO_WAIT_END;
526
527	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END_KO (update)",context,depth);
528
529	reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_KO;
530
531	reg_EVENT_VAL [context] = true;
532	reg_EVENT_UPT_PTR [context] = depth;
533
534	#ifdef STATISTICS
535	if (usage_is_set(_usage,USE_STATISTICS))
536	(*_stat_nb_branch_miss [context][condition])++;
537	#endif
538	}
539	else
540	{
541	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END_OK (update)",context,depth);
542	// reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_OK;
543
544	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END (update)",context,depth);
545	reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END;
546
547	#ifdef STATISTICS
548	if (usage_is_set(_usage,USE_STATISTICS))
549	{
550	if (ok)
551	(*_stat_nb_branch_hit [context][condition]) ++;
552	else
553	(*_stat_nb_branch_unused [context]) ++;
554	}
555	#endif
556	}
557
558	// Update pointer
559	// * if update RAS : update pointer is decreaste until it equal at top pointer
560	if (internal_UPDATE_RAS [i])
561	{
562	// if end_event, restart too bottom, else decrease pointer
563	bool end_event = (reg_UPT_UPDATE [context] == reg_UPT_TOP [context]);
564
565	reg_UPT_UPDATE [context] = (end_event)?reg_UPT_BOTTOM[context]:(((depth==0)?_param->_size_upt_queue[context]:depth)-1);
566	if (end_event)
567	{
568	// reg_UPT_UPDATE [context] = reg_UPT_BOTTOM[context];
569
570	if (reg_EVENT_STATE [context] == EVENT_STATE_EVENT_FLUSH_UPT)
571	{
572	reg_EVENT_STATE [context] = EVENT_STATE_OK;
573	}
574	else
575	reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT;
576	}
577	else
578	{
579	reg_UPT_UPDATE [context] = (((depth==0)?_param->_size_upt_queue[context]:depth)-1);
580	}
581	}
582	else
583	{
584	// increase pointer
585	reg_UPT_UPDATE [context] = (depth+1)%_param->_size_upt_queue[context];
586	}
587
588	// Free the branch with no accurate ?
589	if ( (reg_UPDATE_PREDICTION_TABLE [context][depth]._is_accurate == false) and not ko)
590	reg_IS_ACCURATE [context] = true;
591	}
592	}
593	else
594	can_continue [context] = false;
595	}
596
597	// Round robin
598	reg_UPDATE_PRIORITY = (reg_UPDATE_PRIORITY+1)%_param->_nb_context;
599	}
600
601	// ===================================================================
602	// =====[ BRANCH_EVENT ]==============================================
603	// ===================================================================
604	for (uint32_t i=0; i<_param->_nb_context; i++)
605	if (internal_BRANCH_EVENT_VAL [i] and PORT_READ(in_BRANCH_EVENT_ACK [i]))
606	{
607	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_EVENT [%d] - Accepted",i);
608
609	// if different : an other branch is occured
610	if (reg_EVENT_STATE [i] == EVENT_STATE_UPDATE_CONTEXT)
611	{
612	// Change state
613	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_WAIT_END_EVENT (branch_event)",i);
614
615	reg_EVENT_STATE [i] = EVENT_STATE_WAIT_END_EVENT;
616	}
617	}
618
619	// ===================================================================
620	// =====[ EVENT ]=====================================================
621	// ===================================================================
622	for (uint32_t i=0; i<_param->_nb_context; ++i)
623	if (PORT_READ(in_EVENT_VAL [i]) and internal_EVENT_ACK [i])
624	{
625	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT");
626
627	//----------------------------------------------------------------
628	// Cases
629	//----------------------------------------------------------------
630	// * EVENT_TYPE_NONE - nothing
631	// * EVENT_TYPE_MISS_SPECULATION - Change state, reset pointer
632	// * EVENT_TYPE_EXCEPTION - Flush upft and upt, Change state, reset pointer
633	// * EVENT_TYPE_BRANCH_NO_ACCURATE - nothing : manage in decod and update
634	// * EVENT_TYPE_SPR_ACCESS - nothing
635	// * EVENT_TYPE_MSYNC - nothing
636	// * EVENT_TYPE_PSYNC - nothing
637	// * EVENT_TYPE_CSYNC - nothing
638
639	Tevent_type_t event_type = PORT_READ(in_EVENT_TYPE [i]);
640
641	// Test if end of miss -> all previous branch is complete
642	// -> all next branch is finish
643
644	switch (event_type)
645	{
646	case EVENT_TYPE_BRANCH_MISS_SPECULATION :
647	{
648	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * type : EVENT_TYPE_BRANCH_MISS_SPECULATION");
649
650	#ifdef DEBUG_TEST
651	if (reg_EVENT_STATE [i] != EVENT_STATE_WAIT_END_EVENT)
652	throw ERRORMORPHEO(FUNCTION,_("Event : invalid event state."));
653	#endif
654
655	// Change state
656	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_OK (event)",i);
657
658	reg_EVENT_STATE [i] = EVENT_STATE_OK;
659	reg_IS_ACCURATE [i] = true;
660
661	Tdepth_t depth = reg_EVENT_UPT_PTR [i];
662
663	if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state == UPDATE_PREDICTION_STATE_END_KO)
664	{
665	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END (event)",i,depth);
666
667	reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_END;
668	}
669
670	#ifdef DEBUG_TEST
671	// if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_END_KO_WAIT_END)
672	// throw ERRORMORPHEO(FUNCTION,_("Event : invalid upt event state."));
673	// if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_END_KO)
674	// throw ERRORMORPHEO(FUNCTION,_("Event : invalid upt event state."));
675	#endif
676
677	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END_KO (update)",i,depth);
678
679	// reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_END_KO;
680
681	break;
682	}
683	case EVENT_TYPE_LOAD_MISS_SPECULATION :
684	case EVENT_TYPE_EXCEPTION :
685	{
686	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * type : EVENT_TYPE_LOAD_MISS_SPECULATION");
687
688	// Have a miss !!!
689	// Flush UPFT
690	flush_UFPT [i] = true;
691
692	// Flush UPT
693	Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_EVENT_DEPTH [i]):0;
694	uint32_t top = reg_UPT_TOP [i];
695	uint32_t bottom = reg_UPT_BOTTOM [i];
696	uint32_t new_update = ((top==0)?_param->_size_upt_queue[i]:top)-1;
697	uint32_t full = ((depth == top) and (top == bottom) and not reg_UPT_EMPTY [i]);
698	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top);
699	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth);
700	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * new_update : %d",new_update);
701
702	// Test empty
703	if (not reg_UPT_EMPTY [i])
704	{
705	#ifdef DEBUG_TEST
706	if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END)
707	throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state."));
708	#endif
709	reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_EVENT;
710
711	// flush all slot after the event
712	for (uint32_t j=(depth+1)%_param->_size_upt_queue[i];
713	j!=top;
714	j=(j+1)%_param->_size_upt_queue[i])
715	reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EVENT;
716	}
717
718	// reg_UPT_BOTTOM [i];
719	// TODO : special case : event is an exception on branch, also depth is not valid
720	reg_UPT_TOP [i] = depth; // depth is again valid
721	reg_UPT_TOP_EVENT [i] = top;
722
723	if (bottom == reg_UPT_TOP [i])
724	reg_UPT_EMPTY [i] = true;
725
726	reg_EVENT_VAL [i] = true;
727	reg_EVENT_UPT_PTR [i] = depth;
728	event_state_t event_state = reg_EVENT_STATE [i];
729	bool previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or
730	(event_state == EVENT_STATE_MISS_FLUSH_UPT ) or
731	(event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or
732	(event_state == EVENT_STATE_EVENT_FLUSH_UPT));
733	bool update_ras = (top != depth) or full;
734
735	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update_ras : %d",update_ras);
736
737	// new state :
738	// * test if ufpt is empty
739	// * ok : flush upft and upt
740	// * ko : test if have previous flush upt
741	// * ok : nothing
742	// * ko : flush upt
743	if (reg_UFPT_NB_NEED_UPDATE [i] > 0)
744	{
745	if (update_ras)
746	{
747	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT (branch_complete - miss)",i);
748	reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT;
749	}
750	else
751	{
752	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UFPT (branch_complete - miss)",i);
753	reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UFPT;
754	}
755	}
756	else
757	{
758	// if (not previous_update_ras)
759	if (update_ras)
760	{
761	// have ras prediction ?
762	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UPT (branch_complete - miss)",i);
763
764	reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UPT;
765	}
766	else
767	{
768	reg_EVENT_STATE [i] = EVENT_STATE_OK;
769	}
770	}
771
772	if (not previous_update_ras and update_ras)
773	{
774	reg_UPT_UPDATE [i] = new_update;
775	}
776	// else no update
777
778	reg_EVENT_DEPTH [i] = depth;
779	// reg_EVENT_ADDRESS_SRC [i] = address_src; // delay_slot is compute in I_State
780	// reg_EVENT_ADDRESS_DEST_VAL[i] = good_take;
781	// reg_EVENT_ADDRESS_DEST [i] = good_addr;
782
783	break;
784	}
785	default :
786	{
787	// nothing
788	break;
789	}
790	}
791	}
792
793	// ===================================================================
794	// =====[ FLUSH ]=====================================================
795	// ===================================================================
796
797	for (uint32_t i=0; i<_param->_nb_context; ++i)
798	{
799	if (flush_UFPT [i])
800	{
801	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Flush Update Fetch Prediction Table");
802	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",i);
803	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]);
804
805	// It's to accelerate miss speculation
806	if (reg_UFPT_NB_NEED_UPDATE [i] == 0)
807	{
808
809	// No entry need prediction, flush all entry -> Reset
810	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j)
811	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY;
812	reg_UFPT_BOTTOM [i] = 0;
813	reg_UFPT_TOP [i] = 0;
814	// reg_UFPT_UPDATE [i];
815	}
816	else
817	{
818	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j)
819	{
820	reg_UFPT_NB_UPDATE [i] ++;
821	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EVENT;
822	}
823
824	// TOP is next write slot : last slot is TOP-1
825	uint32_t top = reg_UFPT_TOP [i];
826	reg_UFPT_UPDATE [i] = ((top==0)?_param->_size_ufpt_queue[i]:top)-1;
827
828	// reg_UFPT_BOTTOM [i];
829	// reg_UFPT_TOP [i];
830	}
831
832	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (after ) : %d",reg_UFPT_UPDATE [i]);
833
834	}
835	}
836
837	#ifdef STATISTICS
838	if (usage_is_set(_usage,USE_STATISTICS))
839	for (uint32_t i=0; i<_param->_nb_context; i++)
840	{
841	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; j++)
842	if (reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state != UPDATE_FETCH_PREDICTION_STATE_EMPTY)
843	(*_stat_ufpt_queue_nb_elt [i]) ++;
844	for (uint32_t j=0; j<_param->_size_upt_queue[i]; j++)
845	if (reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_EMPTY)
846	(*_stat_upt_queue_nb_elt [i]) ++;
847	}
848	#endif
849
850	// ===================================================================
851	// =====[ PRINT ]=====================================================
852	// ===================================================================
853
854	#if (DEBUG >= DEBUG_TRACE)
855	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Dump Update_Prediction_Table");
856	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPDATE_PRIORITY : %d",reg_UPDATE_PRIORITY);
857	for (uint32_t i=0; i<_param->_nb_context; i++)
858	{
859	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_IS_ACCURATE : %d",reg_IS_ACCURATE [i]);
860	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_VAL : %d" ,reg_EVENT_VAL [i]);
861	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_PTR : %d" ,reg_EVENT_UPT_PTR [i]);
862	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_STATE : %s" ,toString(reg_EVENT_STATE [i]).c_str());
863	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_DEPTH : %d" ,reg_EVENT_DEPTH [i]);
864	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_SRC : %.8x",reg_EVENT_ADDRESS_SRC [i]);
865	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_DEST_VAL: %d" ,reg_EVENT_ADDRESS_DEST_VAL[i]);
866	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_DEST : %.8x",reg_EVENT_ADDRESS_DEST [i]);
867
868	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update_Fetch_Prediction_Table [%d]",i);
869	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_BOTTOM : %d",reg_UFPT_BOTTOM [i]);
870	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_TOP : %d",reg_UFPT_TOP [i]);
871	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE : %d",reg_UFPT_UPDATE [i]);
872	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]);
873	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_UPDATE : %d",reg_UFPT_NB_UPDATE [i]);
874	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; j++)
875	log_printf(TRACE,Update_Prediction_Table,FUNCTION," [%d] %.4d, %.8x (%.8x) %.8x (%.8x), %.1d %.1d, %.8d %.8x (%.8x) %.4d - %s",
876	j,
877	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._condition,
878	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_src,
879	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_src<<2,
880	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_dest,
881	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_dest<<2,
882	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._last_take,
883	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._is_accurate,
884	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._history,
885	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_ras,
886	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_ras<<2,
887	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._index_ras,
888	toString(reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state).c_str()
889	);
890
891	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update_Prediction_Table [%d]",i);
892	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_BOTTOM : %d",reg_UPT_BOTTOM [i]);
893	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP : %d",reg_UPT_TOP [i]);
894	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP_EVENT : %d",reg_UPT_TOP_EVENT [i]);
895	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE : %d",reg_UPT_UPDATE [i]);
896	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EMPTY : %d",reg_UPT_EMPTY [i]);
897	for (uint32_t j=0; j<_param->_size_upt_queue[i]; j++)
898	log_printf(TRACE,Update_Prediction_Table,FUNCTION," [%d] %.4d, %.8x (%.8x) %.8x (%.8x), %.1d %.1d %.1d, %.8d %.8x (%.8x) %.4d - %s",
899	j,
900	reg_UPDATE_PREDICTION_TABLE [i][j]._condition,
901	reg_UPDATE_PREDICTION_TABLE [i][j]._address_src,
902	reg_UPDATE_PREDICTION_TABLE [i][j]._address_src<<2,
903	reg_UPDATE_PREDICTION_TABLE [i][j]._address_dest,
904	reg_UPDATE_PREDICTION_TABLE [i][j]._address_dest<<2,
905	reg_UPDATE_PREDICTION_TABLE [i][j]._last_take,
906	reg_UPDATE_PREDICTION_TABLE [i][j]._good_take,
907	reg_UPDATE_PREDICTION_TABLE [i][j]._is_accurate,
908	reg_UPDATE_PREDICTION_TABLE [i][j]._history,
909	reg_UPDATE_PREDICTION_TABLE [i][j]._address_ras,
910	reg_UPDATE_PREDICTION_TABLE [i][j]._address_ras<<2,
911	reg_UPDATE_PREDICTION_TABLE [i][j]._index_ras,
912	toString(reg_UPDATE_PREDICTION_TABLE [i][j]._state).c_str()
913	);
914	}
915	#endif
916	}
917
918
919	#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
920	end_cycle ();
921	#endif
922
923	log_end(Update_Prediction_Table,FUNCTION);
924	};
925
926	}; // end namespace update_prediction_table
927	}; // end namespace prediction_unit
928	}; // end namespace front_end
929	}; // end namespace multi_front_end
930	}; // end namespace core
931
932	}; // end namespace behavioural
933	}; // end namespace morpheo
934	#endif

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