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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp @ 115

Last change on this file since 115 was 115, checked in by rosiere, 15 years ago
1) Write queue with mealy 2) Network : fix bug 3) leak memory
Property svn:keywords set to `Id`
File size: 71.2 KB

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1	#ifdef SYSTEMC
2	/*
3	* $Id: Update_Prediction_Table_transition.cpp 115 2009-04-20 21:29:17Z rosiere $
4	*
5	* [ Description ]
6	*
7	*/
8
9	#include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_front_end {
15	namespace front_end {
16	namespace prediction_unit {
17	namespace update_prediction_table {
18
19	#undef FUNCTION
20	#define FUNCTION "Update_Prediction_Table::transition"
21	void Update_Prediction_Table::transition (void)
22	{
23	log_begin(Update_Prediction_Table,FUNCTION);
24	log_function(Update_Prediction_Table,FUNCTION,_name.c_str());
25
26	if (PORT_READ(in_NRESET) == 0)
27	{
28	// Initialisation
29
30	reg_UPDATE_PRIORITY = 0;
31
32	// All pointer is set at 0
33	for (uint32_t i=0; i<_param->_nb_context; i++)
34	{
35	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j)
36	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY;
37	reg_UFPT_BOTTOM [i] = 0;
38	reg_UFPT_TOP [i] = 0;
39	reg_UFPT_UPDATE [i] = 0;
40	reg_UFPT_NB_NEED_UPDATE [i] = 0;
41	reg_UFPT_NB_UPDATE [i] = 0;
42
43	for (uint32_t j=0; j<_param->_size_upt_queue[i]; ++j)
44	reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EMPTY;
45	reg_UPT_BOTTOM [i] = 0;
46	reg_UPT_TOP [i] = 0;
47	reg_UPT_TOP_EVENT [i] = 0;
48	reg_UPT_UPDATE [i] = 0;
49	reg_UPT_EMPTY [i] = true;
50
51	reg_IS_ACCURATE [i] = true;
52
53	reg_EVENT_VAL [i] = false;
54	reg_EVENT_STATE [i] = EVENT_STATE_OK;
55	reg_EVENT_IS_BRANCH [i] = true;
56	}
57	}
58	else
59	{
60	bool flush_UFPT [_param->_nb_context];
61	for (uint32_t i=0; i<_param->_nb_context; i++)
62	{
63	flush_UFPT [i] = false;
64	}
65
66	// ===================================================================
67	// =====[ GARBAGE COLLECTOR ]=========================================
68	// ===================================================================
69
70	// Each cycle, if the most lastest branch have update all prediction struction (state = end), free this slot
71	// * Update state -> new status is "empty"
72	// * Update pointer (bottom and accurate)
73	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * GARBAGE COLLECTOR (BEGIN)");
74	for (uint32_t i=0; i<_param->_nb_context; i++)
75	{
76	// UPDATE_FETCH_PREDICTION_TABLE
77	{
78	uint32_t bottom = reg_UFPT_BOTTOM [i];
79
80	// Test if state is end
81	if (reg_UPDATE_FETCH_PREDICTION_TABLE [i][bottom]._state == UPDATE_FETCH_PREDICTION_STATE_END)
82	{
83	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d]",i,bottom);
84	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state = UPDATE_FETCH_PREDICTION_STATE_EMPTY",i,bottom);
85
86	// Free slot
87	reg_UPDATE_FETCH_PREDICTION_TABLE [i][bottom]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY;
88	// Update pointer
89	reg_UFPT_BOTTOM [i] = (bottom+1)%_param->_size_ufpt_queue[i];
90	}
91	}
92
93	// UPDATE_PREDICTION_TABLE
94	{
95	uint32_t bottom = reg_UPT_BOTTOM [i];
96	bool end = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END);
97	// bool end_ok = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END_OK);
98	// bool end_ko = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END_KO);
99	// event_state_t event_state = reg_EVENT_STATE [i];
100
101	// Test if state is end
102	// if (end_ok or end_ko)
103
104	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state is STATE_END : %d",end);
105	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_BOTTOM (before) : %d",reg_UPT_BOTTOM [i]);
106
107	if (end)
108	{
109	#if defined(DEBUG) and defined(DEBUG_Update_Prediction_Table) and (DEBUG_Update_Prediction_Table == true)
110	if (reg_UPDATE_PREDICTION_TABLE [i][bottom]._retire_ok)
111	{
112	uint32_t num_thread = _param->_translate_num_context_to_num_thread [i];
113	branchement_log_file [num_thread]
114	<< std::hex
115	<< "0x" << reg_UPDATE_PREDICTION_TABLE [i][bottom]._address_src << " "
116	<< "0x" << reg_UPDATE_PREDICTION_TABLE [i][bottom]._address_dest << " "
117	<< std::dec
118	<< reg_UPDATE_PREDICTION_TABLE [i][bottom]._good_take << " - "
119	<< "[" << simulation_cycle() << "] " << " "
120	<< reg_UPDATE_PREDICTION_TABLE [i][bottom]._miss_prediction << " "
121	<< reg_UPDATE_PREDICTION_TABLE [i][bottom]._ifetch_prediction << " "
122	<< "(" << (uint32_t)reg_UPDATE_PREDICTION_TABLE [i][bottom]._condition << ")"
123	<< std::endl;
124	}
125	#endif
126	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d]",i,bottom);
127	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d]._state = UPDATE_PREDICTION_STATE_EMPTY",i,bottom);
128	// Free slot
129	reg_UPDATE_PREDICTION_TABLE [i][bottom]._state = UPDATE_PREDICTION_STATE_EMPTY;
130
131	// Update pointer
132	reg_UPT_BOTTOM [i] = (bottom+1)%_param->_size_upt_queue[i];
133
134	if (reg_UPT_BOTTOM [i] == reg_UPT_TOP [i])
135	reg_UPT_EMPTY [i] = true; // free a slot
136
137	// if (bottom = reg_UPT_UPDATE [i])
138	// reg_UPT_UPDATE [i] = reg_UPT_BOTTOM [i];
139	}// @@@
140
141	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_BOTTOM (after ) : %d",reg_UPT_BOTTOM [i]);
142	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_VAL : %d",reg_EVENT_VAL [i]);
143	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_PTR : %d",reg_EVENT_UPT_PTR [i]);
144	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_FULL : %d",reg_EVENT_UPT_FULL[i]);
145
146	if (reg_EVENT_VAL [i] and (reg_EVENT_UPT_PTR [i] == bottom))
147	{
148	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * END EVENT");
149
150	if ((reg_EVENT_IS_BRANCH [i] == false) and (reg_EVENT_UPT_FULL [i] == false))
151	reg_EVENT_STATE[i] = EVENT_STATE_OK;
152
153	if ((reg_EVENT_IS_BRANCH [i] == true) or (reg_EVENT_UPT_FULL [i] == false))
154	{
155	reg_EVENT_VAL [i] = false;
156	// reg_EVENT_IS_BRANCH [i] = true;
157	reg_UPT_TOP [i] = reg_UPT_TOP_EVENT [i];
158	reg_UPT_UPDATE [i] = reg_UPT_TOP_EVENT [i];
159
160	if (reg_UPT_BOTTOM [i] != reg_UPT_TOP [i])
161	reg_UPT_EMPTY [i] = false;
162	}
163
164	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP : %d",reg_UPT_TOP [i]);
165	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP_EVENT : %d",reg_UPT_TOP_EVENT [i]);
166	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE : %d",reg_UPT_UPDATE [i]);
167	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EMPTY : %d",reg_UPT_EMPTY [i]);
168
169	}
170
171	if (end)
172	reg_EVENT_UPT_FULL [i] = false;
173	}
174	}
175
176	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * GARBAGE COLLECTOR (END)");
177
178	// ===================================================================
179	// =====[ PREDICT ]===================================================
180	// ===================================================================
181
182	// An ifetch_unit compute next cycle and have an branch : predict_val is set
183	// * Alloc new entry -> new status is "wait decod"
184	// * Save input (to restore in miss or error)
185	// * Update pointer
186
187	for (uint32_t i=0; i<_param->_nb_inst_predict; i++)
188	if (PORT_READ(in_PREDICT_VAL[i]) and internal_PREDICT_ACK [i])
189	{
190	Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_PREDICT_CONTEXT_ID [i]):0;
191	uint32_t top = internal_PREDICT_UPDATE_PREDICTION_ID [i];
192
193	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * PREDICT[%d] - Accepted",i);
194	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);
195	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top);
196
197	#ifdef DEBUG_TEST
198	if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._state != UPDATE_FETCH_PREDICTION_STATE_EMPTY)
199	throw ERRORMORPHEO(FUNCTION,_("Predict : invalid state."));
200	#endif
201
202	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD (predict)",context,top);
203	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._state = UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD;
204
205	Tbranch_condition_t condition = PORT_READ(in_PREDICT_BTB_CONDITION [i]);
206
207	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._condition = condition;
208	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_src = PORT_READ(in_PREDICT_BTB_ADDRESS_SRC [i]);
209	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_dest = PORT_READ(in_PREDICT_BTB_ADDRESS_DEST [i]);
210	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._last_take = PORT_READ(in_PREDICT_BTB_LAST_TAKE [i]);
211	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._is_accurate = PORT_READ(in_PREDICT_BTB_IS_ACCURATE [i]);
212	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._history = (_param->_have_port_history)?PORT_READ(in_PREDICT_DIR_HISTORY [i]):0;
213	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_ras = PORT_READ(in_PREDICT_RAS_ADDRESS [i]);
214	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._index_ras = PORT_READ(in_PREDICT_RAS_INDEX [i]);
215
216	reg_UFPT_TOP [context] = (top+1)%_param->_size_ufpt_queue [context];
217	// reg_UFPT_UPDATE [context] = reg_UFPT_TOP [context];
218	if (need_update(condition))
219	{
220	reg_UFPT_NB_NEED_UPDATE [context] ++;
221	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE (after) : %d",reg_UFPT_NB_NEED_UPDATE [context]);
222
223	}
224	}
225
226	// ===================================================================
227	// =====[ DECOD ]=====================================================
228	// ===================================================================
229
230
231	// An decod is detected by decod stage
232	// 1) Hit prediction : The instruction bundle have a branch predicted in ifetch stage and it is this branch
233	// * Update state, wait_decod -> wait_end
234	// * Pop ufpt -> push upt
235	// * Update accurate register : if the predict stage have tagged this branch as not accurate, stop decod
236	// 2) Miss : The instruction bundle have a branch but it is not predicted
237	// * Flush ufpt
238	// * decod information is write in upt
239
240	for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
241	if (PORT_READ(in_DECOD_VAL[i]) and internal_DECOD_ACK [i])
242	{
243	Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0;
244	Tcontrol_t miss_ifetch = PORT_READ(in_DECOD_MISS_IFETCH [i]);
245	Tcontrol_t miss_decod = PORT_READ(in_DECOD_MISS_DECOD [i]);
246	uint32_t upt_ptr_write = internal_DECOD_UPT_PTR_WRITE [i];
247	Tbranch_condition_t condition ;
248	Tcontrol_t is_accurate;
249	Taddress_t address_src = PORT_READ(in_DECOD_BTB_ADDRESS_SRC [i]);
250	Taddress_t address_dest = PORT_READ(in_DECOD_BTB_ADDRESS_DEST [i]);
251	Tcontrol_t last_take = PORT_READ(in_DECOD_BTB_LAST_TAKE [i]);
252
253	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * DECOD[%d] - Accepted",i);
254	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);
255	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_ifetch : %d",miss_ifetch);
256	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_decod : %d",miss_decod);
257	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * upt_ptr_write : %d",upt_ptr_write);
258
259	if (miss_ifetch or miss_decod)
260	{
261	// Have a miss !!!
262	#ifdef DEBUG_TEST
263	if (reg_EVENT_STATE [context] != EVENT_STATE_OK)
264	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid event state."));
265	#endif
266	if (reg_UFPT_NB_NEED_UPDATE [context] == 0)
267	{
268	// Change state
269	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_UPDATE_CONTEXT (decod - miss - no flush ufpt)",context);
270	reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT;
271	// reg_EVENT_SOURCE[context] = EVENT_SOURCE_UFPT;
272	}
273	else
274	{
275	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UFPT (decod - miss - flush ufpt)",context);
276	reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UFPT;
277	}
278
279	// Flush UPFT
280	flush_UFPT [context] = true;
281
282	reg_EVENT_IS_BRANCH [context] = true;
283	reg_EVENT_DEPTH [context] = upt_ptr_write;
284	reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State
285	reg_EVENT_ADDRESS_DEST_VAL[context] = last_take;
286	reg_EVENT_ADDRESS_DEST [context] = address_dest;
287
288	// Push upt (from decod interface)
289	condition = PORT_READ(in_DECOD_BTB_CONDITION [i]);
290	is_accurate = PORT_READ(in_DECOD_IS_ACCURATE [i]);
291
292	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._condition = condition;
293	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_src = address_src ;
294	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_dest = address_dest;
295	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._last_take = last_take ;
296	// reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._good_take;
297	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._is_accurate = is_accurate;
298	// reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._history = ; // static prediction
299	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_ras = PORT_READ(in_DECOD_RAS_ADDRESS [i]);
300	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._index_ras = PORT_READ(in_DECOD_RAS_INDEX [i]);
301	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._ifetch_prediction = false; // static prediction
302	}
303	else
304	{
305	// Normal case : branch is previous predicated, change state of branch
306	uint32_t ufpt_ptr_read = (_param->_have_port_depth)?PORT_READ(in_DECOD_UPDATE_PREDICTION_ID [i]):0;
307
308	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * ufpt_ptr_read : %d",ufpt_ptr_read);
309
310	#ifdef DEBUG_TEST
311	if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._state != UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD)
312	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid ufpt state."));
313	#endif
314	// Change state
315	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_END (decod - hit)",context,ufpt_ptr_read);
316	reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._state = UPDATE_FETCH_PREDICTION_STATE_END;
317
318	// Push upt (from Pop ufpt)
319	condition = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._condition;
320	is_accurate = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._is_accurate;
321
322	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._condition = condition;
323	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_src = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_src ;
324	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_dest = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_dest;
325	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._last_take = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._last_take ;
326	// reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._good_take;
327	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._is_accurate = is_accurate;
328	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._history = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._history ;
329	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_ras = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_ras ;
330	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._index_ras = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._index_ras ;
331	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._ifetch_prediction = true ; // prediction from ifetch
332
333	// Update pointer
334	if (need_update(condition))
335	{
336	reg_UFPT_NB_NEED_UPDATE [context] --;
337	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE (after) : %d",reg_UFPT_NB_NEED_UPDATE [context]);
338
339	}
340	}
341
342	// All case !!!
343	#ifdef DEBUG_TEST
344	if (reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._state != UPDATE_PREDICTION_STATE_EMPTY)
345	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid upt state."));
346	#endif
347
348	// Change state
349	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_WAIT_END (decod - hit)",context,upt_ptr_write);
350	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._state = UPDATE_PREDICTION_STATE_WAIT_END;
351	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._retire_ok = false;
352
353	// Write new accurate
354	#ifdef DEBUG_TEST
355	if (not reg_IS_ACCURATE [context] and not is_accurate)
356	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid accurate flag."));
357	#endif
358	reg_IS_ACCURATE [context] = is_accurate;
359
360	// Update pointer
361	reg_UPT_TOP [context] = (upt_ptr_write+1)%_param->_size_upt_queue [context];
362	reg_UPT_EMPTY [context] = false;
363	// reg_UPT_UPDATE [context] = reg_UPT_TOP [context];
364
365	// if (miss_ifetch or miss_decod)
366	// reg_UPT_TOP_EVENT [context] = reg_UPT_TOP [context];
367	}
368
369	// ===================================================================
370	// =====[ UPDATE ]====================================================
371	// ===================================================================
372	{
373	bool can_continue [_param->_nb_context];
374	for (uint32_t i=0; i<_param->_nb_context; ++i)
375	can_continue [i] = true;
376
377	for (uint32_t i=0; i<_param->_nb_inst_update; i++)
378	{
379	Tcontext_t context = internal_UPDATE_CONTEXT_ID [i];
380
381	if ((internal_UPDATE_VAL[i] and PORT_READ(in_UPDATE_ACK [i])) or
382	(internal_UPDATE_VAL_WITHOUT_ACK [i] and can_continue [context]))
383	{
384	Tdepth_t depth = internal_UPDATE_DEPTH [i];
385
386	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPDATE[%d] - Accepted",i);
387	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);
388	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth);
389
390	if (internal_UPDATE_FROM_UFPT [i])
391	{
392	// if free a slot, also all queue is updated
393	// Last slot ?
394	// if (reg_UFPT_UPDATE [context] == reg_UFPT_BOTTOM [context])
395	if ((--reg_UFPT_NB_UPDATE [context])==0)
396	{
397	switch (reg_EVENT_STATE [context])
398	{
399	case EVENT_STATE_MISS_FLUSH_UFPT :
400	{
401	reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT;
402	// reg_EVENT_SOURCE[context] = EVENT_SOURCE_UFPT;
403
404	break;
405	}
406	// impossible to have an update on ufpt and reg_upt_update>reg_upt_top
407	case EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT : reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UPT ; break;
408	case EVENT_STATE_EVENT_FLUSH_UFPT : reg_EVENT_STATE [context] = EVENT_STATE_OK ; break;
409	case EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT: reg_EVENT_STATE [context] = EVENT_STATE_EVENT_FLUSH_UPT; break;
410	default : break;
411	}
412	}
413
414	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Fetch Prediction Table");
415
416	// Change state
417	#ifdef DEBUG_TEST
418	if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state != UPDATE_FETCH_PREDICTION_STATE_EVENT)
419	throw ERRORMORPHEO(FUNCTION,_("Update : invalid ufpt state."));
420	#endif
421
422	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_END (update)",context,depth);
423
424	reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state = UPDATE_FETCH_PREDICTION_STATE_END;
425
426	// Update pointer
427	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (before) : %d",reg_UFPT_UPDATE [context]);
428	reg_UFPT_UPDATE [context] = ((depth==0)?_param->_size_ufpt_queue[context]:depth)-1;
429	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (after ) : %d",reg_UFPT_UPDATE [context]);
430	// Free a register that need update ?
431	if (need_update(reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._condition))
432	{
433	reg_UFPT_NB_NEED_UPDATE [context] --;
434	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE (after) : %d",reg_UFPT_NB_NEED_UPDATE [context]);
435	}
436	}
437	else
438	{
439	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Prediction Table");
440	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE (before) : %d",reg_UPT_UPDATE [context]);
441	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_STATE : %s",toString(reg_EVENT_STATE [context]).c_str());
442
443	// Change state
444	#ifdef DEBUG_TEST
445	if (internal_UPDATE_RAS [i])
446	{
447	if ((reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_EVENT) and
448	(reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_KO ) )
449	throw ERRORMORPHEO(FUNCTION,_("Update : invalid upt state."));
450	}
451	else
452	{
453	if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_OK )
454	throw ERRORMORPHEO(FUNCTION,_("Update : invalid upt state."));
455	}
456	#endif
457
458	// bool have_event = ((reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_KO) or
459	// (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_EVENT));
460	#ifdef STATISTICS
461	Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition;
462	#endif
463	bool ok = (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_OK);
464	bool ko = (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_KO);
465
466	if (ok or ko)
467	{
468	reg_UPDATE_PREDICTION_TABLE [context][depth]._retire_ok = true;
469	reg_UPDATE_PREDICTION_TABLE [context][depth]._miss_prediction = ko;
470
471	#ifdef STATISTICS
472	if (usage_is_set(_usage,USE_STATISTICS))
473	{
474	if (reg_UPDATE_PREDICTION_TABLE [context][depth]._ifetch_prediction)
475	(*_stat_nb_branch_ifetch_prediction [context])++;
476	if (reg_UPDATE_PREDICTION_TABLE [context][depth]._is_accurate)
477	(*_stat_nb_branch_accurate [context])++;
478	}
479	#endif
480	}
481
482	// Have an update, test the state to transiste to the good state
483	if (ko)
484	{
485	// Ko : wait end of all instruction
486	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END_KO_WAIT_END (update)",context,depth);
487
488	// reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_KO_WAIT_END;
489
490	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END_KO (update)",context,depth);
491
492	reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_KO;
493
494	reg_EVENT_VAL [context] = true;
495	reg_EVENT_UPT_PTR [context] = depth;
496	// reg_EVENT_UPT_FULL [context] = 0;
497	// reg_EVENT_UPT_FULL [i] = (not reg_UPT_EMPTY [i] and (bottom == reg_UPT_TOP [i]));
498
499
500	#ifdef STATISTICS
501	if (usage_is_set(_usage,USE_STATISTICS))
502	(*_stat_nb_branch_miss [context][condition])++;
503	#endif
504	}
505	else
506	{
507	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END_OK (update)",context,depth);
508	// reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_OK;
509
510	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END (update)",context,depth);
511	reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END;
512
513	#ifdef STATISTICS
514	if (usage_is_set(_usage,USE_STATISTICS))
515	{
516	if (ok)
517	(*_stat_nb_branch_hit [context][condition]) ++;
518	else
519	(*_stat_nb_branch_unused [context]) ++;
520	}
521	#endif
522	}
523
524	// Update pointer
525	// * if update RAS : update pointer is decreaste until it equal at top pointer
526	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * internal_UPDATE_RAS [%d] : %d",i,internal_UPDATE_RAS [i]);
527
528	if (internal_UPDATE_RAS [i])
529	{
530	// if end_event, restart too bottom, else decrease pointer
531	bool end_event = (reg_UPT_UPDATE [context] == reg_UPT_TOP [context]);
532
533	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * end_event : %d",end_event);
534	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * bottom : %d",reg_UPT_BOTTOM[context]);
535
536	if (end_event)
537	{
538	reg_UPT_UPDATE [context] = (end_event)?reg_UPT_BOTTOM[context]:(((depth==0)?_param->_size_upt_queue[context]:depth)-1);
539	// reg_UPT_UPDATE [context] = reg_UPT_BOTTOM[context];
540
541	if (reg_EVENT_STATE [context] == EVENT_STATE_EVENT_FLUSH_UPT)
542	{
543	reg_EVENT_STATE [context] = EVENT_STATE_OK;
544	}
545	else
546	{
547	reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT;
548	// reg_EVENT_SOURCE[context] = EVENT_SOURCE_UPT;
549	}
550	}
551	else
552	{
553	reg_UPT_UPDATE [context] = (((depth==0)?_param->_size_upt_queue[context]:depth)-1);
554	}
555	}
556	else
557	{
558	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * next update");
559
560	// increase pointer
561	reg_UPT_UPDATE [context] = (depth+1)%_param->_size_upt_queue[context];
562	}
563
564	// Free the branch with no accurate ?
565	if ((reg_UPDATE_PREDICTION_TABLE [context][depth]._is_accurate == false) and not ko)
566	reg_IS_ACCURATE [context] = true;
567
568	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE (after ) : %d",reg_UPT_UPDATE[context]);
569	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_STATE : %s",toString(reg_EVENT_STATE [context]).c_str());
570	}
571	}
572	else
573	can_continue [context] = false;
574	}
575
576	// Round robin
577	reg_UPDATE_PRIORITY = (reg_UPDATE_PRIORITY+1)%_param->_nb_context;
578	}
579
580	// ===================================================================
581	// =====[ BRANCH_COMPLETE ]===========================================
582	// ===================================================================
583
584	// The branch is complete
585	// * Hit prediction :
586	// * update status
587	// * Miss prediction :
588	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
589	if (PORT_READ(in_BRANCH_COMPLETE_VAL[i]) and internal_BRANCH_COMPLETE_ACK [i])
590	{
591	Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0;
592	Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0;
593	Tcontrol_t miss = internal_BRANCH_COMPLETE_MISS_PREDICTION [i];
594	Tcontrol_t good_take = internal_BRANCH_COMPLETE_TAKE [i];
595	Taddress_t good_addr = internal_BRANCH_COMPLETE_ADDRESS_DEST [i];
596
597	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_COMPLETE[%d] - Accepted",i);
598	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);
599	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth);
600	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss);
601	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_STATE : %s",toString(reg_EVENT_STATE [context]).c_str());
602
603	if (miss)
604	{
605	// Flush UPT
606	uint32_t top = reg_UPT_TOP [context];
607	uint32_t new_update = ((top==0)?_param->_size_upt_queue[context]:top)-1;
608
609	Taddress_t address_src = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src;
610	event_state_t event_state = reg_EVENT_STATE [context];
611	upt_state_t event_top = reg_UPDATE_PREDICTION_TABLE [context][top]._state;
612
613	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * event_top : %s",toString(event_top).c_str());
614
615	bool previous_ufpt_event = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or
616	(event_state == EVENT_STATE_MISS_FLUSH_UFPT ) or
617	(event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or
618	(event_state == EVENT_STATE_EVENT_FLUSH_UFPT ));
619
620	bool previous_upt_event = (false
621	or (event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT )
622	or (event_state == EVENT_STATE_MISS_FLUSH_UPT )
623	or (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT)
624	or (event_state == EVENT_STATE_EVENT_FLUSH_UPT )
625	or (event_top == UPDATE_PREDICTION_STATE_END_KO )
626	or (event_top == UPDATE_PREDICTION_STATE_KO )
627	// or (event_state == EVENT_STATE_WAIT_END_EVENT )
628	// or ((event_state == EVENT_STATE_UPDATE_CONTEXT )
629	// and (reg_EVENT_SOURCE [context] == EVENT_SOURCE_UPT))
630	);
631	// bool update_ras = (new_update != depth);
632
633	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top);
634	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * new_update : %d",new_update);
635	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update_ras : %d",update_ras);
636	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * previous_upt_event : %d",previous_upt_event);
637	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * previous_ufpt_event : %d",previous_ufpt_event);
638	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE : %d",reg_UPT_UPDATE [context]);
639
640	// Have a miss !!!
641	// Flush UPFT
642	flush_UFPT [context] \|= not previous_ufpt_event;
643
644	if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_WAIT_END)
645	{
646	for (uint32_t j=(depth+1)%_param->_size_upt_queue[context];
647	j!=top;
648	j=(j+1)%_param->_size_upt_queue[context])
649	{
650	reg_UPDATE_PREDICTION_TABLE [context][j]._state = UPDATE_PREDICTION_STATE_EVENT;
651	reg_UPDATE_PREDICTION_TABLE [context][j]._retire_ok = false;
652	}
653
654
655	// reg_UPT_BOTTOM [context];
656	reg_UPT_TOP [context] = depth;
657	// reg_UPT_TOP_EVENT [context] = top;
658
659	if (not previous_upt_event)
660	{
661	reg_UPT_TOP_EVENT [context] = top;
662	reg_UPT_UPDATE [context] = new_update;
663	}
664	else
665	{
666	// Have event. Top index this slot
667	reg_UPDATE_PREDICTION_TABLE [context][top]._retire_ok = false;
668
669	switch (event_top)
670	{
671	case UPDATE_PREDICTION_STATE_END_KO :
672	{
673	// Have already update predictor
674	reg_UPDATE_PREDICTION_TABLE [context][top]._state = UPDATE_PREDICTION_STATE_END;
675	reg_UPT_UPDATE [context] = new_update;
676	break;
677	}
678	case UPDATE_PREDICTION_STATE_KO :
679	{
680	// Doesn't have update predictor
681	reg_UPDATE_PREDICTION_TABLE [context][top]._state = UPDATE_PREDICTION_STATE_EVENT;
682	break;
683	}
684	default :
685	{
686	// reg_UPDATE_PREDICTION_TABLE [context][top]._state = UPDATE_PREDICTION_STATE_EVENT;
687	// break;
688
689	#ifdef DEBUG_TEST
690	throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state."));
691	#endif
692	}
693	}
694	}
695
696	if (reg_UPT_BOTTOM [context] == reg_UPT_TOP [context])
697	reg_UPT_EMPTY [context] = true;
698
699	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_KO (branch_complete, ifetch hit)",context,depth);
700	reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_KO;
701
702	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE [%d] : %d",context,reg_UFPT_NB_NEED_UPDATE [context]);
703
704	if ( (reg_UFPT_NB_NEED_UPDATE [context] > 0) or
705	(reg_UFPT_NB_UPDATE [context] > 0))
706	{
707	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT (branch_complete - miss)",context);
708	reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT;
709	}
710	else
711	{
712	// if (not previous_update_ras)
713	{
714	// have ras prediction ?
715	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UPT (branch_complete - miss)",context);
716
717	reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UPT;
718
719	}
720	}
721	// reg_EVENT_SOURCE [context] = EVENT_SOURCE_UPT;
722
723	// else no update
724
725	reg_EVENT_IS_BRANCH [context] = true;
726	reg_EVENT_DEPTH [context] = depth;
727	reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State
728	reg_EVENT_ADDRESS_DEST_VAL[context] = good_take;
729	reg_EVENT_ADDRESS_DEST [context] = good_addr;
730	}
731	}
732	else
733	{
734	// Hit case
735
736	// #ifdef DEBUG_TEST
737	// if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END)
738	// throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state."));
739	// #endif
740
741	if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_WAIT_END)
742	{
743	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_OK (branch_complete, ifetch hit)",context,depth);
744	reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_OK;
745	}
746	}
747
748	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_STATE : %s",toString(reg_EVENT_STATE [context]).c_str());
749
750	// In all case : update good_take
751	reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take = good_take;
752
753	// Write address_dest if need read register
754	Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition;
755
756	if ((condition == BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK) or
757	(condition == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK ) or
758	(condition == BRANCH_CONDITION_READ_STACK ) )
759	reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest = good_addr;
760	}
761
762
763	// ===================================================================
764	// =====[ BRANCH_EVENT ]==============================================
765	// ===================================================================
766	for (uint32_t i=0; i<_param->_nb_context; i++)
767	if (internal_BRANCH_EVENT_VAL [i] and PORT_READ(in_BRANCH_EVENT_ACK [i]))
768	{
769	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_EVENT [%d] - Accepted",i);
770
771	// if different : an other branch is occured
772	if (reg_EVENT_STATE [i] == EVENT_STATE_UPDATE_CONTEXT)
773	{
774	// Change state
775	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_WAIT_END_EVENT (branch_event)",i);
776
777	reg_EVENT_STATE [i] = EVENT_STATE_WAIT_END_EVENT;
778	}
779	}
780
781	// ===================================================================
782	// =====[ EVENT ]=====================================================
783	// ===================================================================
784	for (uint32_t i=0; i<_param->_nb_context; ++i)
785	if (PORT_READ(in_EVENT_VAL [i]) and internal_EVENT_ACK [i])
786	{
787	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT");
788
789	//----------------------------------------------------------------
790	// Cases
791	//----------------------------------------------------------------
792	// * EVENT_TYPE_NONE - nothing
793	// * EVENT_TYPE_MISS_SPECULATION - Change state, reset pointer
794	// * EVENT_TYPE_EXCEPTION - Flush upft and upt, Change state, reset pointer
795	// * EVENT_TYPE_BRANCH_NO_ACCURATE - nothing : manage in decod and update
796	// * EVENT_TYPE_SPR_ACCESS - nothing
797	// * EVENT_TYPE_MSYNC - nothing
798	// * EVENT_TYPE_PSYNC - nothing
799	// * EVENT_TYPE_CSYNC - nothing
800
801	Tevent_type_t event_type = PORT_READ(in_EVENT_TYPE [i]);
802
803	// Test if end of miss -> all previous branch is complete
804	// -> all next branch is finish
805
806	switch (event_type)
807	{
808	case EVENT_TYPE_BRANCH_MISS_SPECULATION :
809	{
810	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * type : EVENT_TYPE_BRANCH_MISS_SPECULATION");
811
812	#ifdef DEBUG_TEST
813	if (reg_EVENT_STATE [i] != EVENT_STATE_WAIT_END_EVENT)
814	throw ERRORMORPHEO(FUNCTION,_("Event : invalid event state."));
815	#endif
816
817	// Change state
818	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_OK (event)",i);
819
820	reg_EVENT_STATE [i] = EVENT_STATE_OK;
821	reg_IS_ACCURATE [i] = true;
822
823	Tdepth_t depth = reg_EVENT_UPT_PTR [i];
824
825	if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state == UPDATE_PREDICTION_STATE_END_KO)
826	{
827	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END (event)",i,depth);
828
829	reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_END;
830	}
831
832	#ifdef DEBUG_TEST
833	// if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_END_KO_WAIT_END)
834	// throw ERRORMORPHEO(FUNCTION,_("Event : invalid upt event state."));
835	// if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_END_KO)
836	// throw ERRORMORPHEO(FUNCTION,_("Event : invalid upt event state."));
837	#endif
838
839	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END_KO (update)",i,depth);
840
841	// reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_END_KO;
842
843	break;
844	}
845	case EVENT_TYPE_LOAD_MISS_SPECULATION :
846	case EVENT_TYPE_EXCEPTION :
847	{
848	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * type : EVENT_TYPE_LOAD_MISS_SPECULATION");
849
850	// Have a miss !!!
851	// Flush UPFT
852	flush_UFPT [i] = true;
853
854	// Flush UPT
855	uint32_t bottom = reg_UPT_BOTTOM [i];
856
857	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * bottom : %d",bottom);
858
859	// event_state_t event_state = reg_EVENT_STATE [i];
860	// bool previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or
861	// (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or
862	// (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or
863	// (event_state == EVENT_STATE_EVENT_FLUSH_UPT));
864
865	bool find = false; // have slot to update ???
866	Tdepth_t top = bottom;
867	Tdepth_t update = bottom;
868	bool empty = reg_UPT_EMPTY [i];
869
870	// flush all slot, because this event is in head of rob
871	for (uint32_t j=0; j<_param->_size_upt_queue[i]; ++j)
872	{
873	Tdepth_t x = (bottom+j)%_param->_size_upt_queue[i];
874
875	if ((reg_UPDATE_PREDICTION_TABLE [i][x]._state != UPDATE_PREDICTION_STATE_END) and
876	(reg_UPDATE_PREDICTION_TABLE [i][x]._state != UPDATE_PREDICTION_STATE_EMPTY))
877	{
878	find = true; // find a not empty slot
879	reg_UPDATE_PREDICTION_TABLE [i][x]._state = UPDATE_PREDICTION_STATE_EVENT;
880	reg_UPDATE_PREDICTION_TABLE [i][x]._retire_ok = false;
881	update = x;
882	}
883
884	if (reg_UPDATE_PREDICTION_TABLE [i][x]._state != UPDATE_PREDICTION_STATE_EMPTY)
885	top = x+1;
886	}
887
888	top = top%_param->_size_upt_queue[i];
889
890	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * find : %d",find);
891	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top);
892
893	// Test if have update slot
894	if (find)
895	{
896	// TODO : special case : event is an exception on branch, also depth is not valid
897	reg_UPT_TOP [i] = top; // depth is again valid
898	reg_UPT_TOP_EVENT [i] = top;
899
900	if (bottom == reg_UPT_TOP [i])
901	reg_UPT_EMPTY [i] = true;
902	}
903	reg_UPT_UPDATE [i] = update;
904
905	// new state :
906	// * test if ufpt is empty
907	// * ok : flush upft and upt
908	// * ko : test if have previous flush upt
909	// * ok : nothing
910	// * ko : flush upt
911	reg_EVENT_VAL [i] = find;
912	reg_EVENT_IS_BRANCH [i] = false;
913	reg_EVENT_UPT_PTR [i] = top;
914	reg_EVENT_UPT_FULL [i] = (not empty and (bottom == reg_UPT_TOP [i]));
915	reg_EVENT_DEPTH [i] = top;
916	// reg_EVENT_ADDRESS_SRC [i] = address_src; // delay_slot is compute in I_State
917	// reg_EVENT_ADDRESS_DEST_VAL[i] = good_take;
918	// reg_EVENT_ADDRESS_DEST [i] = good_addr;
919
920	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_BOTTOM : %d",reg_UPT_BOTTOM [i]);
921	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP : %d",reg_UPT_TOP [i]);
922	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EMPTY : %d",reg_UPT_EMPTY [i]);
923
924	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_VAL : %d",reg_EVENT_VAL [i]);
925	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_PTR : %d",reg_EVENT_UPT_PTR [i]);
926	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_FULL : %d",reg_EVENT_UPT_FULL [i]);
927	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]);
928	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_UPDATE : %d",reg_UFPT_NB_UPDATE [i]);
929
930	if ( (reg_UFPT_NB_NEED_UPDATE [i] > 0) or
931	(reg_UFPT_NB_UPDATE [i] > 0))
932	{
933	if (find)
934	{
935	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT (event - find)",i);
936	reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT;
937	}
938	else
939	{
940	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UFPT (event - not find)",i);
941	// reg_EVENT_VAL [i] = false;
942
943	reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UFPT;
944	}
945	}
946	else
947	{
948	if (find)
949	{
950	// have ras prediction ?
951	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UPT (event - find)",i);
952
953	reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UPT;
954	}
955	else
956	{
957	// special case : nothing
958	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UPT (event - not find)",i);
959
960	// reg_EVENT_VAL [i] = false;
961
962	reg_EVENT_STATE [i] = EVENT_STATE_OK;
963	}
964	}
965
966	// else no update
967
968	// Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_EVENT_DEPTH [i]):0;
969	// uint32_t top = reg_UPT_TOP [i];
970	// uint32_t bottom = reg_UPT_BOTTOM [i];
971	// uint32_t new_update = ((top==0)?_param->_size_upt_queue[i]:top)-1;
972	// // bool empty = reg_UPT_EMPTY [i];
973
974	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top);
975	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth);
976	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * new_update : %d",new_update);
977
978	// event_state_t event_state = reg_EVENT_STATE [i];
979	// bool previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or
980	// (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or
981	// (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or
982	// (event_state == EVENT_STATE_EVENT_FLUSH_UPT));
983
984	// bool find = false; // have slot to update ???
985	// Tdepth_t depth_new = depth;
986
987	// // flush all slot, because this event is in head of rob
988	// for (uint32_t j=(depth+1)%_param->_size_upt_queue[i];
989	// //uint32_t j=bottom;
990	// j!=top;
991	// j=(j+1)%_param->_size_upt_queue[i])
992	// if ((reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_END) and
993	// (reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_EMPTY))
994	// {
995	// find = true;
996	// reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EVENT;
997	// reg_UPDATE_PREDICTION_TABLE [i][j]._retire_ok = false;
998	// }
999	// else
1000	// if (not find) // while state == end or empty
1001	// depth_new ++;
1002
1003	// if ((reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_END) and
1004	// (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_EMPTY))
1005	// {
1006	// find = true;
1007	// reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_EVENT;
1008	// reg_UPDATE_PREDICTION_TABLE [i][depth]._retire_ok = false;
1009
1010	// }
1011	// else
1012	// // while state == end or empty
1013	// depth = (depth_new+1)%_param->_size_upt_queue[i];
1014
1015	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * find : %d",find);
1016	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth_new : %d",depth_new);
1017
1018	// // Test if have update slot
1019	// if (find)
1020	// {
1021	// // // flush all slot after the event
1022	// // for (uint32_t j=(depth+1)%_param->_size_upt_queue[i];
1023	// // j!=top;
1024	// // j=(j+1)%_param->_size_upt_queue[i])
1025	// // reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EVENT;
1026
1027	// // reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_EVENT;
1028
1029	// // reg_UPT_BOTTOM [i];
1030	// // TODO : special case : event is an exception on branch, also depth is not valid
1031	// reg_UPT_TOP [i] = depth; // depth is again valid
1032	// reg_UPT_TOP_EVENT [i] = top;
1033
1034	// if (bottom == reg_UPT_TOP [i])
1035	// reg_UPT_EMPTY [i] = true;
1036	// }
1037
1038	// bool full = ((depth == top) and (top == bottom) and not reg_UPT_EMPTY [i]);
1039	// bool update_ras = find and ((top != depth) or full);
1040
1041	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update_ras : %d",update_ras);
1042
1043	// if (not previous_update_ras and update_ras)
1044	// reg_UPT_UPDATE [i] = new_update;
1045
1046	// // new state :
1047	// // * test if ufpt is empty
1048	// // * ok : flush upft and upt
1049	// // * ko : test if have previous flush upt
1050	// // * ok : nothing
1051	// // * ko : flush upt
1052	// reg_EVENT_VAL [i] = update_ras;
1053	// reg_EVENT_UPT_PTR [i] = depth;
1054
1055	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]);
1056	// // if (reg_UFPT_NB_NEED_UPDATE [i] > 0)
1057	// if ( (reg_UFPT_NB_NEED_UPDATE [i] > 0) or
1058	// (reg_UFPT_NB_UPDATE [i] > 0))
1059	// {
1060	// if (update_ras)
1061	// {
1062	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT (branch_complete - miss)",i);
1063	// reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT;
1064	// }
1065	// else
1066	// {
1067	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UFPT (branch_complete - miss)",i);
1068	// // reg_EVENT_VAL [i] = false;
1069
1070	// reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UFPT;
1071	// }
1072	// }
1073	// else
1074	// {
1075	// // if (not previous_update_ras)
1076	// if (update_ras)
1077	// {
1078	// // have ras prediction ?
1079	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UPT (branch_complete - miss)",i);
1080
1081	// reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UPT;
1082	// }
1083	// else
1084	// {
1085	// // special case : nothing
1086	// // reg_EVENT_VAL [i] = false;
1087
1088	// reg_EVENT_STATE [i] = EVENT_STATE_OK;
1089	// }
1090	// }
1091
1092	// // else no update
1093
1094	// reg_EVENT_DEPTH [i] = depth;
1095	// // reg_EVENT_ADDRESS_SRC [i] = address_src; // delay_slot is compute in I_State
1096	// // reg_EVENT_ADDRESS_DEST_VAL[i] = good_take;
1097	// // reg_EVENT_ADDRESS_DEST [i] = good_addr;
1098
1099	break;
1100	}
1101	default :
1102	{
1103	// nothing
1104	break;
1105	}
1106	}
1107	}
1108
1109	// ===================================================================
1110	// =====[ FLUSH ]=====================================================
1111	// ===================================================================
1112
1113	for (uint32_t i=0; i<_param->_nb_context; ++i)
1114	{
1115	if (flush_UFPT [i])
1116	{
1117	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Flush Update Fetch Prediction Table");
1118	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",i);
1119	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]);
1120
1121	// It's to accelerate miss speculation
1122	if (reg_UFPT_NB_NEED_UPDATE [i] == 0)
1123	{
1124	// No entry need prediction, flush all entry -> Reset
1125	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j)
1126	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY;
1127	reg_UFPT_BOTTOM [i] = 0;
1128	reg_UFPT_TOP [i] = 0;
1129	// reg_UFPT_UPDATE [i];
1130	}
1131	else
1132	{
1133	uint32_t bottom = reg_UFPT_BOTTOM [i];
1134	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j)
1135	{
1136	uint32_t index = (bottom+j)%_param->_size_ufpt_queue[i];
1137	// EMPTY : no event
1138	// END : already update
1139	// EVENT : previous event
1140	if (reg_UPDATE_FETCH_PREDICTION_TABLE [i][index]._state == UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD)
1141	{
1142	reg_UFPT_UPDATE [i] = index;
1143	reg_UFPT_NB_UPDATE [i] ++;
1144	reg_UPDATE_FETCH_PREDICTION_TABLE [i][index]._state = UPDATE_FETCH_PREDICTION_STATE_EVENT;
1145	}
1146	}
1147
1148	// // TOP is next write slot : last slot is TOP-1
1149	// uint32_t top = reg_UFPT_TOP [i];
1150	// reg_UFPT_UPDATE [i] = ((top==0)?_param->_size_ufpt_queue[i]:top)-1;
1151
1152	// reg_UFPT_BOTTOM [i];
1153	// reg_UFPT_TOP [i];
1154	}
1155
1156	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (after ) : %d",reg_UFPT_UPDATE [i]);
1157
1158	}
1159	}
1160
1161	#ifdef STATISTICS
1162	if (usage_is_set(_usage,USE_STATISTICS))
1163	for (uint32_t i=0; i<_param->_nb_context; i++)
1164	{
1165	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; j++)
1166	if (reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state != UPDATE_FETCH_PREDICTION_STATE_EMPTY)
1167	(*_stat_ufpt_queue_nb_elt [i]) ++;
1168	for (uint32_t j=0; j<_param->_size_upt_queue[i]; j++)
1169	if (reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_EMPTY)
1170	(*_stat_upt_queue_nb_elt [i]) ++;
1171	}
1172	#endif
1173
1174	// ===================================================================
1175	// =====[ PRINT ]=====================================================
1176	// ===================================================================
1177
1178	#if (DEBUG >= DEBUG_TRACE)
1179	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Dump Update_Prediction_Table");
1180	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPDATE_PRIORITY : %d",reg_UPDATE_PRIORITY);
1181	for (uint32_t i=0; i<_param->_nb_context; i++)
1182	{
1183	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_IS_ACCURATE : %d",reg_IS_ACCURATE [i]);
1184	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_VAL : %d" ,reg_EVENT_VAL [i]);
1185	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_PTR : %d" ,reg_EVENT_UPT_PTR [i]);
1186	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_FULL : %d" ,reg_EVENT_UPT_FULL [i]);
1187	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_STATE : %s" ,toString(reg_EVENT_STATE [i]).c_str());
1188	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_IS_BRANCH : %d" ,reg_EVENT_IS_BRANCH [i]);
1189	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_DEPTH : %d" ,reg_EVENT_DEPTH [i]);
1190	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_SRC : %.8x (%.8x)",reg_EVENT_ADDRESS_SRC [i],reg_EVENT_ADDRESS_SRC [i]<<2);
1191	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_DEST_VAL: %d" ,reg_EVENT_ADDRESS_DEST_VAL[i]);
1192	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_DEST : %.8x (%.8x)",reg_EVENT_ADDRESS_DEST [i],reg_EVENT_ADDRESS_DEST [i]<<2);
1193
1194	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update_Fetch_Prediction_Table [%d]",i);
1195	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_BOTTOM : %d",reg_UFPT_BOTTOM [i]);
1196	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_TOP : %d",reg_UFPT_TOP [i]);
1197	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE : %d",reg_UFPT_UPDATE [i]);
1198	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]);
1199	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_UPDATE : %d",reg_UFPT_NB_UPDATE [i]);
1200	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; j++)
1201	log_printf(TRACE,Update_Prediction_Table,FUNCTION," [%d] %.4d, %.8x (%.8x) %.8x (%.8x), %.1d %.1d, %.8d %.8x (%.8x) %.4d - %s",
1202	j,
1203	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._condition,
1204	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_src,
1205	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_src<<2,
1206	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_dest,
1207	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_dest<<2,
1208	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._last_take,
1209	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._is_accurate,
1210	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._history,
1211	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_ras,
1212	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_ras<<2,
1213	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._index_ras,
1214	toString(reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state).c_str()
1215	);
1216
1217	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update_Prediction_Table [%d]",i);
1218	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_BOTTOM : %d",reg_UPT_BOTTOM [i]);
1219	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP : %d",reg_UPT_TOP [i]);
1220	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP_EVENT : %d",reg_UPT_TOP_EVENT [i]);
1221	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE : %d",reg_UPT_UPDATE [i]);
1222	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EMPTY : %d",reg_UPT_EMPTY [i]);
1223	for (uint32_t j=0; j<_param->_size_upt_queue[i]; j++)
1224	log_printf(TRACE,Update_Prediction_Table,FUNCTION," [%d] %.4d, %.8x (%.8x) %.8x (%.8x), %.1d %.1d %.1d, %.8d %.8x (%.8x) %.4d - %s",
1225	j,
1226	reg_UPDATE_PREDICTION_TABLE [i][j]._condition,
1227	reg_UPDATE_PREDICTION_TABLE [i][j]._address_src,
1228	reg_UPDATE_PREDICTION_TABLE [i][j]._address_src<<2,
1229	reg_UPDATE_PREDICTION_TABLE [i][j]._address_dest,
1230	reg_UPDATE_PREDICTION_TABLE [i][j]._address_dest<<2,
1231	reg_UPDATE_PREDICTION_TABLE [i][j]._last_take,
1232	reg_UPDATE_PREDICTION_TABLE [i][j]._good_take,
1233	reg_UPDATE_PREDICTION_TABLE [i][j]._is_accurate,
1234	reg_UPDATE_PREDICTION_TABLE [i][j]._history,
1235	reg_UPDATE_PREDICTION_TABLE [i][j]._address_ras,
1236	reg_UPDATE_PREDICTION_TABLE [i][j]._address_ras<<2,
1237	reg_UPDATE_PREDICTION_TABLE [i][j]._index_ras,
1238	toString(reg_UPDATE_PREDICTION_TABLE [i][j]._state).c_str()
1239	);
1240	}
1241	#endif
1242
1243	#ifdef DEBUG_TEST
1244	for (uint32_t i=0; i<_param->_nb_context; i++)
1245	{
1246	if (reg_UFPT_NB_NEED_UPDATE [i] > _param->_size_ufpt_queue[i])
1247	throw ERRORMORPHEO(FUNCTION,toString(_("reg_UFPT_NB_NEED_UPDATE [%d] (%d) is > at size_ufpt_queue (%d).\n"),i,reg_UFPT_NB_NEED_UPDATE [i],_param->_size_ufpt_queue[i]));
1248	if (reg_UFPT_NB_UPDATE [i] > _param->_size_ufpt_queue[i])
1249	throw ERRORMORPHEO(FUNCTION,toString(_("reg_UFPT_NB_UPDATE [%d] (%d) is > at size_ufpt_queue (%d).\n"),i,reg_UFPT_NB_UPDATE [i],_param->_size_ufpt_queue[i]));
1250	}
1251	#endif
1252
1253	}
1254
1255
1256	#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
1257	end_cycle ();
1258	#endif
1259
1260	log_end(Update_Prediction_Table,FUNCTION);
1261	};
1262
1263	}; // end namespace update_prediction_table
1264	}; // end namespace prediction_unit
1265	}; // end namespace front_end
1266	}; // end namespace multi_front_end
1267	}; // end namespace core
1268
1269	}; // end namespace behavioural
1270	}; // end namespace morpheo
1271	#endif

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