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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp @ 123

Last change on this file since 123 was 123, checked in by rosiere, 15 years ago
1) Fix performance 2) add auto generation to SPECINT2000 3) add reset in genMoore and genMealy
Property svn:keywords set to `Id`
File size: 70.1 KB

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1	#ifdef SYSTEMC
2	/*
3	* $Id: Update_Prediction_Table_transition.cpp 123 2009-06-08 20:43:30Z rosiere $
4	*
5	* [ Description ]
6	*
7	*/
8
9	#include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_front_end {
15	namespace front_end {
16	namespace prediction_unit {
17	namespace update_prediction_table {
18
19	#undef FUNCTION
20	#define FUNCTION "Update_Prediction_Table::transition"
21	void Update_Prediction_Table::transition (void)
22	{
23	log_begin(Update_Prediction_Table,FUNCTION);
24	log_function(Update_Prediction_Table,FUNCTION,_name.c_str());
25
26	if (PORT_READ(in_NRESET) == 0)
27	{
28	// Initialisation
29
30	reg_UPDATE_PRIORITY = 0;
31
32	// All pointer is set at 0
33	for (uint32_t i=0; i<_param->_nb_context; i++)
34	{
35	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j)
36	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY;
37	reg_UFPT_BOTTOM [i] = 0;
38	reg_UFPT_TOP [i] = 0;
39	reg_UFPT_UPDATE [i] = 0;
40	reg_UFPT_NB_NEED_UPDATE [i] = 0;
41	reg_UFPT_NB_UPDATE [i] = 0;
42
43	for (uint32_t j=0; j<_param->_size_upt_queue[i]; ++j)
44	reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EMPTY;
45	reg_UPT_BOTTOM [i] = 0;
46	reg_UPT_TOP [i] = 0;
47	reg_UPT_TOP_EVENT [i] = 0;
48	reg_UPT_UPDATE [i] = 0;
49	reg_UPT_EMPTY [i] = true;
50
51	reg_IS_ACCURATE [i] = true;
52
53	reg_UFPT_EVENT_STATE [i] = UFPT_EVENT_STATE_OK;
54	reg_UPT_EVENT_STATE [i] = UPT_EVENT_STATE_OK;
55
56	// reg_EVENT_VAL [i] = false;
57	// reg_EVENT_STATE [i] = EVENT_STATE_OK;
58	// reg_EVENT_IS_BRANCH [i] = true;
59	}
60	}
61	else
62	{
63	bool flush_UFPT [_param->_nb_context];
64	for (uint32_t i=0; i<_param->_nb_context; i++)
65	{
66	flush_UFPT [i] = false;
67	}
68
69	// ===================================================================
70	// =====[ GARBAGE COLLECTOR ]=========================================
71	// ===================================================================
72
73	// Each cycle, if the most lastest branch have update all prediction struction (state = end), free this slot
74	// * Update state -> new status is "empty"
75	// * Update pointer (bottom and accurate)
76	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * GARBAGE COLLECTOR (BEGIN)");
77	for (uint32_t i=0; i<_param->_nb_context; i++)
78	{
79	// -----------------------------
80	// UPDATE_FETCH_PREDICTION_TABLE
81	// -----------------------------
82	{
83	uint32_t bottom = reg_UFPT_BOTTOM [i];
84	bool end = (reg_UPDATE_FETCH_PREDICTION_TABLE [i][bottom]._state == UPDATE_FETCH_PREDICTION_STATE_END);
85
86	// Test if bottom slot can be remove
87	if (end)
88	{
89	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d]",i,bottom);
90	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state = UPDATE_FETCH_PREDICTION_STATE_EMPTY",i,bottom);
91
92	// Free slot
93	reg_UPDATE_FETCH_PREDICTION_TABLE [i][bottom]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY;
94	// Update pointer
95	bottom = (bottom+1)%_param->_size_ufpt_queue[i];
96
97	reg_UFPT_BOTTOM [i] = bottom;
98	}
99	}
100
101	// -----------------------
102	// UPDATE_PREDICTION_TABLE
103	// -----------------------
104	{
105	uint32_t bottom = reg_UPT_BOTTOM [i];
106
107	// if (reg_UPT_EVENT_STATE [i] == UPT_EVENT_STATE_OK)
108	{
109	bool end = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END);
110
111	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_BOTTOM (before) : %d",bottom);
112	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state is STATE_END : %d",end);
113
114	if (end)
115	{
116	#if defined(DEBUG) and defined(DEBUG_Update_Prediction_Table) and (DEBUG_Update_Prediction_Table == true)
117	if (reg_UPDATE_PREDICTION_TABLE [i][bottom]._retire_ok)
118	{
119	uint32_t num_thread = _param->_translate_num_context_to_num_thread [i];
120	branchement_log_file [num_thread]
121	<< std::hex
122	<< "0x" << reg_UPDATE_PREDICTION_TABLE [i][bottom]._address_src << " "
123	<< "0x" << reg_UPDATE_PREDICTION_TABLE [i][bottom]._address_dest << " "
124	<< std::dec
125	<< reg_UPDATE_PREDICTION_TABLE [i][bottom]._good_take << " - "
126	<< "[" << simulation_cycle() << "] " << " "
127	<< reg_UPDATE_PREDICTION_TABLE [i][bottom]._miss_prediction << " "
128	<< reg_UPDATE_PREDICTION_TABLE [i][bottom]._ifetch_prediction << " "
129	<< "(" << (uint32_t)reg_UPDATE_PREDICTION_TABLE [i][bottom]._condition << ")"
130	<< std::endl;
131	}
132	#endif
133
134	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d]",i,bottom);
135	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d]._state = UPDATE_PREDICTION_STATE_EMPTY",i,bottom);
136	// Free slot
137	reg_UPDATE_PREDICTION_TABLE [i][bottom]._state = UPDATE_PREDICTION_STATE_EMPTY;
138
139	// Update pointer
140	reg_UPT_BOTTOM [i] = (bottom+1)%_param->_size_upt_queue[i];
141
142	// Free a slot, test if bottom pointer overtake the top pointer
143	if (reg_UPT_BOTTOM [i] == reg_UPT_TOP [i])
144	reg_UPT_EMPTY [i] = true; // free a slot
145
146	reg_EVENT_UPT_FULL [i] = false;
147	}
148
149	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_BOTTOM (after ) : %d",reg_UPT_BOTTOM [i]);
150	}
151	}
152	}
153
154	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * GARBAGE COLLECTOR (END)");
155
156	// ===================================================================
157	// =====[ PREDICT ]===================================================
158	// ===================================================================
159
160	// An ifetch_unit compute next cycle and have an branch : predict_val is set
161	// * Alloc new entry -> new status is "wait decod"
162	// * Save input (to restore in miss or error)
163	// * Update pointer
164
165	for (uint32_t i=0; i<_param->_nb_inst_predict; i++)
166	// Test if have a transaction
167	if (PORT_READ(in_PREDICT_VAL[i]) and internal_PREDICT_ACK [i])
168	{
169	// get transaction information
170	Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_PREDICT_CONTEXT_ID [i]):0;
171	uint32_t top = internal_PREDICT_UPDATE_PREDICTION_ID [i];
172	Tbranch_condition_t condition = PORT_READ(in_PREDICT_BTB_CONDITION [i]);
173	bool is_accurate = (_param->_always_accurate_predict or
174	(_param->_can_accurate_predict and PORT_READ(in_PREDICT_BTB_IS_ACCURATE [i])));
175
176
177	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * PREDICT[%d] - Accepted",i);
178	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);
179	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top);
180	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * condition : %d",condition);
181	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * is_accurate : %d",is_accurate);
182
183	#ifdef DEBUG_TEST
184	if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._state != UPDATE_FETCH_PREDICTION_STATE_EMPTY)
185	throw ERRORMORPHEO(FUNCTION,_("Predict : invalid state."));
186	#endif
187
188	// Ifetch unit have fetch an instruction bundle with a branchement.
189	// Insert in UFPT
190	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD (predict)",context,top);
191	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._state = UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD;
192
193	// Write information
194	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._condition = condition;
195	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_src = PORT_READ(in_PREDICT_BTB_ADDRESS_SRC [i]);
196	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_dest = PORT_READ(in_PREDICT_BTB_ADDRESS_DEST [i]);
197	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._last_take = PORT_READ(in_PREDICT_BTB_LAST_TAKE [i]);
198	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._is_accurate = is_accurate;
199	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._history = (_param->_have_port_history)?PORT_READ(in_PREDICT_DIR_HISTORY [i]):0;
200	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_ras = PORT_READ(in_PREDICT_RAS_ADDRESS [i]);
201	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._index_ras = PORT_READ(in_PREDICT_RAS_INDEX [i]);
202
203	// Update pointer
204	reg_UFPT_TOP [context] = (top+1)%_param->_size_ufpt_queue [context];
205
206	// Test if this branchement need update
207	if (need_update(condition))
208	{
209	reg_UFPT_NB_NEED_UPDATE [context] ++;
210	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE (after) : %d",reg_UFPT_NB_NEED_UPDATE [context]);
211	}
212	}
213
214	// ===================================================================
215	// =====[ DECOD ]=====================================================
216	// ===================================================================
217
218
219	// An decod is detected by decod stage
220	// 1) Hit prediction : The instruction bundle have a branch predicted in ifetch stage and it is this branch
221	// * Update state, wait_decod -> wait_end
222	// * Pop ufpt -> push upt
223	// * Update accurate register : if the predict stage have tagged this branch as not accurate, stop decod
224	// 2) Miss : The instruction bundle have a branch but it is not predicted
225	// * Flush ufpt
226	// * decod information is write in upt
227
228	for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
229	// Test if have a decod transaction
230	if (PORT_READ(in_DECOD_VAL[i]) and internal_DECOD_ACK [i])
231	{
232	// Read information
233	Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0;
234	Tcontrol_t miss_ifetch = PORT_READ(in_DECOD_MISS_IFETCH [i]);
235	Tcontrol_t miss_decod = PORT_READ(in_DECOD_MISS_DECOD [i]);
236	uint32_t upt_ptr_write = internal_DECOD_UPT_PTR_WRITE [i];
237	uint32_t top_next = (upt_ptr_write+1)%_param->_size_upt_queue [context];
238	Tbranch_condition_t condition ;
239	Tcontrol_t is_accurate;
240	Taddress_t address_src = PORT_READ(in_DECOD_BTB_ADDRESS_SRC [i]);
241	Taddress_t address_dest = PORT_READ(in_DECOD_BTB_ADDRESS_DEST [i]);
242	Tcontrol_t direction = PORT_READ(in_DECOD_BTB_LAST_TAKE [i]);
243
244	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * DECOD[%d] - Accepted",i);
245	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);
246	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_ifetch : %d",miss_ifetch);
247	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_decod : %d",miss_decod);
248	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * upt_ptr_write : %d",upt_ptr_write);
249
250	// In decod step, two miss type :
251	// miss_ifetch = branch is previously predict (predict interface), but it's not the good
252	// miss_decod = branch was not detected
253	if (not (miss_ifetch or miss_decod))
254	{
255	// Normal case : branch is previous predicted, change state of branch
256
257	// Read ufpt_ptr (send in predic step)
258	uint32_t ufpt_ptr_read = (_param->_have_port_depth)?PORT_READ(in_DECOD_UPDATE_PREDICTION_ID [i]):0;
259
260	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * ufpt_ptr_read : %d",ufpt_ptr_read);
261
262	#ifdef DEBUG_TEST
263	if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._state != UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD)
264	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid ufpt state."));
265	#endif
266	// Change state
267	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_END (decod - hit)",context,ufpt_ptr_read);
268	reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._state = UPDATE_FETCH_PREDICTION_STATE_END;
269
270	// Push upt (from Pop ufpt)
271	condition = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._condition;
272	is_accurate = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._is_accurate;
273
274	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._condition = condition;
275	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_src = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_src ;
276	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_dest = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_dest;
277	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._last_take = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._last_take ;
278	// reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._good_take;
279	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._is_accurate = is_accurate;
280	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._history = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._history ;
281	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_ras = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_ras ;
282	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._index_ras = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._index_ras ;
283	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._ifetch_prediction = true ; // prediction from ifetch
284
285	// Update pointer (now, this instruction is not in ufpt)
286	if (need_update(condition))
287	{
288	reg_UFPT_NB_NEED_UPDATE [context] --;
289	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE (after) : %d",reg_UFPT_NB_NEED_UPDATE [context]);
290	}
291	}
292	else
293	{
294	// Have a miss !!!
295	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss !!!");
296
297	condition = PORT_READ(in_DECOD_BTB_CONDITION [i]);
298	is_accurate = (_param->_always_accurate_decod or
299	(_param->_can_accurate_decod and PORT_READ(in_DECOD_IS_ACCURATE [i])));
300
301	// if can_continue, don't wait the end of all instruction
302	// (can_continue = not miss_commit and the destination is accurate (know))
303	Tcontrol_t can_continue = is_accurate;
304
305	#ifdef DEBUG_TEST
306	if (reg_UPT_EVENT_STATE [context] != UPT_EVENT_STATE_OK)
307	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid upt event state."));
308	if (reg_UFPT_EVENT_STATE [context] != UFPT_EVENT_STATE_OK)
309	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid ufpt event state."));
310	#endif
311
312	// miss_ifetch -> need flush ufpt
313	// miss_decod -> not necessary
314	// if can_continue (destination is know) and direction is not take (instruction in ifetch_queue can be valid)
315	bool flush_ufpt = (not (can_continue and not direction and not miss_ifetch));
316
317	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * can_continue: %d",can_continue);
318	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * direction : %d",direction );
319	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_ifetch : %d",miss_ifetch );
320	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * flush_ufpt: %d",flush_ufpt );
321
322	// Test if can continue without flushing the ufpt (and ifetch_queue)
323	if (flush_ufpt)
324	{
325	// // Optimisation : Test if ufpt have entry that need update prediction struction (as Return Address Stack)
326	// if (reg_UFPT_NB_NEED_UPDATE [context] == 0)
327	// {
328	// // Change state
329	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT_EVENT [%d] <- UPT_EVENT_STATE_KO_COMMIT_UPDATE_CONTEXT (decod - miss - no flush ufpt)",context);
330	// reg_UPT_EVENT_STATE [context] = UPT_EVENT_STATE_KO_COMMIT_UPDATE_CONTEXT;
331
332	// // @@@
333	// // // Have an actual event ?
334	// // if (not reg_EVENT_VAL [context])
335	// // reg_EVENT_UPT_PTR [context] = upt_ptr_write;
336	// }
337	// else
338	// {
339	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- UPT_EVENT_STATE_KO_MISS_WAIT_UFPT (decod - miss - flush ufpt)",context);
340	// // just wait ufpt, don't flush upt
341	// reg_UPT_EVENT_STATE [context] = UPT_EVENT_STATE_KO_MISS_WAIT_UFPT;
342	// }
343
344	reg_UPT_EVENT_STATE [context] = UPT_EVENT_STATE_KO_DECODE_UPDATE_CONTEXT;
345	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT_EVENT_STATE [%d] <- %s (decod, miss)",context,toString(reg_UPT_EVENT_STATE [context]).c_str());
346
347	// Need Flush UPFT
348	flush_UFPT [context] = true;
349
350	// Write information
351	// reg_EVENT_IS_BRANCH [context] = true;
352	reg_EVENT_DEPTH [context] = upt_ptr_write;
353	reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State
354	reg_EVENT_ADDRESS_DEST_VAL[context] = direction;
355	reg_EVENT_ADDRESS_DEST [context] = address_dest;
356	reg_EVENT_CAN_CONTINUE [context] = can_continue;
357	}
358	// else can continue
359
360	// Push upt (from decod interface)
361	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._condition = condition;
362	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_src = address_src ;
363	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_dest = address_dest;
364	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._last_take = direction ;
365	// reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._good_take;
366	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._is_accurate = is_accurate;
367	// reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._history = ; // static prediction
368	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_ras = PORT_READ(in_DECOD_RAS_ADDRESS [i]);
369	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._index_ras = PORT_READ(in_DECOD_RAS_INDEX [i]);
370	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._ifetch_prediction = false; // static prediction
371	}
372
373	// In all case !!!
374	#ifdef DEBUG_TEST
375	if (reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._state != UPDATE_PREDICTION_STATE_EMPTY)
376	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid upt state."));
377	#endif
378
379	// Change state
380	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_WAIT_END (decod - hit)",context,upt_ptr_write);
381	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._state = UPDATE_PREDICTION_STATE_WAIT_END;
382	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._retire_ok = false;
383	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._miss_commit = false;
384
385	// Write new accurate
386	#ifdef DEBUG_TEST
387	if (not reg_IS_ACCURATE [context] and not is_accurate)
388	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid accurate flag."));
389	#endif
390
391	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * is_accurate : %d",is_accurate);
392
393	reg_IS_ACCURATE [context] = is_accurate;
394
395	// Update pointer
396	reg_UPT_TOP [context] = top_next;
397	reg_UPT_EMPTY [context] = false; // new instruction
398	}
399
400	// ===================================================================
401	// =====[ UPDATE ]====================================================
402	// ===================================================================
403	{
404	bool can_continue [_param->_nb_context];
405	for (uint32_t i=0; i<_param->_nb_context; ++i)
406	can_continue [i] = true;
407
408	// For each updated instruction
409	for (uint32_t i=0; i<_param->_nb_inst_update; i++)
410	{
411	Tcontext_t context = internal_UPDATE_CONTEXT_ID [i];
412
413	// Test if transaction
414	// (an val_with_out is an update and don't need update prediction structure
415	if ((internal_UPDATE_VAL[i] and PORT_READ(in_UPDATE_ACK [i])) or
416	(internal_UPDATE_VAL_WITHOUT_ACK [i] and can_continue [context]))
417	{
418	Tdepth_t depth = internal_UPDATE_DEPTH [i];
419
420	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPDATE[%d] - Accepted",i);
421	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);
422	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth);
423
424	upt_event_state_t upt_event_state = reg_UPT_EVENT_STATE [context];
425
426	// One interface to two source :
427	// * from ufpt -> newest prediction
428	// * from upt -> oldest prediction
429	if (internal_UPDATE_FROM_UFPT [i])
430	{
431	// if free a slot, also all queue is updated
432	// Last slot ?
433	if ((--reg_UFPT_NB_UPDATE [context])==0)
434	{
435	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT_EVENT [%d] <- UFPT_EVENT_STATE_OK (update - end flush ufpt)",context);
436	reg_UFPT_EVENT_STATE [context] = UFPT_EVENT_STATE_OK;
437	reg_UFPT_NB_NEED_UPDATE [context] = 0;
438
439	// // Test upt event to change state
440	// // test if upt wait ufpt
441	// switch (upt_event_state)
442	// {
443	// // this case when don't need flush upt (miss decod and can continue)
444	// case UPT_EVENT_STATE_KO_MISS_WAIT_UFPT : upt_event_state = UPT_EVENT_STATE_KO_COMMIT_UPDATE_CONTEXT; break;
445	// case UPT_EVENT_STATE_KO_EVENT_WAIT_UFPT : upt_event_state = UPT_EVENT_STATE_OK ; break;
446	// default : break;
447	// }
448
449	// reg_UPT_EVENT_STATE [context] = upt_event_state;
450	}
451
452	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Fetch Prediction Table");
453
454	// Change state
455	#ifdef DEBUG_TEST
456	if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state != UPDATE_FETCH_PREDICTION_STATE_EVENT)
457	throw ERRORMORPHEO(FUNCTION,_("Update : invalid ufpt state."));
458	#endif
459
460	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_END (update)",context,depth);
461
462	reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state = UPDATE_FETCH_PREDICTION_STATE_END;
463
464	// Update pointer
465	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (before) : %d",reg_UFPT_UPDATE [context]);
466	reg_UFPT_UPDATE [context] = ((depth==0)?_param->_size_ufpt_queue[context]:depth)-1;
467	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (after ) : %d",reg_UFPT_UPDATE [context]);
468	}
469	else
470	{
471	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Prediction Table");
472	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE (before) : %d",reg_UPT_UPDATE [context]);
473	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EVENT_STATE : %s",toString(upt_event_state).c_str());
474
475	// Change state
476	#ifdef DEBUG_TEST
477	if (internal_UPDATE_RAS [i])
478	{
479	if ((reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_EVENT) and
480	(reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_KO ) )
481	throw ERRORMORPHEO(FUNCTION,_("Update : invalid upt state."));
482	}
483	else
484	{
485	if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_OK )
486	throw ERRORMORPHEO(FUNCTION,_("Update : invalid upt state."));
487	}
488	#endif
489
490	#ifdef STATISTICS
491	Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition;
492	#endif
493	bool ok = (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_OK);
494	bool ko = (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_KO);
495
496	// Test if branch is valid (prediction can be incorrect)
497	if (ok or ko)
498	{
499	reg_UPDATE_PREDICTION_TABLE [context][depth]._retire_ok = true;
500	reg_UPDATE_PREDICTION_TABLE [context][depth]._miss_prediction = ko;
501
502	#ifdef STATISTICS
503	if (usage_is_set(_usage,USE_STATISTICS))
504	{
505	if (reg_UPDATE_PREDICTION_TABLE [context][depth]._ifetch_prediction)
506	(*_stat_nb_branch_ifetch_prediction [context])++;
507	if (reg_UPDATE_PREDICTION_TABLE [context][depth]._is_accurate)
508	(*_stat_nb_branch_accurate [context])++;
509	}
510	#endif
511	}
512
513	// Have an update, test the state to transiste to the good state
514	if (ko)
515	{
516	// Ko
517	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END_KO (update)",context,depth);
518
519	// Wait update of context_state
520	reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_KO;
521
522	reg_EVENT_UPT_PTR [context] = depth;
523
524	#ifdef STATISTICS
525	if (usage_is_set(_usage,USE_STATISTICS))
526	(*_stat_nb_branch_miss [context][condition])++;
527	#endif
528	}
529	else
530	{
531	// ok or event
532
533	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END (update)",context,depth);
534	reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END;
535
536	#ifdef STATISTICS
537	if (usage_is_set(_usage,USE_STATISTICS))
538	{
539	if (ok)
540	(*_stat_nb_branch_hit [context][condition]) ++;
541	else
542	(*_stat_nb_branch_unused [context]) ++;
543	}
544	#endif
545	}
546
547	// Test if freeing the branch with no accurate ?
548	if ((reg_UPDATE_PREDICTION_TABLE [context][depth]._is_accurate == false) and not ko)
549	reg_IS_ACCURATE [context] = true;
550
551	// Update pointer
552	// * if update RAS : update pointer is decreaste until it equal at top pointer
553	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * internal_UPDATE_RAS [%d] : %d",i,internal_UPDATE_RAS [i]);
554
555	if (internal_UPDATE_RAS [i])
556	{
557	// if end_event, restart too bottom, else decrease pointer
558	bool end_event = (reg_UPT_UPDATE [context] == reg_UPT_TOP [context]);
559
560	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * end_event : %d",end_event);
561	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * bottom : %d",reg_UPT_BOTTOM[context]);
562
563	if (end_event)
564	{
565	reg_UPT_UPDATE [context] = (end_event)?reg_UPT_BOTTOM[context]:(((depth==0)?_param->_size_upt_queue[context]:depth)-1);
566	// reg_UPT_UPDATE [context] = reg_UPT_BOTTOM[context];
567
568	switch (upt_event_state)
569	{
570	// this case when don't need flush upt (miss decod and can continue)
571	case UPT_EVENT_STATE_KO_MISS_FLUSH_UPT : upt_event_state = UPT_EVENT_STATE_KO_COMMIT_UPDATE_CONTEXT; break;
572	case UPT_EVENT_STATE_KO_EVENT_FLUSH_UPT :
573	{
574	upt_event_state = UPT_EVENT_STATE_OK;
575	reg_UPT_TOP [context] = reg_UPT_TOP_EVENT [context];
576	reg_UPT_UPDATE [context] = reg_UPT_TOP_EVENT [context];
577
578	break;
579	}
580	default : break;
581	}
582
583	}
584	else
585	{
586	// else, decrease update pointer
587	reg_UPT_UPDATE [context] = (((depth==0)?_param->_size_upt_queue[context]:depth)-1);
588	}
589	}
590	else
591	{
592	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * next update");
593
594	// increase pointer
595	reg_UPT_UPDATE [context] = (depth+1)%_param->_size_upt_queue[context];
596	}
597
598	// special case :
599	if ((upt_event_state == UPT_EVENT_STATE_KO_COMMIT_WAIT_END_UPDATE) and
600	(reg_UPT_UPDATE [context] == reg_EVENT_UPT_PTR [context]))
601	{
602	reg_UPT_TOP [context] = reg_UPT_TOP_EVENT [context];
603	reg_UPT_UPDATE [context] = reg_UPT_TOP_EVENT [context];
604	reg_IS_ACCURATE [context] = true;
605
606	upt_event_state = UPT_EVENT_STATE_OK;
607	}
608
609	reg_UPT_EVENT_STATE [context] = upt_event_state;
610
611	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE (after ) : %d",reg_UPT_UPDATE[context]);
612	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EVENT_STATE : %s",toString(reg_UPT_EVENT_STATE [context]).c_str());
613	}
614	}
615	else
616	can_continue [context] = false;
617	}
618
619	// Round robin
620	reg_UPDATE_PRIORITY = (reg_UPDATE_PRIORITY+1)%_param->_nb_context;
621	}
622
623	// ===================================================================
624	// =====[ BRANCH_COMPLETE ]===========================================
625	// ===================================================================
626
627	// The branch is complete
628	// * Hit prediction :
629	// * update status
630	// * Miss prediction :
631	{
632	bool branch_complete_miss [_param->_nb_context];
633	for (uint32_t i=0; i<_param->_nb_context; ++i)
634	branch_complete_miss [i] = false;
635
636	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
637	if (PORT_READ(in_BRANCH_COMPLETE_VAL[i]) and internal_BRANCH_COMPLETE_ACK [i])
638	{
639	// Read information
640	Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0;
641	Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0;
642	Tcontrol_t miss = internal_BRANCH_COMPLETE_MISS_PREDICTION [i];
643	Tcontrol_t good_take = internal_BRANCH_COMPLETE_TAKE [i];
644	Taddress_t good_addr = internal_BRANCH_COMPLETE_ADDRESS_DEST [i];
645
646	upt_event_state_t upt_event_state = reg_UPT_EVENT_STATE [context];
647
648	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_COMPLETE[%d] - Accepted",i);
649	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);
650	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth);
651	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss);
652	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EVENT_STATE : %s",toString(upt_event_state).c_str());
653
654	// Test if the completed branch is a speculation miss
655	if (miss)
656	{
657	// special case : two branch complete on the same context.
658	// when the re order keep the order, the branch complete j is most speculative that the branch comple i if i < j
659	if (not branch_complete_miss [context])
660	{
661	branch_complete_miss [context] = true;
662	// Flush UPT
663	// get information
664	uint32_t top = reg_UPT_TOP [context];
665	uint32_t new_update = ((top==0)?_param->_size_upt_queue[context]:top)-1;
666
667	Taddress_t address_src = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src;
668	upt_state_t top_state = reg_UPDATE_PREDICTION_TABLE [context][top]._state;
669
670	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * upt_event_state : %s",toString(upt_event_state).c_str());
671	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top_state : %s",toString(top_state).c_str());
672
673	bool previous_ufpt_event = (reg_UFPT_EVENT_STATE [i] == UFPT_EVENT_STATE_KO_FLUSH);
674
675
676	bool previous_upt_event = (false
677	or (upt_event_state == UPT_EVENT_STATE_KO_MISS_WAIT_UFPT )
678	or (upt_event_state == UPT_EVENT_STATE_KO_MISS_FLUSH_UPT )
679	or (upt_event_state == UPT_EVENT_STATE_KO_EVENT_WAIT_UFPT)
680	or (upt_event_state == UPT_EVENT_STATE_KO_EVENT_FLUSH_UPT)
681	or (upt_event_state == UPT_EVENT_STATE_KO_COMMIT_WAIT_END_UPDATE)
682	or (top_state == UPDATE_PREDICTION_STATE_END_KO )
683	or (top_state == UPDATE_PREDICTION_STATE_KO )
684	);
685
686	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top);
687	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * new_update : %d",new_update);
688	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * previous_upt_event : %d",previous_upt_event);
689	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * previous_ufpt_event : %d",previous_ufpt_event);
690	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE : %d",reg_UPT_UPDATE [context]);
691
692	// Have a miss !!!
693	// Flush UPFT
694	flush_UFPT [context] \|= not previous_ufpt_event;
695
696	// Test if the entry wait the branchment (else, they have a previous event)
697	if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_WAIT_END)
698	{
699	// All instruction between the instruction and the top is disable
700	for (uint32_t j=(depth+1)%_param->_size_upt_queue[context];
701	j!=top;
702	j=(j+1)%_param->_size_upt_queue[context])
703	{
704	reg_UPDATE_PREDICTION_TABLE [context][j]._state = UPDATE_PREDICTION_STATE_EVENT;
705	reg_UPDATE_PREDICTION_TABLE [context][j]._retire_ok = false; // event
706	}
707
708	// New top
709	reg_UPT_TOP [context] = depth;
710
711	if (not previous_upt_event)
712	{
713	reg_UPT_TOP_EVENT [context] = top;
714	reg_UPT_UPDATE [context] = new_update;
715	}
716	else
717	{
718	// Have event. Top index this slot
719	reg_UPDATE_PREDICTION_TABLE [context][top]._retire_ok = false;
720
721	switch (top_state)
722	{
723	case UPDATE_PREDICTION_STATE_END_KO :
724	case UPDATE_PREDICTION_STATE_END :
725	{
726	// Have already update predictor
727	reg_UPDATE_PREDICTION_TABLE [context][top]._state = UPDATE_PREDICTION_STATE_END;
728	reg_UPT_UPDATE [context] = new_update;
729	break;
730	}
731	case UPDATE_PREDICTION_STATE_KO :
732	{
733	// Doesn't have update predictor
734	reg_UPDATE_PREDICTION_TABLE [context][top]._state = UPDATE_PREDICTION_STATE_EVENT;
735	break;
736	}
737	default :
738	{
739	// reg_UPDATE_PREDICTION_TABLE [context][top]._state = UPDATE_PREDICTION_STATE_EVENT;
740	// break;
741
742	#ifdef DEBUG_TEST
743	throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state."));
744	#endif
745	}
746	}
747	}
748
749	if (reg_UPT_BOTTOM [context] == reg_UPT_TOP [context])
750	reg_UPT_EMPTY [context] = true;
751
752	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_KO (branch_complete, ifetch hit)",context,depth);
753	reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_KO;
754
755	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE [%d] : %d",context,reg_UFPT_NB_NEED_UPDATE [context]);
756
757	// if ( (reg_UFPT_NB_NEED_UPDATE [context] > 0) or
758	// (reg_UFPT_NB_UPDATE [context] > 0))
759	// {
760	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT (branch_complete - miss)",context);
761	// reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT;
762	// }
763	// else
764	// {
765	// // if (not previous_update_ras)
766	// {
767	// // have ras prediction ?
768	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UPT (branch_complete - miss)",context);
769
770	// reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UPT;
771
772	// }
773	// }
774
775	reg_UPT_EVENT_STATE [context] = UPT_EVENT_STATE_KO_MISS_FLUSH_UPT;
776	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT_EVENT_STATE [%d] <- %s (branch_complete, ifetch hit)",context,toString(reg_UPT_EVENT_STATE [context]).c_str());
777
778	// reg_EVENT_SOURCE [context] = EVENT_SOURCE_UPT;
779
780	// else no update
781
782	// reg_EVENT_IS_BRANCH [context] = true;
783	reg_EVENT_DEPTH [context] = depth;
784	reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State
785	reg_EVENT_ADDRESS_DEST_VAL[context] = good_take;
786	reg_EVENT_ADDRESS_DEST [context] = good_addr;
787	reg_EVENT_CAN_CONTINUE [context] = false;
788
789	}
790
791	reg_UPDATE_PREDICTION_TABLE [context][depth]._miss_commit = true;
792	}
793	}
794	else
795	{
796	// Hit case
797
798	// #ifdef DEBUG_TEST
799	// if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END)
800	// throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state."));
801	// #endif
802
803	// In same cycle, can have a previous branch_complete
804	if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_WAIT_END)
805	{
806	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_OK (branch_complete, ifetch hit)",context,depth);
807	reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_OK;
808	}
809	}
810
811	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EVENT_STATE : %s",toString(reg_UPT_EVENT_STATE [context]).c_str());
812
813	// In all case : update good_take
814	reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take = good_take;
815
816	// Write address_dest if need read register
817	Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition;
818
819	if ((condition == BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK) or
820	(condition == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK ) or
821	(condition == BRANCH_CONDITION_READ_STACK ) )
822	reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest = good_addr;
823	}
824	}
825
826	// ===================================================================
827	// =====[ BRANCH_EVENT ]==============================================
828	// ===================================================================
829	for (uint32_t i=0; i<_param->_nb_context; i++)
830	if (internal_BRANCH_EVENT_VAL [i] and PORT_READ(in_BRANCH_EVENT_ACK [i]))
831	{
832	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_EVENT [%d] - Accepted",i);
833
834	upt_event_state_t upt_event_state = reg_UPT_EVENT_STATE [i];
835
836	switch (upt_event_state)
837	{
838	case UPT_EVENT_STATE_KO_DECODE_UPDATE_CONTEXT : upt_event_state = UPT_EVENT_STATE_KO_DECODE_WAIT_END_EVENT; break;
839	case UPT_EVENT_STATE_KO_COMMIT_UPDATE_CONTEXT : upt_event_state = UPT_EVENT_STATE_KO_COMMIT_WAIT_END_EVENT; break;
840	default : break; // an other branch is occured
841	}
842
843	reg_UPT_EVENT_STATE [i] = upt_event_state;
844	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EVENT_STATE : %s (branch_event)",toString(upt_event_state).c_str());
845	}
846
847	// ===================================================================
848	// =====[ EVENT ]=====================================================
849	// ===================================================================
850	for (uint32_t i=0; i<_param->_nb_context; ++i)
851	if (PORT_READ(in_EVENT_VAL [i]) and internal_EVENT_ACK [i])
852	{
853	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT");
854
855	//----------------------------------------------------------------
856	// Cases
857	//----------------------------------------------------------------
858	// * EVENT_TYPE_NONE - nothing
859	// * EVENT_TYPE_MISS_SPECULATION - Change state, reset pointer
860	// * EVENT_TYPE_EXCEPTION - Flush upft and upt, Change state, reset pointer
861	// * EVENT_TYPE_BRANCH_NO_ACCURATE - nothing : manage in decod and update
862	// * EVENT_TYPE_SPR_ACCESS - nothing
863	// * EVENT_TYPE_MSYNC - nothing
864	// * EVENT_TYPE_PSYNC - nothing
865	// * EVENT_TYPE_CSYNC - nothing
866
867	Tevent_type_t event_type = PORT_READ(in_EVENT_TYPE [i]);
868	upt_event_state_t upt_event_state = reg_UPT_EVENT_STATE [i];
869
870	// Test if end of miss -> all previous branch is complete
871	// -> all next branch is finish
872
873	switch (event_type)
874	{
875	case EVENT_TYPE_BRANCH_MISS_SPECULATION :
876	{
877	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * type : EVENT_TYPE_BRANCH_MISS_SPECULATION");
878
879	switch (upt_event_state)
880	{
881	case UPT_EVENT_STATE_KO_COMMIT_WAIT_END_EVENT :
882	{
883	Tdepth_t depth = reg_EVENT_UPT_PTR [i];
884	Tdepth_t update = reg_UPT_UPDATE [i];
885
886	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth);
887
888	if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state == UPDATE_PREDICTION_STATE_END_KO)
889	{
890	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END (event)",i,depth);
891
892	reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_END;
893	}
894
895	// Special case : branch_complete a speculative branch and the context_state signal the end of this event before the complete of previous branch
896	if (depth != update)
897	{
898	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_COMMIT_WAIT_END_UPDATE (event)",i);
899	upt_event_state = UPT_EVENT_STATE_KO_COMMIT_WAIT_END_UPDATE;
900
901	break; // stop here
902	}
903
904	reg_UPT_TOP [i] = reg_UPT_TOP_EVENT [i];
905	reg_UPT_UPDATE [i] = reg_UPT_TOP_EVENT [i];
906
907	// break; continue
908	}
909	case UPT_EVENT_STATE_KO_DECODE_WAIT_END_EVENT :
910	{
911	// Change state
912	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_OK (event)",i);
913
914	upt_event_state = UPT_EVENT_STATE_OK;
915	reg_IS_ACCURATE [i] = true;
916
917	break;
918	}
919	default : break; // an other branch is occured
920	}
921
922	break;
923	}
924	case EVENT_TYPE_LOAD_MISS_SPECULATION :
925	case EVENT_TYPE_EXCEPTION :
926	{
927	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * type : EVENT_TYPE_LOAD_MISS_SPECULATION");
928
929	// Have a miss !!!
930	// Flush UPFT
931	flush_UFPT [i] = true;
932
933	if (upt_event_state == UPT_EVENT_STATE_KO_COMMIT_WAIT_END_UPDATE)
934	{
935	reg_UPT_TOP [i] = reg_UPT_TOP_EVENT [i];
936	reg_UPT_UPDATE [i] = reg_UPT_TOP_EVENT [i];
937	reg_IS_ACCURATE [i] = true;
938
939	upt_event_state = UPT_EVENT_STATE_OK;
940	}
941
942	// Flush UPT
943	uint32_t bottom = reg_UPT_BOTTOM [i];
944
945	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * bottom : %d",bottom);
946
947	// event_state_t event_state = reg_EVENT_STATE [i];
948	// bool previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or
949	// (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or
950	// (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or
951	// (event_state == EVENT_STATE_EVENT_FLUSH_UPT));
952
953	bool find = false; // have slot to update ???
954	bool find_top = false;
955	Tdepth_t top = bottom;
956	Tdepth_t update = bottom;
957	bool empty = reg_UPT_EMPTY [i];
958
959	// flush all slot, because this event is in head of rob
960	for (uint32_t j=0; j<_param->_size_upt_queue[i]; ++j)
961	{
962	Tdepth_t x = (bottom+j)%_param->_size_upt_queue[i];
963
964	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d] : %s",x,toString(reg_UPDATE_PREDICTION_TABLE [i][x]._state).c_str());
965
966	if ((reg_UPDATE_PREDICTION_TABLE [i][x]._state != UPDATE_PREDICTION_STATE_END) and
967	(reg_UPDATE_PREDICTION_TABLE [i][x]._state != UPDATE_PREDICTION_STATE_EMPTY))
968	{
969	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * find at UPT[%d]",x);
970
971	find = true; // find a not empty slot
972	reg_UPDATE_PREDICTION_TABLE [i][x]._state = UPDATE_PREDICTION_STATE_EVENT;
973	reg_UPDATE_PREDICTION_TABLE [i][x]._retire_ok = false;
974	update = x;
975	}
976
977	if (reg_UPDATE_PREDICTION_TABLE [i][x]._state != UPDATE_PREDICTION_STATE_EMPTY)
978	if (not find_top)
979	{
980	top = x;
981	find_top = true;
982	}
983	}
984
985	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * find : %d",find);
986	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top);
987	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update : %d",update);
988
989	// Test if have update slot
990	reg_UPT_TOP_EVENT [i] = reg_UPT_TOP[i];
991	if (find)
992	{
993	// TODO : special case : event is an exception on branch, also depth is not valid
994	reg_UPT_TOP [i] = top; // depth is again valid
995
996	if (bottom == reg_UPT_TOP [i])
997	reg_UPT_EMPTY [i] = true;
998
999	reg_UPT_UPDATE [i] = update;
1000	}
1001
1002	// new state :
1003	// * test if ufpt is empty
1004	// * ok : flush upft and upt
1005	// * ko : test if have previous flush upt
1006	// * ok : nothing
1007	// * ko : flush upt
1008	// reg_EVENT_VAL [i] = find;
1009	// reg_EVENT_IS_BRANCH [i] = false;
1010	// reg_EVENT_UPT_PTR [i] = ((top==0)?_param->_size_upt_queue[i]:top)-1; ///// ZE MODIF
1011	reg_EVENT_UPT_PTR [i] = top;
1012	reg_EVENT_UPT_FULL [i] = (not empty and (bottom == reg_UPT_TOP [i]));
1013	// reg_EVENT_DEPTH [i] = PORT_READ(in_EVENT_DEPTH [i]);//(top+1)%_param->_size_upt_queue[i];
1014	reg_EVENT_DEPTH [i] = top;
1015
1016	// reg_EVENT_ADDRESS_SRC [i] = address_src; // delay_slot is compute in I_State
1017	// reg_EVENT_ADDRESS_DEST_VAL[i] = good_take;
1018	// reg_EVENT_ADDRESS_DEST [i] = good_addr;
1019
1020	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_BOTTOM : %d",reg_UPT_BOTTOM [i]);
1021	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP : %d",reg_UPT_TOP [i]);
1022	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EMPTY : %d",reg_UPT_EMPTY [i]);
1023
1024	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_VAL : %d",reg_EVENT_VAL [i]);
1025	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_PTR : %d",reg_EVENT_UPT_PTR [i]);
1026	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_FULL : %d",reg_EVENT_UPT_FULL [i]);
1027	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]);
1028	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_UPDATE : %d",reg_UFPT_NB_UPDATE [i]);
1029
1030	if (find)
1031	{
1032	// have ras prediction ?
1033	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT_EVENT [%d] <- UPT_EVENT_STATE_KO_EVENT_FLUSH_UPT (event - find)",i);
1034
1035	upt_event_state = UPT_EVENT_STATE_KO_EVENT_FLUSH_UPT;
1036	}
1037	else
1038	{
1039	// special case : nothing
1040	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT_EVENT [%d] <- UPT_EVENT_STATE_KO_EVENT_WAIT_UFPT (event - not find)",i);
1041
1042	// reg_EVENT_VAL [i] = false;
1043
1044	upt_event_state = UPT_EVENT_STATE_KO_EVENT_WAIT_UFPT;
1045	}
1046
1047	break;
1048	}
1049	default :
1050	{
1051	// nothing
1052	break;
1053	}
1054	}
1055
1056	reg_UPT_EVENT_STATE [i] = upt_event_state;
1057	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EVENT_STATE : %s (branch_event)",toString(upt_event_state).c_str());
1058	}
1059
1060	// ===================================================================
1061	// =====[ FLUSH ]=====================================================
1062	// ===================================================================
1063
1064	for (uint32_t i=0; i<_param->_nb_context; ++i)
1065	{
1066	if (flush_UFPT [i])
1067	{
1068	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Flush Update Fetch Prediction Table");
1069	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",i);
1070	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]);
1071
1072	// It's to accelerate miss speculation -> associative access
1073	if (reg_UFPT_NB_NEED_UPDATE [i] == 0)
1074	{
1075	// No entry need prediction, flush all entry -> Reset
1076	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j)
1077	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY;
1078	reg_UFPT_BOTTOM [i] = 0;
1079	reg_UFPT_TOP [i] = 0;
1080	}
1081	else
1082	{
1083	uint32_t bottom = reg_UFPT_BOTTOM [i];
1084	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j)
1085	{
1086	uint32_t index = (bottom+j)%_param->_size_ufpt_queue[i];
1087	// EMPTY : no event
1088	// END : already update
1089	// EVENT : previous event
1090	if (reg_UPDATE_FETCH_PREDICTION_TABLE [i][index]._state == UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD)
1091	{
1092	reg_UFPT_UPDATE [i] = index;
1093	reg_UFPT_NB_UPDATE [i] ++;
1094	reg_UPDATE_FETCH_PREDICTION_TABLE [i][index]._state = UPDATE_FETCH_PREDICTION_STATE_EVENT;
1095	}
1096	}
1097
1098	// Change state
1099	reg_UFPT_EVENT_STATE [i] = UFPT_EVENT_STATE_KO_FLUSH;
1100	}
1101
1102	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (after ) : %d",reg_UFPT_UPDATE [i]);
1103
1104	}
1105
1106	// Change state on UPT
1107	{
1108	upt_event_state_t upt_event_state = reg_UPT_EVENT_STATE [i];
1109	ufpt_event_state_t ufpt_event_state = reg_UFPT_EVENT_STATE [i];
1110
1111	// Test upt event to change state
1112	// test if upt wait ufpt
1113	if (ufpt_event_state == UFPT_EVENT_STATE_OK)
1114	switch (upt_event_state)
1115	{
1116	// this case when don't need flush upt (miss decod and can continue)
1117	case UPT_EVENT_STATE_KO_MISS_WAIT_UFPT : upt_event_state = UPT_EVENT_STATE_KO_COMMIT_UPDATE_CONTEXT; break;
1118	case UPT_EVENT_STATE_KO_EVENT_WAIT_UFPT : upt_event_state = UPT_EVENT_STATE_OK ; break;
1119	default : break;
1120	}
1121
1122	reg_UPT_EVENT_STATE [i] = upt_event_state;
1123	}
1124	}
1125
1126	#ifdef STATISTICS
1127	if (usage_is_set(_usage,USE_STATISTICS))
1128	for (uint32_t i=0; i<_param->_nb_context; i++)
1129	{
1130	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; j++)
1131	if (reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state != UPDATE_FETCH_PREDICTION_STATE_EMPTY)
1132	(*_stat_ufpt_queue_nb_elt [i]) ++;
1133	for (uint32_t j=0; j<_param->_size_upt_queue[i]; j++)
1134	if (reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_EMPTY)
1135	(*_stat_upt_queue_nb_elt [i]) ++;
1136	}
1137	#endif
1138
1139	// ===================================================================
1140	// =====[ PRINT ]=====================================================
1141	// ===================================================================
1142
1143	#if (DEBUG >= DEBUG_TRACE)
1144	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Dump Update_Prediction_Table");
1145	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPDATE_PRIORITY : %d",reg_UPDATE_PRIORITY);
1146	for (uint32_t i=0; i<_param->_nb_context; i++)
1147	{
1148	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_IS_ACCURATE : %d",reg_IS_ACCURATE [i]);
1149	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UFPT_STATE : %s" ,toString(reg_UFPT_EVENT_STATE [i]).c_str());
1150	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_STATE : %s" ,toString(reg_UPT_EVENT_STATE [i]).c_str());
1151	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_VAL : %d" ,reg_EVENT_VAL [i]);
1152	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_PTR : %d" ,reg_EVENT_UPT_PTR [i]);
1153	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_FULL : %d" ,reg_EVENT_UPT_FULL [i]);
1154	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_IS_BRANCH : %d" ,reg_EVENT_IS_BRANCH [i]);
1155	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_DEPTH : %d" ,reg_EVENT_DEPTH [i]);
1156	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_SRC : %.8x (%.8x)",reg_EVENT_ADDRESS_SRC [i],reg_EVENT_ADDRESS_SRC [i]<<2);
1157	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_DEST_VAL: %d" ,reg_EVENT_ADDRESS_DEST_VAL[i]);
1158	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_DEST : %.8x (%.8x)",reg_EVENT_ADDRESS_DEST [i],reg_EVENT_ADDRESS_DEST [i]<<2);
1159	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_CAN_CONTINUE : %d" ,reg_EVENT_CAN_CONTINUE [i]);
1160
1161	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Dump UFPT [%d] (Update_Fetch_Prediction_Table)",i);
1162	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_BOTTOM : %d",reg_UFPT_BOTTOM [i]);
1163	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_TOP : %d",reg_UFPT_TOP [i]);
1164	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE : %d",reg_UFPT_UPDATE [i]);
1165	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]);
1166	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_UPDATE : %d",reg_UFPT_NB_UPDATE [i]);
1167	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; j++)
1168	log_printf(TRACE,Update_Prediction_Table,FUNCTION," [%d] %.4d, %.8x (%.8x) %.8x (%.8x), %.1d %.1d, %.8d %.8x (%.8x) %.4d - %s",
1169	j,
1170	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._condition,
1171	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_src,
1172	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_src<<2,
1173	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_dest,
1174	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_dest<<2,
1175	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._last_take,
1176	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._is_accurate,
1177	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._history,
1178	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_ras,
1179	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_ras<<2,
1180	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._index_ras,
1181	toString(reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state).c_str()
1182	);
1183
1184	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Dump UPT [%d] (Update_Prediction_Table)",i);
1185	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_BOTTOM : %d",reg_UPT_BOTTOM [i]);
1186	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP : %d",reg_UPT_TOP [i]);
1187	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP_EVENT : %d",reg_UPT_TOP_EVENT [i]);
1188	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE : %d",reg_UPT_UPDATE [i]);
1189	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EMPTY : %d",reg_UPT_EMPTY [i]);
1190	for (uint32_t j=0; j<_param->_size_upt_queue[i]; j++)
1191	log_printf(TRACE,Update_Prediction_Table,FUNCTION," [%d] %.4d, %.8x (%.8x) %.8x (%.8x), %.1d %.1d %.1d, %.8d %.8x (%.8x) %.4d - %s",
1192	j,
1193	reg_UPDATE_PREDICTION_TABLE [i][j]._condition,
1194	reg_UPDATE_PREDICTION_TABLE [i][j]._address_src,
1195	reg_UPDATE_PREDICTION_TABLE [i][j]._address_src<<2,
1196	reg_UPDATE_PREDICTION_TABLE [i][j]._address_dest,
1197	reg_UPDATE_PREDICTION_TABLE [i][j]._address_dest<<2,
1198	reg_UPDATE_PREDICTION_TABLE [i][j]._last_take,
1199	reg_UPDATE_PREDICTION_TABLE [i][j]._good_take,
1200	reg_UPDATE_PREDICTION_TABLE [i][j]._is_accurate,
1201	reg_UPDATE_PREDICTION_TABLE [i][j]._history,
1202	reg_UPDATE_PREDICTION_TABLE [i][j]._address_ras,
1203	reg_UPDATE_PREDICTION_TABLE [i][j]._address_ras<<2,
1204	reg_UPDATE_PREDICTION_TABLE [i][j]._index_ras,
1205	toString(reg_UPDATE_PREDICTION_TABLE [i][j]._state).c_str()
1206	);
1207	}
1208	#endif
1209
1210	#ifdef DEBUG_TEST
1211	for (uint32_t i=0; i<_param->_nb_context; i++)
1212	{
1213	if (reg_UFPT_NB_NEED_UPDATE [i] > _param->_size_ufpt_queue[i])
1214	throw ERRORMORPHEO(FUNCTION,toString(_("reg_UFPT_NB_NEED_UPDATE [%d] (%d) is > at size_ufpt_queue (%d).\n"),i,reg_UFPT_NB_NEED_UPDATE [i],_param->_size_ufpt_queue[i]));
1215	if (reg_UFPT_NB_UPDATE [i] > _param->_size_ufpt_queue[i])
1216	throw ERRORMORPHEO(FUNCTION,toString(_("reg_UFPT_NB_UPDATE [%d] (%d) is > at size_ufpt_queue (%d).\n"),i,reg_UFPT_NB_UPDATE [i],_param->_size_ufpt_queue[i]));
1217	}
1218	#endif
1219
1220	}
1221
1222
1223	#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
1224	end_cycle ();
1225	#endif
1226
1227	log_end(Update_Prediction_Table,FUNCTION);
1228	};
1229
1230	}; // end namespace update_prediction_table
1231	}; // end namespace prediction_unit
1232	}; // end namespace front_end
1233	}; // end namespace multi_front_end
1234	}; // end namespace core
1235
1236	}; // end namespace behavioural
1237	}; // end namespace morpheo
1238	#endif

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