[88] | 1 | /* |
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| 2 | * $Id: test.cpp 131 2009-07-08 18:40:08Z rosiere $ |
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| 3 | * |
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| 4 | * [ Description ] |
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| 5 | * |
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| 6 | * Test |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_Front_end/Front_end/SelfTest/include/test.h" |
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| 10 | #include "Behavioural/include/Allocation.h" |
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| 11 | |
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| 12 | void test (string name, |
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| 13 | morpheo::behavioural::core::multi_front_end::front_end::Parameters * _param) |
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| 14 | { |
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| 15 | msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); |
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| 16 | |
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| 17 | #ifdef STATISTICS |
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| 18 | morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX); |
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| 19 | #endif |
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| 20 | |
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| 21 | Tusage_t _usage = USE_ALL; |
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| 22 | |
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| 23 | // _usage = usage_unset(_usage,USE_SYSTEMC ); |
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| 24 | // _usage = usage_unset(_usage,USE_VHDL ); |
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| 25 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); |
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| 26 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); |
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| 27 | // _usage = usage_unset(_usage,USE_POSITION ); |
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| 28 | // _usage = usage_unset(_usage,USE_STATISTICS ); |
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| 29 | // _usage = usage_unset(_usage,USE_INFORMATION ); |
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| 30 | |
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| 31 | Front_end * _Front_end = new Front_end |
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| 32 | (name.c_str(), |
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| 33 | #ifdef STATISTICS |
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| 34 | _parameters_statistics, |
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| 35 | #endif |
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| 36 | _param, |
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| 37 | _usage); |
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| 38 | |
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| 39 | #ifdef SYSTEMC |
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| 40 | if (usage_is_set(_usage,USE_SYSTEMC)) |
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| 41 | { |
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| 42 | /********************************************************************* |
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| 43 | * Déclarations des signaux |
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| 44 | *********************************************************************/ |
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| 45 | string rename; |
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| 46 | |
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| 47 | sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); |
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| 48 | sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); |
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| 49 | |
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[128] | 50 | sc_signal<Tcontrol_t > ** out_ICACHE_REQ_VAL ; |
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| 51 | sc_signal<Tcontrol_t > ** in_ICACHE_REQ_ACK ; |
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| 52 | //sc_signal<Tcontext_t > ** out_ICACHE_REQ_THREAD_ID ; |
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| 53 | sc_signal<Tpacket_t > ** out_ICACHE_REQ_PACKET_ID ; |
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| 54 | sc_signal<Ticache_instruction_t> ** out_ICACHE_REQ_ADDRESS ; |
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| 55 | sc_signal<Ticache_type_t > ** out_ICACHE_REQ_TYPE ; |
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| 56 | sc_signal<Tcontrol_t > ** in_ICACHE_RSP_VAL ; |
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| 57 | sc_signal<Tcontrol_t > ** out_ICACHE_RSP_ACK ; |
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| 58 | //sc_signal<Tcontext_t > ** in_ICACHE_RSP_THREAD_ID ; |
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| 59 | sc_signal<Tpacket_t > ** in_ICACHE_RSP_PACKET_ID ; |
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| 60 | sc_signal<Ticache_instruction_t> *** in_ICACHE_RSP_INSTRUCTION ; |
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| 61 | sc_signal<Ticache_error_t > ** in_ICACHE_RSP_ERROR ; |
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| 62 | sc_signal<Tcontrol_t > ** out_DECOD_VAL ; |
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| 63 | sc_signal<Tcontrol_t > ** in_DECOD_ACK ; |
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| 64 | sc_signal<Tcontext_t > ** out_DECOD_CONTEXT_ID ; |
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| 65 | sc_signal<Tdepth_t > ** out_DECOD_DEPTH ; |
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| 66 | sc_signal<Ttype_t > ** out_DECOD_TYPE ; |
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| 67 | sc_signal<Toperation_t > ** out_DECOD_OPERATION ; |
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| 68 | sc_signal<Tcontrol_t > ** out_DECOD_NO_EXECUTE ; |
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[131] | 69 | sc_signal<Tcontrol_t > ** out_DECOD_LAST_EVENT ; |
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[128] | 70 | sc_signal<Tcontrol_t > ** out_DECOD_IS_DELAY_SLOT ; |
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| 71 | sc_signal<Tgeneral_data_t > ** out_DECOD_ADDRESS ; |
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| 72 | sc_signal<Tgeneral_data_t > ** out_DECOD_ADDRESS_NEXT ; |
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| 73 | sc_signal<Tcontrol_t > ** out_DECOD_HAS_IMMEDIAT ; |
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| 74 | sc_signal<Tgeneral_data_t > ** out_DECOD_IMMEDIAT ; |
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| 75 | sc_signal<Tcontrol_t > ** out_DECOD_READ_RA ; |
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| 76 | sc_signal<Tgeneral_address_t > ** out_DECOD_NUM_REG_RA ; |
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| 77 | sc_signal<Tcontrol_t > ** out_DECOD_READ_RB ; |
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| 78 | sc_signal<Tgeneral_address_t > ** out_DECOD_NUM_REG_RB ; |
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| 79 | sc_signal<Tcontrol_t > ** out_DECOD_READ_RC ; |
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| 80 | sc_signal<Tspecial_address_t > ** out_DECOD_NUM_REG_RC ; |
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| 81 | sc_signal<Tcontrol_t > ** out_DECOD_WRITE_RD ; |
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| 82 | sc_signal<Tgeneral_address_t > ** out_DECOD_NUM_REG_RD ; |
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| 83 | sc_signal<Tcontrol_t > ** out_DECOD_WRITE_RE ; |
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| 84 | sc_signal<Tspecial_address_t > ** out_DECOD_NUM_REG_RE ; |
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| 85 | sc_signal<Texception_t > ** out_DECOD_EXCEPTION_USE ; |
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| 86 | sc_signal<Texception_t > ** out_DECOD_EXCEPTION ; |
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| 87 | sc_signal<Tcontrol_t > ** in_BRANCH_COMPLETE_VAL ; |
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| 88 | sc_signal<Tcontrol_t > ** out_BRANCH_COMPLETE_ACK ; |
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| 89 | sc_signal<Tcontext_t > ** in_BRANCH_COMPLETE_CONTEXT_ID ; |
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| 90 | sc_signal<Tdepth_t > ** in_BRANCH_COMPLETE_DEPTH ; |
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| 91 | sc_signal<Taddress_t > ** in_BRANCH_COMPLETE_ADDRESS ; |
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| 92 | sc_signal<Tcontrol_t > ** in_BRANCH_COMPLETE_NO_SEQUENCE ; |
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| 93 | sc_signal<Tcontrol_t > ** out_BRANCH_COMPLETE_MISS_PREDICTION; |
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| 94 | sc_signal<Tcontrol_t > * in_COMMIT_EVENT_VAL ; |
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| 95 | sc_signal<Tcontrol_t > * out_COMMIT_EVENT_ACK ; |
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| 96 | sc_signal<Tcontext_t > * in_COMMIT_EVENT_CONTEXT_ID ; |
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| 97 | sc_signal<Tdepth_t > * in_COMMIT_EVENT_DEPTH ; |
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| 98 | sc_signal<Tevent_type_t > * in_COMMIT_EVENT_TYPE ; |
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| 99 | sc_signal<Tcontrol_t > * in_COMMIT_EVENT_IS_DELAY_SLOT ; |
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| 100 | sc_signal<Taddress_t > * in_COMMIT_EVENT_ADDRESS ; |
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| 101 | sc_signal<Tcontrol_t > * in_COMMIT_EVENT_ADDRESS_EPCR_VAL ; |
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| 102 | sc_signal<Taddress_t > * in_COMMIT_EVENT_ADDRESS_EPCR ; |
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| 103 | sc_signal<Tcontrol_t > * in_COMMIT_EVENT_ADDRESS_EEAR_VAL ; |
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| 104 | sc_signal<Tgeneral_data_t > * in_COMMIT_EVENT_ADDRESS_EEAR ; |
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| 105 | sc_signal<Tcontrol_t > ** out_EVENT_VAL ; |
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| 106 | sc_signal<Tcontrol_t > ** in_EVENT_ACK ; |
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| 107 | sc_signal<Taddress_t > ** out_EVENT_ADDRESS ; |
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| 108 | sc_signal<Taddress_t > ** out_EVENT_ADDRESS_NEXT ; |
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| 109 | sc_signal<Tcontrol_t > ** out_EVENT_ADDRESS_NEXT_VAL ; |
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| 110 | sc_signal<Tcontrol_t > ** out_EVENT_IS_DS_TAKE ; |
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| 111 | sc_signal<Tcontrol_t > ** out_SPR_EVENT_VAL ; |
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| 112 | sc_signal<Tcontrol_t > ** in_SPR_EVENT_ACK ; |
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| 113 | sc_signal<Tspr_t > ** out_SPR_EVENT_EPCR ; |
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| 114 | sc_signal<Tcontrol_t > ** out_SPR_EVENT_EEAR_WEN ; |
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| 115 | sc_signal<Tspr_t > ** out_SPR_EVENT_EEAR ; |
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| 116 | sc_signal<Tcontrol_t > ** out_SPR_EVENT_SR_DSX ; |
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| 117 | sc_signal<Tcontrol_t > ** out_SPR_EVENT_SR_TO_ESR ; |
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| 118 | sc_signal<Tcounter_t > ** in_NB_INST_COMMIT_ALL ; |
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| 119 | sc_signal<Tcounter_t > ** in_NB_INST_COMMIT_MEM ; |
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| 120 | sc_signal<Tcounter_t > ** out_NB_INST_DECOD_ALL ; |
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| 121 | sc_signal<Tdepth_t > ** out_DEPTH_MIN ; |
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| 122 | sc_signal<Tdepth_t > ** out_DEPTH_MAX ; |
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| 123 | sc_signal<Tcontrol_t > ** out_DEPTH_FULL ; |
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| 124 | sc_signal<Tcontrol_t > ** in_SPR_SR_IEE ; |
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| 125 | sc_signal<Tcontrol_t > ** in_SPR_SR_EPH ; |
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| 126 | sc_signal<Tcontrol_t > ** in_INTERRUPT_ENABLE ; |
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| 127 | |
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[88] | 128 | ALLOC1_SC_SIGNAL(out_ICACHE_REQ_VAL ,"out_ICACHE_REQ_VAL ",Tcontrol_t ,_param->_nb_context); |
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| 129 | ALLOC1_SC_SIGNAL( in_ICACHE_REQ_ACK ," in_ICACHE_REQ_ACK ",Tcontrol_t ,_param->_nb_context); |
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| 130 | //ALLOC1_SC_SIGNAL(out_ICACHE_REQ_THREAD_ID ,"out_ICACHE_REQ_THREAD_ID ",Tcontext_t ,_param->_nb_context); |
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| 131 | ALLOC1_SC_SIGNAL(out_ICACHE_REQ_PACKET_ID ,"out_ICACHE_REQ_PACKET_ID ",Tpacket_t ,_param->_nb_context); |
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| 132 | ALLOC1_SC_SIGNAL(out_ICACHE_REQ_ADDRESS ,"out_ICACHE_REQ_ADDRESS ",Ticache_instruction_t,_param->_nb_context); |
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| 133 | ALLOC1_SC_SIGNAL(out_ICACHE_REQ_TYPE ,"out_ICACHE_REQ_TYPE ",Ticache_type_t ,_param->_nb_context); |
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| 134 | ALLOC1_SC_SIGNAL( in_ICACHE_RSP_VAL ," in_ICACHE_RSP_VAL ",Tcontrol_t ,_param->_nb_context); |
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| 135 | ALLOC1_SC_SIGNAL(out_ICACHE_RSP_ACK ,"out_ICACHE_RSP_ACK ",Tcontrol_t ,_param->_nb_context); |
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| 136 | //ALLOC1_SC_SIGNAL( in_ICACHE_RSP_THREAD_ID ," in_ICACHE_RSP_THREAD_ID ",Tcontext_t ,_param->_nb_context); |
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| 137 | ALLOC1_SC_SIGNAL( in_ICACHE_RSP_PACKET_ID ," in_ICACHE_RSP_PACKET_ID ",Tpacket_t ,_param->_nb_context); |
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| 138 | ALLOC2_SC_SIGNAL( in_ICACHE_RSP_INSTRUCTION ," in_ICACHE_RSP_INSTRUCTION ",Ticache_instruction_t,_param->_nb_context,_param->_nb_inst_fetch[it1]); |
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| 139 | ALLOC1_SC_SIGNAL( in_ICACHE_RSP_ERROR ," in_ICACHE_RSP_ERROR ",Ticache_error_t ,_param->_nb_context); |
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| 140 | ALLOC1_SC_SIGNAL(out_DECOD_VAL ,"out_DECOD_VAL ",Tcontrol_t ,_param->_sum_inst_decod); |
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| 141 | ALLOC1_SC_SIGNAL( in_DECOD_ACK ," in_DECOD_ACK ",Tcontrol_t ,_param->_sum_inst_decod); |
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| 142 | ALLOC1_SC_SIGNAL(out_DECOD_CONTEXT_ID ,"out_DECOD_CONTEXT_ID ",Tcontext_t ,_param->_sum_inst_decod); |
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| 143 | ALLOC1_SC_SIGNAL(out_DECOD_DEPTH ,"out_DECOD_DEPTH ",Tdepth_t ,_param->_sum_inst_decod); |
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| 144 | ALLOC1_SC_SIGNAL(out_DECOD_TYPE ,"out_DECOD_TYPE ",Ttype_t ,_param->_sum_inst_decod); |
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| 145 | ALLOC1_SC_SIGNAL(out_DECOD_OPERATION ,"out_DECOD_OPERATION ",Toperation_t ,_param->_sum_inst_decod); |
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| 146 | ALLOC1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,"out_DECOD_NO_EXECUTE ",Tcontrol_t ,_param->_sum_inst_decod); |
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[131] | 147 | ALLOC1_SC_SIGNAL(out_DECOD_LAST_EVENT ,"out_DECOD_LAST_EVENT ",Tcontrol_t ,_param->_sum_inst_decod); |
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[88] | 148 | ALLOC1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,"out_DECOD_IS_DELAY_SLOT ",Tcontrol_t ,_param->_sum_inst_decod); |
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[108] | 149 | ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS ,"out_DECOD_ADDRESS ",Tgeneral_data_t ,_param->_sum_inst_decod); |
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[105] | 150 | ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS_NEXT ,"out_DECOD_ADDRESS_NEXT ",Tgeneral_data_t ,_param->_sum_inst_decod); |
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[88] | 151 | ALLOC1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT ,"out_DECOD_HAS_IMMEDIAT ",Tcontrol_t ,_param->_sum_inst_decod); |
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| 152 | ALLOC1_SC_SIGNAL(out_DECOD_IMMEDIAT ,"out_DECOD_IMMEDIAT ",Tgeneral_data_t ,_param->_sum_inst_decod); |
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| 153 | ALLOC1_SC_SIGNAL(out_DECOD_READ_RA ,"out_DECOD_READ_RA ",Tcontrol_t ,_param->_sum_inst_decod); |
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| 154 | ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RA ,"out_DECOD_NUM_REG_RA ",Tgeneral_address_t ,_param->_sum_inst_decod); |
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| 155 | ALLOC1_SC_SIGNAL(out_DECOD_READ_RB ,"out_DECOD_READ_RB ",Tcontrol_t ,_param->_sum_inst_decod); |
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| 156 | ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RB ,"out_DECOD_NUM_REG_RB ",Tgeneral_address_t ,_param->_sum_inst_decod); |
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| 157 | ALLOC1_SC_SIGNAL(out_DECOD_READ_RC ,"out_DECOD_READ_RC ",Tcontrol_t ,_param->_sum_inst_decod); |
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| 158 | ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RC ,"out_DECOD_NUM_REG_RC ",Tspecial_address_t ,_param->_sum_inst_decod); |
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| 159 | ALLOC1_SC_SIGNAL(out_DECOD_WRITE_RD ,"out_DECOD_WRITE_RD ",Tcontrol_t ,_param->_sum_inst_decod); |
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| 160 | ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RD ,"out_DECOD_NUM_REG_RD ",Tgeneral_address_t ,_param->_sum_inst_decod); |
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| 161 | ALLOC1_SC_SIGNAL(out_DECOD_WRITE_RE ,"out_DECOD_WRITE_RE ",Tcontrol_t ,_param->_sum_inst_decod); |
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| 162 | ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RE ,"out_DECOD_NUM_REG_RE ",Tspecial_address_t ,_param->_sum_inst_decod); |
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| 163 | ALLOC1_SC_SIGNAL(out_DECOD_EXCEPTION_USE ,"out_DECOD_EXCEPTION_USE ",Texception_t ,_param->_sum_inst_decod); |
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| 164 | ALLOC1_SC_SIGNAL(out_DECOD_EXCEPTION ,"out_DECOD_EXCEPTION ",Texception_t ,_param->_sum_inst_decod); |
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| 165 | ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ," in_BRANCH_COMPLETE_VAL ",Tcontrol_t ,_param->_nb_inst_branch_complete); |
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| 166 | ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,"out_BRANCH_COMPLETE_ACK ",Tcontrol_t ,_param->_nb_inst_branch_complete); |
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| 167 | ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ," in_BRANCH_COMPLETE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_branch_complete); |
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| 168 | ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ," in_BRANCH_COMPLETE_DEPTH ",Tdepth_t ,_param->_nb_inst_branch_complete); |
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| 169 | ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ," in_BRANCH_COMPLETE_ADDRESS ",Taddress_t ,_param->_nb_inst_branch_complete); |
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[98] | 170 | ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_NO_SEQUENCE ," in_BRANCH_COMPLETE_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_inst_branch_complete); |
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[88] | 171 | ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION,"out_BRANCH_COMPLETE_MISS_PREDICTION",Tcontrol_t ,_param->_nb_inst_branch_complete); |
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| 172 | ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_VAL ," in_COMMIT_EVENT_VAL ",Tcontrol_t ); |
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| 173 | ALLOC0_SC_SIGNAL(out_COMMIT_EVENT_ACK ,"out_COMMIT_EVENT_ACK ",Tcontrol_t ); |
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| 174 | ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_CONTEXT_ID ," in_COMMIT_EVENT_CONTEXT_ID ",Tcontext_t ); |
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| 175 | ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_DEPTH ," in_COMMIT_EVENT_DEPTH ",Tdepth_t ); |
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| 176 | ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_TYPE ," in_COMMIT_EVENT_TYPE ",Tevent_type_t ); |
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| 177 | ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_IS_DELAY_SLOT ," in_COMMIT_EVENT_IS_DELAY_SLOT ",Tcontrol_t ); |
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| 178 | ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS ," in_COMMIT_EVENT_ADDRESS ",Taddress_t ); |
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[105] | 179 | ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR_VAL ," in_COMMIT_EVENT_ADDRESS_EPCR_VAL ",Tcontrol_t ); |
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[88] | 180 | ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR ," in_COMMIT_EVENT_ADDRESS_EPCR ",Taddress_t ); |
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| 181 | ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ," in_COMMIT_EVENT_ADDRESS_EEAR_VAL ",Tcontrol_t ); |
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[97] | 182 | ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR ," in_COMMIT_EVENT_ADDRESS_EEAR ",Tgeneral_data_t ); |
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[88] | 183 | ALLOC1_SC_SIGNAL(out_EVENT_VAL ,"out_EVENT_VAL ",Tcontrol_t ,_param->_nb_context); |
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| 184 | ALLOC1_SC_SIGNAL( in_EVENT_ACK ," in_EVENT_ACK ",Tcontrol_t ,_param->_nb_context); |
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| 185 | ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS ,"out_EVENT_ADDRESS ",Taddress_t ,_param->_nb_context); |
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| 186 | ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT ,"out_EVENT_ADDRESS_NEXT ",Taddress_t ,_param->_nb_context); |
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| 187 | ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,"out_EVENT_ADDRESS_NEXT_VAL ",Tcontrol_t ,_param->_nb_context); |
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| 188 | ALLOC1_SC_SIGNAL(out_EVENT_IS_DS_TAKE ,"out_EVENT_IS_DS_TAKE ",Tcontrol_t ,_param->_nb_context); |
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| 189 | ALLOC1_SC_SIGNAL(out_SPR_EVENT_VAL ,"out_SPR_EVENT_VAL ",Tcontrol_t ,_param->_nb_context); |
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| 190 | ALLOC1_SC_SIGNAL( in_SPR_EVENT_ACK ," in_SPR_EVENT_ACK ",Tcontrol_t ,_param->_nb_context); |
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| 191 | ALLOC1_SC_SIGNAL(out_SPR_EVENT_EPCR ,"out_SPR_EVENT_EPCR ",Tspr_t ,_param->_nb_context); |
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| 192 | ALLOC1_SC_SIGNAL(out_SPR_EVENT_EEAR_WEN ,"out_SPR_EVENT_EEAR_WEN ",Tcontrol_t ,_param->_nb_context); |
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| 193 | ALLOC1_SC_SIGNAL(out_SPR_EVENT_EEAR ,"out_SPR_EVENT_EEAR ",Tspr_t ,_param->_nb_context); |
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| 194 | ALLOC1_SC_SIGNAL(out_SPR_EVENT_SR_DSX ,"out_SPR_EVENT_SR_DSX ",Tcontrol_t ,_param->_nb_context); |
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| 195 | ALLOC1_SC_SIGNAL(out_SPR_EVENT_SR_TO_ESR ,"out_SPR_EVENT_SR_TO_ESR ",Tcontrol_t ,_param->_nb_context); |
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| 196 | ALLOC1_SC_SIGNAL( in_NB_INST_COMMIT_ALL ," in_NB_INST_COMMIT_ALL ",Tcounter_t ,_param->_nb_context); |
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| 197 | ALLOC1_SC_SIGNAL( in_NB_INST_COMMIT_MEM ," in_NB_INST_COMMIT_MEM ",Tcounter_t ,_param->_nb_context); |
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[108] | 198 | ALLOC1_SC_SIGNAL(out_NB_INST_DECOD_ALL ,"out_NB_INST_DECOD_ALL ",Tcounter_t ,_param->_nb_context); |
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[88] | 199 | ALLOC1_SC_SIGNAL(out_DEPTH_MIN ,"out_DEPTH_MIN ",Tdepth_t ,_param->_nb_context); |
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| 200 | ALLOC1_SC_SIGNAL(out_DEPTH_MAX ,"out_DEPTH_MAX ",Tdepth_t ,_param->_nb_context); |
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[101] | 201 | ALLOC1_SC_SIGNAL(out_DEPTH_FULL ,"out_DEPTH_FULL ",Tcontrol_t ,_param->_nb_context); |
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[88] | 202 | ALLOC1_SC_SIGNAL( in_SPR_SR_IEE ," in_SPR_SR_IEE ",Tcontrol_t ,_param->_nb_context); |
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| 203 | ALLOC1_SC_SIGNAL( in_SPR_SR_EPH ," in_SPR_SR_EPH ",Tcontrol_t ,_param->_nb_context); |
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| 204 | ALLOC1_SC_SIGNAL( in_INTERRUPT_ENABLE ," in_INTERRUPT_ENABLE ",Tcontrol_t ,_param->_nb_context); |
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| 205 | |
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| 206 | /******************************************************** |
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| 207 | * Instanciation |
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| 208 | ********************************************************/ |
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| 209 | |
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| 210 | msg(_("<%s> : Instanciation of _Front_end.\n"),name.c_str()); |
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| 211 | |
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| 212 | (*(_Front_end->in_CLOCK)) (*(in_CLOCK)); |
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| 213 | (*(_Front_end->in_NRESET)) (*(in_NRESET)); |
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| 214 | |
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| 215 | INSTANCE1_SC_SIGNAL(_Front_end,out_ICACHE_REQ_VAL ,_param->_nb_context); |
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| 216 | INSTANCE1_SC_SIGNAL(_Front_end, in_ICACHE_REQ_ACK ,_param->_nb_context); |
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| 217 | //INSTANCE1_SC_SIGNAL(_Front_end,out_ICACHE_REQ_THREAD_ID ,_param->_nb_context); |
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| 218 | if (_param->_have_port_ifetch_queue_ptr) |
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| 219 | INSTANCE1_SC_SIGNAL(_Front_end,out_ICACHE_REQ_PACKET_ID ,_param->_nb_context); |
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| 220 | INSTANCE1_SC_SIGNAL(_Front_end,out_ICACHE_REQ_ADDRESS ,_param->_nb_context); |
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| 221 | INSTANCE1_SC_SIGNAL(_Front_end,out_ICACHE_REQ_TYPE ,_param->_nb_context); |
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| 222 | INSTANCE1_SC_SIGNAL(_Front_end, in_ICACHE_RSP_VAL ,_param->_nb_context); |
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| 223 | INSTANCE1_SC_SIGNAL(_Front_end,out_ICACHE_RSP_ACK ,_param->_nb_context); |
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| 224 | //INSTANCE1_SC_SIGNAL(_Front_end, in_ICACHE_RSP_THREAD_ID ,_param->_nb_context); |
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| 225 | if (_param->_have_port_ifetch_queue_ptr) |
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| 226 | INSTANCE1_SC_SIGNAL(_Front_end, in_ICACHE_RSP_PACKET_ID ,_param->_nb_context); |
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| 227 | INSTANCE2_SC_SIGNAL(_Front_end, in_ICACHE_RSP_INSTRUCTION ,_param->_nb_context,_param->_nb_inst_fetch[it1]); |
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| 228 | INSTANCE1_SC_SIGNAL(_Front_end, in_ICACHE_RSP_ERROR ,_param->_nb_context); |
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| 229 | INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_VAL ,_param->_sum_inst_decod); |
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| 230 | INSTANCE1_SC_SIGNAL(_Front_end, in_DECOD_ACK ,_param->_sum_inst_decod); |
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| 231 | if (_param->_have_port_context_id) |
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| 232 | INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_CONTEXT_ID ,_param->_sum_inst_decod); |
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| 233 | if (_param->_have_port_depth) |
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| 234 | INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_DEPTH ,_param->_sum_inst_decod); |
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| 235 | INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_TYPE ,_param->_sum_inst_decod); |
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| 236 | INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_OPERATION ,_param->_sum_inst_decod); |
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| 237 | INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_NO_EXECUTE ,_param->_sum_inst_decod); |
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[131] | 238 | INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_LAST_EVENT ,_param->_sum_inst_decod); |
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[88] | 239 | INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_IS_DELAY_SLOT ,_param->_sum_inst_decod); |
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[108] | 240 | #ifdef DEBUG |
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| 241 | INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_ADDRESS ,_param->_sum_inst_decod); |
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| 242 | #endif |
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[105] | 243 | INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_ADDRESS_NEXT ,_param->_sum_inst_decod); |
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[88] | 244 | INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_HAS_IMMEDIAT ,_param->_sum_inst_decod); |
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| 245 | INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_IMMEDIAT ,_param->_sum_inst_decod); |
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| 246 | INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_READ_RA ,_param->_sum_inst_decod); |
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| 247 | INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_NUM_REG_RA ,_param->_sum_inst_decod); |
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| 248 | INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_READ_RB ,_param->_sum_inst_decod); |
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| 249 | INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_NUM_REG_RB ,_param->_sum_inst_decod); |
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| 250 | INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_READ_RC ,_param->_sum_inst_decod); |
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| 251 | INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_NUM_REG_RC ,_param->_sum_inst_decod); |
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| 252 | INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_WRITE_RD ,_param->_sum_inst_decod); |
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| 253 | INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_NUM_REG_RD ,_param->_sum_inst_decod); |
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| 254 | INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_WRITE_RE ,_param->_sum_inst_decod); |
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| 255 | INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_NUM_REG_RE ,_param->_sum_inst_decod); |
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| 256 | INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_EXCEPTION_USE ,_param->_sum_inst_decod); |
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| 257 | INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_EXCEPTION ,_param->_sum_inst_decod); |
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| 258 | INSTANCE1_SC_SIGNAL(_Front_end, in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete); |
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| 259 | INSTANCE1_SC_SIGNAL(_Front_end,out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete); |
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| 260 | if (_param->_have_port_context_id) |
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| 261 | INSTANCE1_SC_SIGNAL(_Front_end, in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete); |
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| 262 | if (_param->_have_port_depth) |
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| 263 | INSTANCE1_SC_SIGNAL(_Front_end, in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete); |
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| 264 | INSTANCE1_SC_SIGNAL(_Front_end, in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete); |
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[98] | 265 | INSTANCE1_SC_SIGNAL(_Front_end, in_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete); |
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[88] | 266 | INSTANCE1_SC_SIGNAL(_Front_end,out_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete); |
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| 267 | INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_VAL ); |
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| 268 | INSTANCE0_SC_SIGNAL(_Front_end,out_COMMIT_EVENT_ACK ); |
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| 269 | if (_param->_have_port_context_id) |
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| 270 | INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_CONTEXT_ID ); |
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| 271 | if (_param->_have_port_depth) |
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| 272 | INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_DEPTH ); |
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| 273 | INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_TYPE ); |
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| 274 | INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_IS_DELAY_SLOT ); |
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| 275 | INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_ADDRESS ); |
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[105] | 276 | INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_ADDRESS_EPCR_VAL ); |
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[88] | 277 | INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_ADDRESS_EPCR ); |
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| 278 | INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_ADDRESS_EEAR_VAL ); |
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| 279 | INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_ADDRESS_EEAR ); |
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| 280 | INSTANCE1_SC_SIGNAL(_Front_end,out_EVENT_VAL ,_param->_nb_context); |
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| 281 | INSTANCE1_SC_SIGNAL(_Front_end, in_EVENT_ACK ,_param->_nb_context); |
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| 282 | INSTANCE1_SC_SIGNAL(_Front_end,out_EVENT_ADDRESS ,_param->_nb_context); |
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| 283 | INSTANCE1_SC_SIGNAL(_Front_end,out_EVENT_ADDRESS_NEXT ,_param->_nb_context); |
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| 284 | INSTANCE1_SC_SIGNAL(_Front_end,out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context); |
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| 285 | INSTANCE1_SC_SIGNAL(_Front_end,out_EVENT_IS_DS_TAKE ,_param->_nb_context); |
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| 286 | INSTANCE1_SC_SIGNAL(_Front_end,out_SPR_EVENT_VAL ,_param->_nb_context); |
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| 287 | INSTANCE1_SC_SIGNAL(_Front_end, in_SPR_EVENT_ACK ,_param->_nb_context); |
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| 288 | INSTANCE1_SC_SIGNAL(_Front_end,out_SPR_EVENT_EPCR ,_param->_nb_context); |
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| 289 | INSTANCE1_SC_SIGNAL(_Front_end,out_SPR_EVENT_EEAR_WEN ,_param->_nb_context); |
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| 290 | INSTANCE1_SC_SIGNAL(_Front_end,out_SPR_EVENT_EEAR ,_param->_nb_context); |
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| 291 | INSTANCE1_SC_SIGNAL(_Front_end,out_SPR_EVENT_SR_DSX ,_param->_nb_context); |
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| 292 | INSTANCE1_SC_SIGNAL(_Front_end,out_SPR_EVENT_SR_TO_ESR ,_param->_nb_context); |
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| 293 | INSTANCE1_SC_SIGNAL(_Front_end, in_NB_INST_COMMIT_ALL ,_param->_nb_context); |
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| 294 | INSTANCE1_SC_SIGNAL(_Front_end, in_NB_INST_COMMIT_MEM ,_param->_nb_context); |
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[108] | 295 | INSTANCE1_SC_SIGNAL(_Front_end,out_NB_INST_DECOD_ALL ,_param->_nb_context); |
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[88] | 296 | if (_param->_have_port_depth) |
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[101] | 297 | { |
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[88] | 298 | INSTANCE1_SC_SIGNAL(_Front_end,out_DEPTH_MIN ,_param->_nb_context); |
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| 299 | INSTANCE1_SC_SIGNAL(_Front_end,out_DEPTH_MAX ,_param->_nb_context); |
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[101] | 300 | } |
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| 301 | INSTANCE1_SC_SIGNAL(_Front_end,out_DEPTH_FULL ,_param->_nb_context); |
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[88] | 302 | INSTANCE1_SC_SIGNAL(_Front_end, in_SPR_SR_IEE ,_param->_nb_context); |
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| 303 | INSTANCE1_SC_SIGNAL(_Front_end, in_SPR_SR_EPH ,_param->_nb_context); |
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| 304 | INSTANCE1_SC_SIGNAL(_Front_end, in_INTERRUPT_ENABLE ,_param->_nb_context); |
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| 305 | |
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| 306 | msg(_("<%s> : Start Simulation ............\n"),name.c_str()); |
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| 307 | |
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| 308 | Time * _time = new Time(); |
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| 309 | |
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| 310 | /******************************************************** |
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| 311 | * Simulation - Begin |
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| 312 | ********************************************************/ |
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| 313 | |
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| 314 | // Initialisation |
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| 315 | |
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| 316 | const uint32_t seed = 0; |
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| 317 | //const uint32_t seed = static_cast<uint32_t>(time(NULL)); |
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| 318 | |
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| 319 | srand(seed); |
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| 320 | |
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| 321 | SC_START(0); |
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| 322 | LABEL("Initialisation"); |
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| 323 | |
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[131] | 324 | // for (uint32_t i=0; i<_param->_nb_context; ++i) |
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| 325 | // { |
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| 326 | // in_ICACHE_REQ_ACK [i]->write(0); |
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| 327 | // in_ICACHE_RSP_VAL [i]->write(0); |
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| 328 | // in_EVENT_ACK [i]->write(0); |
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| 329 | // in_SPR_EVENT_ACK [i]->write(0); |
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| 330 | // in_NB_INST_COMMIT_ALL [i]->write(0); // no inst |
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| 331 | // in_NB_INST_COMMIT_MEM [i]->write(0); // no inst |
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| 332 | // in_SPR_SR_IEE [i]->write(0); // interrupt disable |
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| 333 | // in_SPR_SR_EPH [i]->write(0); // exception msb = 0 |
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| 334 | // in_INTERRUPT_ENABLE [i]->write(0); // no interrupt |
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| 335 | // } |
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| 336 | // for (uint32_t i=0; i<_param->_sum_inst_decod; ++i) |
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| 337 | // in_DECOD_ACK [i]->write(0); |
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| 338 | // for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i) |
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| 339 | // in_BRANCH_COMPLETE_VAL [i]->write(0); |
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| 340 | // in_COMMIT_EVENT_VAL->write(0); |
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[88] | 341 | |
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| 342 | |
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[131] | 343 | // for (uint32_t i=0; i<_param->_nb_context; ++i) |
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| 344 | // { |
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| 345 | // TEST(Tcontrol_t,out_ICACHE_REQ_VAL [i]->read(),0); |
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| 346 | // TEST(Tcontrol_t,out_ICACHE_RSP_ACK [i]->read(),1); // Can accept a respons |
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| 347 | // TEST(Tcontrol_t,out_EVENT_VAL [i]->read(),0); |
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| 348 | // TEST(Tcontrol_t,out_SPR_EVENT_VAL [i]->read(),0); |
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| 349 | // TEST(Tdepth_t ,out_DEPTH_MIN [i]->read(),0); // no branch speculated |
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| 350 | // TEST(Tdepth_t ,out_DEPTH_MAX [i]->read(),0); // no branch speculated |
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| 351 | // TEST(Tdepth_t ,out_DEPTH_FULL [i]->read(),0); // no branch speculated |
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| 352 | // } |
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| 353 | // for (uint32_t i=0; i<_param->_sum_inst_decod; ++i) |
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| 354 | // TEST(Tcontrol_t,out_DECOD_VAL [i]->read(),0); |
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| 355 | // for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i) |
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| 356 | // TEST(Tcontrol_t,out_BRANCH_COMPLETE_ACK [i]->read(),0); // can't accept (interactive) |
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| 357 | // TEST(Tcontrol_t,out_COMMIT_EVENT_ACK ->read(),1); // can accept |
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[88] | 358 | |
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| 359 | LABEL("Reset"); |
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| 360 | in_NRESET->write(0); |
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| 361 | SC_START(5); |
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| 362 | in_NRESET->write(1); |
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| 363 | |
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| 364 | LABEL("Loop of Test"); |
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| 365 | |
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[131] | 366 | for (uint32_t iteration=0; iteration< NB_ITERATION; iteration ++) |
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[88] | 367 | { |
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| 368 | LABEL("Iteration %d",iteration); |
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| 369 | |
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| 370 | SC_START(1); |
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| 371 | } |
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| 372 | |
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| 373 | /******************************************************** |
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| 374 | * Simulation - End |
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| 375 | ********************************************************/ |
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| 376 | |
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| 377 | TEST_OK ("End of Simulation"); |
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| 378 | delete _time; |
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| 379 | |
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| 380 | msg(_("<%s> : ............ Stop Simulation\n"),name.c_str()); |
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| 381 | |
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| 382 | delete in_CLOCK; |
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| 383 | delete in_NRESET; |
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| 384 | |
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| 385 | DELETE1_SC_SIGNAL(out_ICACHE_REQ_VAL ,_param->_nb_context); |
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| 386 | DELETE1_SC_SIGNAL( in_ICACHE_REQ_ACK ,_param->_nb_context); |
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| 387 | //DELETE1_SC_SIGNAL(out_ICACHE_REQ_THREAD_ID ,_param->_nb_context); |
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| 388 | DELETE1_SC_SIGNAL(out_ICACHE_REQ_PACKET_ID ,_param->_nb_context); |
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| 389 | DELETE1_SC_SIGNAL(out_ICACHE_REQ_ADDRESS ,_param->_nb_context); |
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| 390 | DELETE1_SC_SIGNAL(out_ICACHE_REQ_TYPE ,_param->_nb_context); |
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| 391 | DELETE1_SC_SIGNAL( in_ICACHE_RSP_VAL ,_param->_nb_context); |
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| 392 | DELETE1_SC_SIGNAL(out_ICACHE_RSP_ACK ,_param->_nb_context); |
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| 393 | //DELETE1_SC_SIGNAL( in_ICACHE_RSP_THREAD_ID ,_param->_nb_context); |
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| 394 | DELETE1_SC_SIGNAL( in_ICACHE_RSP_PACKET_ID ,_param->_nb_context); |
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| 395 | DELETE2_SC_SIGNAL( in_ICACHE_RSP_INSTRUCTION ,_param->_nb_context,_param->_nb_inst_fetch[it1]); |
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| 396 | DELETE1_SC_SIGNAL( in_ICACHE_RSP_ERROR ,_param->_nb_context); |
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| 397 | DELETE1_SC_SIGNAL(out_DECOD_VAL ,_param->_sum_inst_decod); |
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| 398 | DELETE1_SC_SIGNAL( in_DECOD_ACK ,_param->_sum_inst_decod); |
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| 399 | DELETE1_SC_SIGNAL(out_DECOD_CONTEXT_ID ,_param->_sum_inst_decod); |
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| 400 | DELETE1_SC_SIGNAL(out_DECOD_DEPTH ,_param->_sum_inst_decod); |
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| 401 | DELETE1_SC_SIGNAL(out_DECOD_TYPE ,_param->_sum_inst_decod); |
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| 402 | DELETE1_SC_SIGNAL(out_DECOD_OPERATION ,_param->_sum_inst_decod); |
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| 403 | DELETE1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,_param->_sum_inst_decod); |
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[131] | 404 | DELETE1_SC_SIGNAL(out_DECOD_LAST_EVENT ,_param->_sum_inst_decod); |
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[88] | 405 | DELETE1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,_param->_sum_inst_decod); |
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[108] | 406 | DELETE1_SC_SIGNAL(out_DECOD_ADDRESS ,_param->_sum_inst_decod); |
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[105] | 407 | DELETE1_SC_SIGNAL(out_DECOD_ADDRESS_NEXT ,_param->_sum_inst_decod); |
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[88] | 408 | DELETE1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT ,_param->_sum_inst_decod); |
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| 409 | DELETE1_SC_SIGNAL(out_DECOD_IMMEDIAT ,_param->_sum_inst_decod); |
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| 410 | DELETE1_SC_SIGNAL(out_DECOD_READ_RA ,_param->_sum_inst_decod); |
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| 411 | DELETE1_SC_SIGNAL(out_DECOD_NUM_REG_RA ,_param->_sum_inst_decod); |
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| 412 | DELETE1_SC_SIGNAL(out_DECOD_READ_RB ,_param->_sum_inst_decod); |
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| 413 | DELETE1_SC_SIGNAL(out_DECOD_NUM_REG_RB ,_param->_sum_inst_decod); |
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| 414 | DELETE1_SC_SIGNAL(out_DECOD_READ_RC ,_param->_sum_inst_decod); |
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| 415 | DELETE1_SC_SIGNAL(out_DECOD_NUM_REG_RC ,_param->_sum_inst_decod); |
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| 416 | DELETE1_SC_SIGNAL(out_DECOD_WRITE_RD ,_param->_sum_inst_decod); |
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| 417 | DELETE1_SC_SIGNAL(out_DECOD_NUM_REG_RD ,_param->_sum_inst_decod); |
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| 418 | DELETE1_SC_SIGNAL(out_DECOD_WRITE_RE ,_param->_sum_inst_decod); |
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| 419 | DELETE1_SC_SIGNAL(out_DECOD_NUM_REG_RE ,_param->_sum_inst_decod); |
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| 420 | DELETE1_SC_SIGNAL(out_DECOD_EXCEPTION_USE ,_param->_sum_inst_decod); |
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| 421 | DELETE1_SC_SIGNAL(out_DECOD_EXCEPTION ,_param->_sum_inst_decod); |
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| 422 | DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete); |
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| 423 | DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete); |
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| 424 | DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete); |
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| 425 | DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete); |
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| 426 | DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete); |
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[98] | 427 | DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete); |
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[88] | 428 | DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete); |
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| 429 | DELETE0_SC_SIGNAL( in_COMMIT_EVENT_VAL ); |
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| 430 | DELETE0_SC_SIGNAL(out_COMMIT_EVENT_ACK ); |
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| 431 | DELETE0_SC_SIGNAL( in_COMMIT_EVENT_CONTEXT_ID ); |
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| 432 | DELETE0_SC_SIGNAL( in_COMMIT_EVENT_DEPTH ); |
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| 433 | DELETE0_SC_SIGNAL( in_COMMIT_EVENT_TYPE ); |
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| 434 | DELETE0_SC_SIGNAL( in_COMMIT_EVENT_IS_DELAY_SLOT ); |
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| 435 | DELETE0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS ); |
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[105] | 436 | DELETE0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR_VAL ); |
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[88] | 437 | DELETE0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR ); |
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| 438 | DELETE0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ); |
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| 439 | DELETE0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR ); |
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| 440 | DELETE1_SC_SIGNAL(out_EVENT_VAL ,_param->_nb_context); |
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| 441 | DELETE1_SC_SIGNAL( in_EVENT_ACK ,_param->_nb_context); |
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| 442 | DELETE1_SC_SIGNAL(out_EVENT_ADDRESS ,_param->_nb_context); |
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| 443 | DELETE1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT ,_param->_nb_context); |
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| 444 | DELETE1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context); |
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| 445 | DELETE1_SC_SIGNAL(out_EVENT_IS_DS_TAKE ,_param->_nb_context); |
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| 446 | DELETE1_SC_SIGNAL(out_SPR_EVENT_VAL ,_param->_nb_context); |
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| 447 | DELETE1_SC_SIGNAL( in_SPR_EVENT_ACK ,_param->_nb_context); |
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| 448 | DELETE1_SC_SIGNAL(out_SPR_EVENT_EPCR ,_param->_nb_context); |
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| 449 | DELETE1_SC_SIGNAL(out_SPR_EVENT_EEAR_WEN ,_param->_nb_context); |
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| 450 | DELETE1_SC_SIGNAL(out_SPR_EVENT_EEAR ,_param->_nb_context); |
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| 451 | DELETE1_SC_SIGNAL(out_SPR_EVENT_SR_DSX ,_param->_nb_context); |
---|
| 452 | DELETE1_SC_SIGNAL(out_SPR_EVENT_SR_TO_ESR ,_param->_nb_context); |
---|
| 453 | DELETE1_SC_SIGNAL( in_NB_INST_COMMIT_ALL ,_param->_nb_context); |
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| 454 | DELETE1_SC_SIGNAL( in_NB_INST_COMMIT_MEM ,_param->_nb_context); |
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[108] | 455 | DELETE1_SC_SIGNAL(out_NB_INST_DECOD_ALL ,_param->_nb_context); |
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[88] | 456 | DELETE1_SC_SIGNAL(out_DEPTH_MIN ,_param->_nb_context); |
---|
| 457 | DELETE1_SC_SIGNAL(out_DEPTH_MAX ,_param->_nb_context); |
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[101] | 458 | DELETE1_SC_SIGNAL(out_DEPTH_FULL ,_param->_nb_context); |
---|
[88] | 459 | DELETE1_SC_SIGNAL( in_SPR_SR_IEE ,_param->_nb_context); |
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| 460 | DELETE1_SC_SIGNAL( in_SPR_SR_EPH ,_param->_nb_context); |
---|
| 461 | DELETE1_SC_SIGNAL( in_INTERRUPT_ENABLE ,_param->_nb_context); |
---|
| 462 | } |
---|
| 463 | #endif |
---|
| 464 | |
---|
| 465 | delete _Front_end; |
---|
| 466 | #ifdef STATISTICS |
---|
| 467 | delete _parameters_statistics; |
---|
| 468 | #endif |
---|
| 469 | } |
---|