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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/test.cpp @ 108

Last change on this file since 108 was 108, checked in by rosiere, 15 years ago
1) decod_queue : add reg_LAST_SLOT. 2) Commit : insert on event -> to pop decod_queue. Head test : add information (speculative or not) 3) Context State / UPT : Branch miss and Load miss in same cycle. 4) Free List : Bank is on LSB not MSB. 5) Platforms : move data
Property svn:keywords set to `Id`
File size: 27.5 KB

Line
1	/*
2	* $Id: test.cpp 108 2009-02-12 11:55:06Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#include "Behavioural/Core/Multi_Front_end/Front_end/SelfTest/include/test.h"
10	#include "Behavioural/include/Allocation.h"
11
12	void test (string name,
13	morpheo::behavioural::core::multi_front_end::front_end::Parameters * _param)
14	{
15	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
16
17	#ifdef STATISTICS
18	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX);
19	#endif
20
21	Tusage_t _usage = USE_ALL;
22
23	// _usage = usage_unset(_usage,USE_SYSTEMC );
24	// _usage = usage_unset(_usage,USE_VHDL );
25	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
26	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
27	// _usage = usage_unset(_usage,USE_POSITION );
28	// _usage = usage_unset(_usage,USE_STATISTICS );
29	// _usage = usage_unset(_usage,USE_INFORMATION );
30
31	Front_end * _Front_end = new Front_end
32	(name.c_str(),
33	#ifdef STATISTICS
34	_parameters_statistics,
35	#endif
36	_param,
37	_usage);
38
39	#ifdef SYSTEMC
40	if (usage_is_set(_usage,USE_SYSTEMC))
41	{
42	/*********************************************************************
43	* Déclarations des signaux
44	*********************************************************************/
45	string rename;
46
47	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
48	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
49
50	ALLOC1_SC_SIGNAL(out_ICACHE_REQ_VAL ,"out_ICACHE_REQ_VAL ",Tcontrol_t ,_param->_nb_context);
51	ALLOC1_SC_SIGNAL( in_ICACHE_REQ_ACK ," in_ICACHE_REQ_ACK ",Tcontrol_t ,_param->_nb_context);
52	//ALLOC1_SC_SIGNAL(out_ICACHE_REQ_THREAD_ID ,"out_ICACHE_REQ_THREAD_ID ",Tcontext_t ,_param->_nb_context);
53	ALLOC1_SC_SIGNAL(out_ICACHE_REQ_PACKET_ID ,"out_ICACHE_REQ_PACKET_ID ",Tpacket_t ,_param->_nb_context);
54	ALLOC1_SC_SIGNAL(out_ICACHE_REQ_ADDRESS ,"out_ICACHE_REQ_ADDRESS ",Ticache_instruction_t,_param->_nb_context);
55	ALLOC1_SC_SIGNAL(out_ICACHE_REQ_TYPE ,"out_ICACHE_REQ_TYPE ",Ticache_type_t ,_param->_nb_context);
56	ALLOC1_SC_SIGNAL( in_ICACHE_RSP_VAL ," in_ICACHE_RSP_VAL ",Tcontrol_t ,_param->_nb_context);
57	ALLOC1_SC_SIGNAL(out_ICACHE_RSP_ACK ,"out_ICACHE_RSP_ACK ",Tcontrol_t ,_param->_nb_context);
58	//ALLOC1_SC_SIGNAL( in_ICACHE_RSP_THREAD_ID ," in_ICACHE_RSP_THREAD_ID ",Tcontext_t ,_param->_nb_context);
59	ALLOC1_SC_SIGNAL( in_ICACHE_RSP_PACKET_ID ," in_ICACHE_RSP_PACKET_ID ",Tpacket_t ,_param->_nb_context);
60	ALLOC2_SC_SIGNAL( in_ICACHE_RSP_INSTRUCTION ," in_ICACHE_RSP_INSTRUCTION ",Ticache_instruction_t,_param->_nb_context,_param->_nb_inst_fetch[it1]);
61	ALLOC1_SC_SIGNAL( in_ICACHE_RSP_ERROR ," in_ICACHE_RSP_ERROR ",Ticache_error_t ,_param->_nb_context);
62	ALLOC1_SC_SIGNAL(out_DECOD_VAL ,"out_DECOD_VAL ",Tcontrol_t ,_param->_sum_inst_decod);
63	ALLOC1_SC_SIGNAL( in_DECOD_ACK ," in_DECOD_ACK ",Tcontrol_t ,_param->_sum_inst_decod);
64	ALLOC1_SC_SIGNAL(out_DECOD_CONTEXT_ID ,"out_DECOD_CONTEXT_ID ",Tcontext_t ,_param->_sum_inst_decod);
65	ALLOC1_SC_SIGNAL(out_DECOD_DEPTH ,"out_DECOD_DEPTH ",Tdepth_t ,_param->_sum_inst_decod);
66	ALLOC1_SC_SIGNAL(out_DECOD_TYPE ,"out_DECOD_TYPE ",Ttype_t ,_param->_sum_inst_decod);
67	ALLOC1_SC_SIGNAL(out_DECOD_OPERATION ,"out_DECOD_OPERATION ",Toperation_t ,_param->_sum_inst_decod);
68	ALLOC1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,"out_DECOD_NO_EXECUTE ",Tcontrol_t ,_param->_sum_inst_decod);
69	ALLOC1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,"out_DECOD_IS_DELAY_SLOT ",Tcontrol_t ,_param->_sum_inst_decod);
70	#ifdef DEBUG
71	ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS ,"out_DECOD_ADDRESS ",Tgeneral_data_t ,_param->_sum_inst_decod);
72	#endif
73	ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS_NEXT ,"out_DECOD_ADDRESS_NEXT ",Tgeneral_data_t ,_param->_sum_inst_decod);
74	ALLOC1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT ,"out_DECOD_HAS_IMMEDIAT ",Tcontrol_t ,_param->_sum_inst_decod);
75	ALLOC1_SC_SIGNAL(out_DECOD_IMMEDIAT ,"out_DECOD_IMMEDIAT ",Tgeneral_data_t ,_param->_sum_inst_decod);
76	ALLOC1_SC_SIGNAL(out_DECOD_READ_RA ,"out_DECOD_READ_RA ",Tcontrol_t ,_param->_sum_inst_decod);
77	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RA ,"out_DECOD_NUM_REG_RA ",Tgeneral_address_t ,_param->_sum_inst_decod);
78	ALLOC1_SC_SIGNAL(out_DECOD_READ_RB ,"out_DECOD_READ_RB ",Tcontrol_t ,_param->_sum_inst_decod);
79	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RB ,"out_DECOD_NUM_REG_RB ",Tgeneral_address_t ,_param->_sum_inst_decod);
80	ALLOC1_SC_SIGNAL(out_DECOD_READ_RC ,"out_DECOD_READ_RC ",Tcontrol_t ,_param->_sum_inst_decod);
81	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RC ,"out_DECOD_NUM_REG_RC ",Tspecial_address_t ,_param->_sum_inst_decod);
82	ALLOC1_SC_SIGNAL(out_DECOD_WRITE_RD ,"out_DECOD_WRITE_RD ",Tcontrol_t ,_param->_sum_inst_decod);
83	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RD ,"out_DECOD_NUM_REG_RD ",Tgeneral_address_t ,_param->_sum_inst_decod);
84	ALLOC1_SC_SIGNAL(out_DECOD_WRITE_RE ,"out_DECOD_WRITE_RE ",Tcontrol_t ,_param->_sum_inst_decod);
85	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RE ,"out_DECOD_NUM_REG_RE ",Tspecial_address_t ,_param->_sum_inst_decod);
86	ALLOC1_SC_SIGNAL(out_DECOD_EXCEPTION_USE ,"out_DECOD_EXCEPTION_USE ",Texception_t ,_param->_sum_inst_decod);
87	ALLOC1_SC_SIGNAL(out_DECOD_EXCEPTION ,"out_DECOD_EXCEPTION ",Texception_t ,_param->_sum_inst_decod);
88	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ," in_BRANCH_COMPLETE_VAL ",Tcontrol_t ,_param->_nb_inst_branch_complete);
89	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,"out_BRANCH_COMPLETE_ACK ",Tcontrol_t ,_param->_nb_inst_branch_complete);
90	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ," in_BRANCH_COMPLETE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_branch_complete);
91	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ," in_BRANCH_COMPLETE_DEPTH ",Tdepth_t ,_param->_nb_inst_branch_complete);
92	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ," in_BRANCH_COMPLETE_ADDRESS ",Taddress_t ,_param->_nb_inst_branch_complete);
93	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_NO_SEQUENCE ," in_BRANCH_COMPLETE_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_inst_branch_complete);
94	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION,"out_BRANCH_COMPLETE_MISS_PREDICTION",Tcontrol_t ,_param->_nb_inst_branch_complete);
95	ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_VAL ," in_COMMIT_EVENT_VAL ",Tcontrol_t );
96	ALLOC0_SC_SIGNAL(out_COMMIT_EVENT_ACK ,"out_COMMIT_EVENT_ACK ",Tcontrol_t );
97	ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_CONTEXT_ID ," in_COMMIT_EVENT_CONTEXT_ID ",Tcontext_t );
98	ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_DEPTH ," in_COMMIT_EVENT_DEPTH ",Tdepth_t );
99	ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_TYPE ," in_COMMIT_EVENT_TYPE ",Tevent_type_t );
100	ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_IS_DELAY_SLOT ," in_COMMIT_EVENT_IS_DELAY_SLOT ",Tcontrol_t );
101	ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS ," in_COMMIT_EVENT_ADDRESS ",Taddress_t );
102	ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR_VAL ," in_COMMIT_EVENT_ADDRESS_EPCR_VAL ",Tcontrol_t );
103	ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR ," in_COMMIT_EVENT_ADDRESS_EPCR ",Taddress_t );
104	ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ," in_COMMIT_EVENT_ADDRESS_EEAR_VAL ",Tcontrol_t );
105	ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR ," in_COMMIT_EVENT_ADDRESS_EEAR ",Tgeneral_data_t );
106	ALLOC1_SC_SIGNAL(out_EVENT_VAL ,"out_EVENT_VAL ",Tcontrol_t ,_param->_nb_context);
107	ALLOC1_SC_SIGNAL( in_EVENT_ACK ," in_EVENT_ACK ",Tcontrol_t ,_param->_nb_context);
108	ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS ,"out_EVENT_ADDRESS ",Taddress_t ,_param->_nb_context);
109	ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT ,"out_EVENT_ADDRESS_NEXT ",Taddress_t ,_param->_nb_context);
110	ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,"out_EVENT_ADDRESS_NEXT_VAL ",Tcontrol_t ,_param->_nb_context);
111	ALLOC1_SC_SIGNAL(out_EVENT_IS_DS_TAKE ,"out_EVENT_IS_DS_TAKE ",Tcontrol_t ,_param->_nb_context);
112	ALLOC1_SC_SIGNAL(out_SPR_EVENT_VAL ,"out_SPR_EVENT_VAL ",Tcontrol_t ,_param->_nb_context);
113	ALLOC1_SC_SIGNAL( in_SPR_EVENT_ACK ," in_SPR_EVENT_ACK ",Tcontrol_t ,_param->_nb_context);
114	ALLOC1_SC_SIGNAL(out_SPR_EVENT_EPCR ,"out_SPR_EVENT_EPCR ",Tspr_t ,_param->_nb_context);
115	ALLOC1_SC_SIGNAL(out_SPR_EVENT_EEAR_WEN ,"out_SPR_EVENT_EEAR_WEN ",Tcontrol_t ,_param->_nb_context);
116	ALLOC1_SC_SIGNAL(out_SPR_EVENT_EEAR ,"out_SPR_EVENT_EEAR ",Tspr_t ,_param->_nb_context);
117	ALLOC1_SC_SIGNAL(out_SPR_EVENT_SR_DSX ,"out_SPR_EVENT_SR_DSX ",Tcontrol_t ,_param->_nb_context);
118	ALLOC1_SC_SIGNAL(out_SPR_EVENT_SR_TO_ESR ,"out_SPR_EVENT_SR_TO_ESR ",Tcontrol_t ,_param->_nb_context);
119	ALLOC1_SC_SIGNAL( in_NB_INST_COMMIT_ALL ," in_NB_INST_COMMIT_ALL ",Tcounter_t ,_param->_nb_context);
120	ALLOC1_SC_SIGNAL( in_NB_INST_COMMIT_MEM ," in_NB_INST_COMMIT_MEM ",Tcounter_t ,_param->_nb_context);
121	ALLOC1_SC_SIGNAL(out_NB_INST_DECOD_ALL ,"out_NB_INST_DECOD_ALL ",Tcounter_t ,_param->_nb_context);
122	ALLOC1_SC_SIGNAL(out_DEPTH_MIN ,"out_DEPTH_MIN ",Tdepth_t ,_param->_nb_context);
123	ALLOC1_SC_SIGNAL(out_DEPTH_MAX ,"out_DEPTH_MAX ",Tdepth_t ,_param->_nb_context);
124	ALLOC1_SC_SIGNAL(out_DEPTH_FULL ,"out_DEPTH_FULL ",Tcontrol_t ,_param->_nb_context);
125	ALLOC1_SC_SIGNAL( in_SPR_SR_IEE ," in_SPR_SR_IEE ",Tcontrol_t ,_param->_nb_context);
126	ALLOC1_SC_SIGNAL( in_SPR_SR_EPH ," in_SPR_SR_EPH ",Tcontrol_t ,_param->_nb_context);
127	ALLOC1_SC_SIGNAL( in_INTERRUPT_ENABLE ," in_INTERRUPT_ENABLE ",Tcontrol_t ,_param->_nb_context);
128
129	/********************************************************
130	* Instanciation
131	********************************************************/
132
133	msg(_("<%s> : Instanciation of _Front_end.\n"),name.c_str());
134
135	((_Front_end->in_CLOCK)) ((in_CLOCK));
136	((_Front_end->in_NRESET)) ((in_NRESET));
137
138	INSTANCE1_SC_SIGNAL(_Front_end,out_ICACHE_REQ_VAL ,_param->_nb_context);
139	INSTANCE1_SC_SIGNAL(_Front_end, in_ICACHE_REQ_ACK ,_param->_nb_context);
140	//INSTANCE1_SC_SIGNAL(_Front_end,out_ICACHE_REQ_THREAD_ID ,_param->_nb_context);
141	if (_param->_have_port_ifetch_queue_ptr)
142	INSTANCE1_SC_SIGNAL(_Front_end,out_ICACHE_REQ_PACKET_ID ,_param->_nb_context);
143	INSTANCE1_SC_SIGNAL(_Front_end,out_ICACHE_REQ_ADDRESS ,_param->_nb_context);
144	INSTANCE1_SC_SIGNAL(_Front_end,out_ICACHE_REQ_TYPE ,_param->_nb_context);
145	INSTANCE1_SC_SIGNAL(_Front_end, in_ICACHE_RSP_VAL ,_param->_nb_context);
146	INSTANCE1_SC_SIGNAL(_Front_end,out_ICACHE_RSP_ACK ,_param->_nb_context);
147	//INSTANCE1_SC_SIGNAL(_Front_end, in_ICACHE_RSP_THREAD_ID ,_param->_nb_context);
148	if (_param->_have_port_ifetch_queue_ptr)
149	INSTANCE1_SC_SIGNAL(_Front_end, in_ICACHE_RSP_PACKET_ID ,_param->_nb_context);
150	INSTANCE2_SC_SIGNAL(_Front_end, in_ICACHE_RSP_INSTRUCTION ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
151	INSTANCE1_SC_SIGNAL(_Front_end, in_ICACHE_RSP_ERROR ,_param->_nb_context);
152	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_VAL ,_param->_sum_inst_decod);
153	INSTANCE1_SC_SIGNAL(_Front_end, in_DECOD_ACK ,_param->_sum_inst_decod);
154	if (_param->_have_port_context_id)
155	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_CONTEXT_ID ,_param->_sum_inst_decod);
156	if (_param->_have_port_depth)
157	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_DEPTH ,_param->_sum_inst_decod);
158	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_TYPE ,_param->_sum_inst_decod);
159	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_OPERATION ,_param->_sum_inst_decod);
160	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_NO_EXECUTE ,_param->_sum_inst_decod);
161	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_IS_DELAY_SLOT ,_param->_sum_inst_decod);
162	#ifdef DEBUG
163	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_ADDRESS ,_param->_sum_inst_decod);
164	#endif
165	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_ADDRESS_NEXT ,_param->_sum_inst_decod);
166	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_HAS_IMMEDIAT ,_param->_sum_inst_decod);
167	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_IMMEDIAT ,_param->_sum_inst_decod);
168	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_READ_RA ,_param->_sum_inst_decod);
169	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_NUM_REG_RA ,_param->_sum_inst_decod);
170	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_READ_RB ,_param->_sum_inst_decod);
171	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_NUM_REG_RB ,_param->_sum_inst_decod);
172	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_READ_RC ,_param->_sum_inst_decod);
173	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_NUM_REG_RC ,_param->_sum_inst_decod);
174	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_WRITE_RD ,_param->_sum_inst_decod);
175	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_NUM_REG_RD ,_param->_sum_inst_decod);
176	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_WRITE_RE ,_param->_sum_inst_decod);
177	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_NUM_REG_RE ,_param->_sum_inst_decod);
178	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_EXCEPTION_USE ,_param->_sum_inst_decod);
179	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_EXCEPTION ,_param->_sum_inst_decod);
180	INSTANCE1_SC_SIGNAL(_Front_end, in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete);
181	INSTANCE1_SC_SIGNAL(_Front_end,out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete);
182	if (_param->_have_port_context_id)
183	INSTANCE1_SC_SIGNAL(_Front_end, in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete);
184	if (_param->_have_port_depth)
185	INSTANCE1_SC_SIGNAL(_Front_end, in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete);
186	INSTANCE1_SC_SIGNAL(_Front_end, in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete);
187	INSTANCE1_SC_SIGNAL(_Front_end, in_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete);
188	INSTANCE1_SC_SIGNAL(_Front_end,out_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete);
189	INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_VAL );
190	INSTANCE0_SC_SIGNAL(_Front_end,out_COMMIT_EVENT_ACK );
191	if (_param->_have_port_context_id)
192	INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_CONTEXT_ID );
193	if (_param->_have_port_depth)
194	INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_DEPTH );
195	INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_TYPE );
196	INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_IS_DELAY_SLOT );
197	INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_ADDRESS );
198	INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_ADDRESS_EPCR_VAL );
199	INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_ADDRESS_EPCR );
200	INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_ADDRESS_EEAR_VAL );
201	INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_ADDRESS_EEAR );
202	INSTANCE1_SC_SIGNAL(_Front_end,out_EVENT_VAL ,_param->_nb_context);
203	INSTANCE1_SC_SIGNAL(_Front_end, in_EVENT_ACK ,_param->_nb_context);
204	INSTANCE1_SC_SIGNAL(_Front_end,out_EVENT_ADDRESS ,_param->_nb_context);
205	INSTANCE1_SC_SIGNAL(_Front_end,out_EVENT_ADDRESS_NEXT ,_param->_nb_context);
206	INSTANCE1_SC_SIGNAL(_Front_end,out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context);
207	INSTANCE1_SC_SIGNAL(_Front_end,out_EVENT_IS_DS_TAKE ,_param->_nb_context);
208	INSTANCE1_SC_SIGNAL(_Front_end,out_SPR_EVENT_VAL ,_param->_nb_context);
209	INSTANCE1_SC_SIGNAL(_Front_end, in_SPR_EVENT_ACK ,_param->_nb_context);
210	INSTANCE1_SC_SIGNAL(_Front_end,out_SPR_EVENT_EPCR ,_param->_nb_context);
211	INSTANCE1_SC_SIGNAL(_Front_end,out_SPR_EVENT_EEAR_WEN ,_param->_nb_context);
212	INSTANCE1_SC_SIGNAL(_Front_end,out_SPR_EVENT_EEAR ,_param->_nb_context);
213	INSTANCE1_SC_SIGNAL(_Front_end,out_SPR_EVENT_SR_DSX ,_param->_nb_context);
214	INSTANCE1_SC_SIGNAL(_Front_end,out_SPR_EVENT_SR_TO_ESR ,_param->_nb_context);
215	INSTANCE1_SC_SIGNAL(_Front_end, in_NB_INST_COMMIT_ALL ,_param->_nb_context);
216	INSTANCE1_SC_SIGNAL(_Front_end, in_NB_INST_COMMIT_MEM ,_param->_nb_context);
217	INSTANCE1_SC_SIGNAL(_Front_end,out_NB_INST_DECOD_ALL ,_param->_nb_context);
218	if (_param->_have_port_depth)
219	{
220	INSTANCE1_SC_SIGNAL(_Front_end,out_DEPTH_MIN ,_param->_nb_context);
221	INSTANCE1_SC_SIGNAL(_Front_end,out_DEPTH_MAX ,_param->_nb_context);
222	}
223	INSTANCE1_SC_SIGNAL(_Front_end,out_DEPTH_FULL ,_param->_nb_context);
224	INSTANCE1_SC_SIGNAL(_Front_end, in_SPR_SR_IEE ,_param->_nb_context);
225	INSTANCE1_SC_SIGNAL(_Front_end, in_SPR_SR_EPH ,_param->_nb_context);
226	INSTANCE1_SC_SIGNAL(_Front_end, in_INTERRUPT_ENABLE ,_param->_nb_context);
227
228	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
229
230	Time * _time = new Time();
231
232	/********************************************************
233	* Simulation - Begin
234	********************************************************/
235
236	// Initialisation
237
238	const uint32_t seed = 0;
239	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
240
241	srand(seed);
242
243	SC_START(0);
244	LABEL("Initialisation");
245
246	for (uint32_t i=0; i<_param->_nb_context; ++i)
247	{
248	in_ICACHE_REQ_ACK [i]->write(0);
249	in_ICACHE_RSP_VAL [i]->write(0);
250	in_EVENT_ACK [i]->write(0);
251	in_SPR_EVENT_ACK [i]->write(0);
252	in_NB_INST_COMMIT_ALL [i]->write(0); // no inst
253	in_NB_INST_COMMIT_MEM [i]->write(0); // no inst
254	in_SPR_SR_IEE [i]->write(0); // interrupt disable
255	in_SPR_SR_EPH [i]->write(0); // exception msb = 0
256	in_INTERRUPT_ENABLE [i]->write(0); // no interrupt
257	}
258	for (uint32_t i=0; i<_param->_sum_inst_decod; ++i)
259	in_DECOD_ACK [i]->write(0);
260	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i)
261	in_BRANCH_COMPLETE_VAL [i]->write(0);
262	in_COMMIT_EVENT_VAL->write(0);
263
264
265	for (uint32_t i=0; i<_param->_nb_context; ++i)
266	{
267	TEST(Tcontrol_t,out_ICACHE_REQ_VAL [i]->read(),0);
268	TEST(Tcontrol_t,out_ICACHE_RSP_ACK [i]->read(),1); // Can accept a respons
269	TEST(Tcontrol_t,out_EVENT_VAL [i]->read(),0);
270	TEST(Tcontrol_t,out_SPR_EVENT_VAL [i]->read(),0);
271	TEST(Tdepth_t ,out_DEPTH_MIN [i]->read(),0); // no branch speculated
272	TEST(Tdepth_t ,out_DEPTH_MAX [i]->read(),0); // no branch speculated
273	TEST(Tdepth_t ,out_DEPTH_FULL [i]->read(),0); // no branch speculated
274	}
275	for (uint32_t i=0; i<_param->_sum_inst_decod; ++i)
276	TEST(Tcontrol_t,out_DECOD_VAL [i]->read(),0);
277	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i)
278	TEST(Tcontrol_t,out_BRANCH_COMPLETE_ACK [i]->read(),0); // can't accept (interactive)
279	TEST(Tcontrol_t,out_COMMIT_EVENT_ACK ->read(),1); // can accept
280
281	LABEL("Reset");
282	in_NRESET->write(0);
283	SC_START(5);
284	in_NRESET->write(1);
285
286	LABEL("Loop of Test");
287
288	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
289	{
290	LABEL("Iteration %d",iteration);
291
292	SC_START(1);
293	}
294
295	/********************************************************
296	* Simulation - End
297	********************************************************/
298
299	TEST_OK ("End of Simulation");
300	delete _time;
301
302	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
303
304	delete in_CLOCK;
305	delete in_NRESET;
306
307	DELETE1_SC_SIGNAL(out_ICACHE_REQ_VAL ,_param->_nb_context);
308	DELETE1_SC_SIGNAL( in_ICACHE_REQ_ACK ,_param->_nb_context);
309	//DELETE1_SC_SIGNAL(out_ICACHE_REQ_THREAD_ID ,_param->_nb_context);
310	DELETE1_SC_SIGNAL(out_ICACHE_REQ_PACKET_ID ,_param->_nb_context);
311	DELETE1_SC_SIGNAL(out_ICACHE_REQ_ADDRESS ,_param->_nb_context);
312	DELETE1_SC_SIGNAL(out_ICACHE_REQ_TYPE ,_param->_nb_context);
313	DELETE1_SC_SIGNAL( in_ICACHE_RSP_VAL ,_param->_nb_context);
314	DELETE1_SC_SIGNAL(out_ICACHE_RSP_ACK ,_param->_nb_context);
315	//DELETE1_SC_SIGNAL( in_ICACHE_RSP_THREAD_ID ,_param->_nb_context);
316	DELETE1_SC_SIGNAL( in_ICACHE_RSP_PACKET_ID ,_param->_nb_context);
317	DELETE2_SC_SIGNAL( in_ICACHE_RSP_INSTRUCTION ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
318	DELETE1_SC_SIGNAL( in_ICACHE_RSP_ERROR ,_param->_nb_context);
319	DELETE1_SC_SIGNAL(out_DECOD_VAL ,_param->_sum_inst_decod);
320	DELETE1_SC_SIGNAL( in_DECOD_ACK ,_param->_sum_inst_decod);
321	DELETE1_SC_SIGNAL(out_DECOD_CONTEXT_ID ,_param->_sum_inst_decod);
322	DELETE1_SC_SIGNAL(out_DECOD_DEPTH ,_param->_sum_inst_decod);
323	DELETE1_SC_SIGNAL(out_DECOD_TYPE ,_param->_sum_inst_decod);
324	DELETE1_SC_SIGNAL(out_DECOD_OPERATION ,_param->_sum_inst_decod);
325	DELETE1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,_param->_sum_inst_decod);
326	DELETE1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,_param->_sum_inst_decod);
327	#ifdef DEBUG
328	DELETE1_SC_SIGNAL(out_DECOD_ADDRESS ,_param->_sum_inst_decod);
329	#endif
330	DELETE1_SC_SIGNAL(out_DECOD_ADDRESS_NEXT ,_param->_sum_inst_decod);
331	DELETE1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT ,_param->_sum_inst_decod);
332	DELETE1_SC_SIGNAL(out_DECOD_IMMEDIAT ,_param->_sum_inst_decod);
333	DELETE1_SC_SIGNAL(out_DECOD_READ_RA ,_param->_sum_inst_decod);
334	DELETE1_SC_SIGNAL(out_DECOD_NUM_REG_RA ,_param->_sum_inst_decod);
335	DELETE1_SC_SIGNAL(out_DECOD_READ_RB ,_param->_sum_inst_decod);
336	DELETE1_SC_SIGNAL(out_DECOD_NUM_REG_RB ,_param->_sum_inst_decod);
337	DELETE1_SC_SIGNAL(out_DECOD_READ_RC ,_param->_sum_inst_decod);
338	DELETE1_SC_SIGNAL(out_DECOD_NUM_REG_RC ,_param->_sum_inst_decod);
339	DELETE1_SC_SIGNAL(out_DECOD_WRITE_RD ,_param->_sum_inst_decod);
340	DELETE1_SC_SIGNAL(out_DECOD_NUM_REG_RD ,_param->_sum_inst_decod);
341	DELETE1_SC_SIGNAL(out_DECOD_WRITE_RE ,_param->_sum_inst_decod);
342	DELETE1_SC_SIGNAL(out_DECOD_NUM_REG_RE ,_param->_sum_inst_decod);
343	DELETE1_SC_SIGNAL(out_DECOD_EXCEPTION_USE ,_param->_sum_inst_decod);
344	DELETE1_SC_SIGNAL(out_DECOD_EXCEPTION ,_param->_sum_inst_decod);
345	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete);
346	DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete);
347	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete);
348	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete);
349	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete);
350	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete);
351	DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete);
352	DELETE0_SC_SIGNAL( in_COMMIT_EVENT_VAL );
353	DELETE0_SC_SIGNAL(out_COMMIT_EVENT_ACK );
354	DELETE0_SC_SIGNAL( in_COMMIT_EVENT_CONTEXT_ID );
355	DELETE0_SC_SIGNAL( in_COMMIT_EVENT_DEPTH );
356	DELETE0_SC_SIGNAL( in_COMMIT_EVENT_TYPE );
357	DELETE0_SC_SIGNAL( in_COMMIT_EVENT_IS_DELAY_SLOT );
358	DELETE0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS );
359	DELETE0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR_VAL );
360	DELETE0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR );
361	DELETE0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR_VAL );
362	DELETE0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR );
363	DELETE1_SC_SIGNAL(out_EVENT_VAL ,_param->_nb_context);
364	DELETE1_SC_SIGNAL( in_EVENT_ACK ,_param->_nb_context);
365	DELETE1_SC_SIGNAL(out_EVENT_ADDRESS ,_param->_nb_context);
366	DELETE1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT ,_param->_nb_context);
367	DELETE1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context);
368	DELETE1_SC_SIGNAL(out_EVENT_IS_DS_TAKE ,_param->_nb_context);
369	DELETE1_SC_SIGNAL(out_SPR_EVENT_VAL ,_param->_nb_context);
370	DELETE1_SC_SIGNAL( in_SPR_EVENT_ACK ,_param->_nb_context);
371	DELETE1_SC_SIGNAL(out_SPR_EVENT_EPCR ,_param->_nb_context);
372	DELETE1_SC_SIGNAL(out_SPR_EVENT_EEAR_WEN ,_param->_nb_context);
373	DELETE1_SC_SIGNAL(out_SPR_EVENT_EEAR ,_param->_nb_context);
374	DELETE1_SC_SIGNAL(out_SPR_EVENT_SR_DSX ,_param->_nb_context);
375	DELETE1_SC_SIGNAL(out_SPR_EVENT_SR_TO_ESR ,_param->_nb_context);
376	DELETE1_SC_SIGNAL( in_NB_INST_COMMIT_ALL ,_param->_nb_context);
377	DELETE1_SC_SIGNAL( in_NB_INST_COMMIT_MEM ,_param->_nb_context);
378	DELETE1_SC_SIGNAL(out_NB_INST_DECOD_ALL ,_param->_nb_context);
379	DELETE1_SC_SIGNAL(out_DEPTH_MIN ,_param->_nb_context);
380	DELETE1_SC_SIGNAL(out_DEPTH_MAX ,_param->_nb_context);
381	DELETE1_SC_SIGNAL(out_DEPTH_FULL ,_param->_nb_context);
382	DELETE1_SC_SIGNAL( in_SPR_SR_IEE ,_param->_nb_context);
383	DELETE1_SC_SIGNAL( in_SPR_SR_EPH ,_param->_nb_context);
384	DELETE1_SC_SIGNAL( in_INTERRUPT_ENABLE ,_param->_nb_context);
385	}
386	#endif
387
388	delete _Front_end;
389	#ifdef STATISTICS
390	delete _parameters_statistics;
391	#endif
392	}

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