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test.cpp @ 131

Last change on this file since 131 was 131, checked in by rosiere, 15 years ago
1) add constant method 2) test with systemc 2.2.0
Property svn:keywords set to `Id`
File size: 33.6 KB

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1	/*
2	* $Id: test.cpp 131 2009-07-08 18:40:08Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#include "Behavioural/Core/Multi_Front_end/Front_end/SelfTest/include/test.h"
10	#include "Behavioural/include/Allocation.h"
11
12	void test (string name,
13	morpheo::behavioural::core::multi_front_end::front_end::Parameters * _param)
14	{
15	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
16
17	#ifdef STATISTICS
18	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX);
19	#endif
20
21	Tusage_t _usage = USE_ALL;
22
23	// _usage = usage_unset(_usage,USE_SYSTEMC );
24	// _usage = usage_unset(_usage,USE_VHDL );
25	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
26	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
27	// _usage = usage_unset(_usage,USE_POSITION );
28	// _usage = usage_unset(_usage,USE_STATISTICS );
29	// _usage = usage_unset(_usage,USE_INFORMATION );
30
31	Front_end * _Front_end = new Front_end
32	(name.c_str(),
33	#ifdef STATISTICS
34	_parameters_statistics,
35	#endif
36	_param,
37	_usage);
38
39	#ifdef SYSTEMC
40	if (usage_is_set(_usage,USE_SYSTEMC))
41	{
42	/*********************************************************************
43	* Déclarations des signaux
44	*********************************************************************/
45	string rename;
46
47	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
48	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
49
50	sc_signal<Tcontrol_t > ** out_ICACHE_REQ_VAL ;
51	sc_signal<Tcontrol_t > ** in_ICACHE_REQ_ACK ;
52	//sc_signal<Tcontext_t > ** out_ICACHE_REQ_THREAD_ID ;
53	sc_signal<Tpacket_t > ** out_ICACHE_REQ_PACKET_ID ;
54	sc_signal<Ticache_instruction_t> ** out_ICACHE_REQ_ADDRESS ;
55	sc_signal<Ticache_type_t > ** out_ICACHE_REQ_TYPE ;
56	sc_signal<Tcontrol_t > ** in_ICACHE_RSP_VAL ;
57	sc_signal<Tcontrol_t > ** out_ICACHE_RSP_ACK ;
58	//sc_signal<Tcontext_t > ** in_ICACHE_RSP_THREAD_ID ;
59	sc_signal<Tpacket_t > ** in_ICACHE_RSP_PACKET_ID ;
60	sc_signal<Ticache_instruction_t> *** in_ICACHE_RSP_INSTRUCTION ;
61	sc_signal<Ticache_error_t > ** in_ICACHE_RSP_ERROR ;
62	sc_signal<Tcontrol_t > ** out_DECOD_VAL ;
63	sc_signal<Tcontrol_t > ** in_DECOD_ACK ;
64	sc_signal<Tcontext_t > ** out_DECOD_CONTEXT_ID ;
65	sc_signal<Tdepth_t > ** out_DECOD_DEPTH ;
66	sc_signal<Ttype_t > ** out_DECOD_TYPE ;
67	sc_signal<Toperation_t > ** out_DECOD_OPERATION ;
68	sc_signal<Tcontrol_t > ** out_DECOD_NO_EXECUTE ;
69	sc_signal<Tcontrol_t > ** out_DECOD_LAST_EVENT ;
70	sc_signal<Tcontrol_t > ** out_DECOD_IS_DELAY_SLOT ;
71	sc_signal<Tgeneral_data_t > ** out_DECOD_ADDRESS ;
72	sc_signal<Tgeneral_data_t > ** out_DECOD_ADDRESS_NEXT ;
73	sc_signal<Tcontrol_t > ** out_DECOD_HAS_IMMEDIAT ;
74	sc_signal<Tgeneral_data_t > ** out_DECOD_IMMEDIAT ;
75	sc_signal<Tcontrol_t > ** out_DECOD_READ_RA ;
76	sc_signal<Tgeneral_address_t > ** out_DECOD_NUM_REG_RA ;
77	sc_signal<Tcontrol_t > ** out_DECOD_READ_RB ;
78	sc_signal<Tgeneral_address_t > ** out_DECOD_NUM_REG_RB ;
79	sc_signal<Tcontrol_t > ** out_DECOD_READ_RC ;
80	sc_signal<Tspecial_address_t > ** out_DECOD_NUM_REG_RC ;
81	sc_signal<Tcontrol_t > ** out_DECOD_WRITE_RD ;
82	sc_signal<Tgeneral_address_t > ** out_DECOD_NUM_REG_RD ;
83	sc_signal<Tcontrol_t > ** out_DECOD_WRITE_RE ;
84	sc_signal<Tspecial_address_t > ** out_DECOD_NUM_REG_RE ;
85	sc_signal<Texception_t > ** out_DECOD_EXCEPTION_USE ;
86	sc_signal<Texception_t > ** out_DECOD_EXCEPTION ;
87	sc_signal<Tcontrol_t > ** in_BRANCH_COMPLETE_VAL ;
88	sc_signal<Tcontrol_t > ** out_BRANCH_COMPLETE_ACK ;
89	sc_signal<Tcontext_t > ** in_BRANCH_COMPLETE_CONTEXT_ID ;
90	sc_signal<Tdepth_t > ** in_BRANCH_COMPLETE_DEPTH ;
91	sc_signal<Taddress_t > ** in_BRANCH_COMPLETE_ADDRESS ;
92	sc_signal<Tcontrol_t > ** in_BRANCH_COMPLETE_NO_SEQUENCE ;
93	sc_signal<Tcontrol_t > ** out_BRANCH_COMPLETE_MISS_PREDICTION;
94	sc_signal<Tcontrol_t > * in_COMMIT_EVENT_VAL ;
95	sc_signal<Tcontrol_t > * out_COMMIT_EVENT_ACK ;
96	sc_signal<Tcontext_t > * in_COMMIT_EVENT_CONTEXT_ID ;
97	sc_signal<Tdepth_t > * in_COMMIT_EVENT_DEPTH ;
98	sc_signal<Tevent_type_t > * in_COMMIT_EVENT_TYPE ;
99	sc_signal<Tcontrol_t > * in_COMMIT_EVENT_IS_DELAY_SLOT ;
100	sc_signal<Taddress_t > * in_COMMIT_EVENT_ADDRESS ;
101	sc_signal<Tcontrol_t > * in_COMMIT_EVENT_ADDRESS_EPCR_VAL ;
102	sc_signal<Taddress_t > * in_COMMIT_EVENT_ADDRESS_EPCR ;
103	sc_signal<Tcontrol_t > * in_COMMIT_EVENT_ADDRESS_EEAR_VAL ;
104	sc_signal<Tgeneral_data_t > * in_COMMIT_EVENT_ADDRESS_EEAR ;
105	sc_signal<Tcontrol_t > ** out_EVENT_VAL ;
106	sc_signal<Tcontrol_t > ** in_EVENT_ACK ;
107	sc_signal<Taddress_t > ** out_EVENT_ADDRESS ;
108	sc_signal<Taddress_t > ** out_EVENT_ADDRESS_NEXT ;
109	sc_signal<Tcontrol_t > ** out_EVENT_ADDRESS_NEXT_VAL ;
110	sc_signal<Tcontrol_t > ** out_EVENT_IS_DS_TAKE ;
111	sc_signal<Tcontrol_t > ** out_SPR_EVENT_VAL ;
112	sc_signal<Tcontrol_t > ** in_SPR_EVENT_ACK ;
113	sc_signal<Tspr_t > ** out_SPR_EVENT_EPCR ;
114	sc_signal<Tcontrol_t > ** out_SPR_EVENT_EEAR_WEN ;
115	sc_signal<Tspr_t > ** out_SPR_EVENT_EEAR ;
116	sc_signal<Tcontrol_t > ** out_SPR_EVENT_SR_DSX ;
117	sc_signal<Tcontrol_t > ** out_SPR_EVENT_SR_TO_ESR ;
118	sc_signal<Tcounter_t > ** in_NB_INST_COMMIT_ALL ;
119	sc_signal<Tcounter_t > ** in_NB_INST_COMMIT_MEM ;
120	sc_signal<Tcounter_t > ** out_NB_INST_DECOD_ALL ;
121	sc_signal<Tdepth_t > ** out_DEPTH_MIN ;
122	sc_signal<Tdepth_t > ** out_DEPTH_MAX ;
123	sc_signal<Tcontrol_t > ** out_DEPTH_FULL ;
124	sc_signal<Tcontrol_t > ** in_SPR_SR_IEE ;
125	sc_signal<Tcontrol_t > ** in_SPR_SR_EPH ;
126	sc_signal<Tcontrol_t > ** in_INTERRUPT_ENABLE ;
127
128	ALLOC1_SC_SIGNAL(out_ICACHE_REQ_VAL ,"out_ICACHE_REQ_VAL ",Tcontrol_t ,_param->_nb_context);
129	ALLOC1_SC_SIGNAL( in_ICACHE_REQ_ACK ," in_ICACHE_REQ_ACK ",Tcontrol_t ,_param->_nb_context);
130	//ALLOC1_SC_SIGNAL(out_ICACHE_REQ_THREAD_ID ,"out_ICACHE_REQ_THREAD_ID ",Tcontext_t ,_param->_nb_context);
131	ALLOC1_SC_SIGNAL(out_ICACHE_REQ_PACKET_ID ,"out_ICACHE_REQ_PACKET_ID ",Tpacket_t ,_param->_nb_context);
132	ALLOC1_SC_SIGNAL(out_ICACHE_REQ_ADDRESS ,"out_ICACHE_REQ_ADDRESS ",Ticache_instruction_t,_param->_nb_context);
133	ALLOC1_SC_SIGNAL(out_ICACHE_REQ_TYPE ,"out_ICACHE_REQ_TYPE ",Ticache_type_t ,_param->_nb_context);
134	ALLOC1_SC_SIGNAL( in_ICACHE_RSP_VAL ," in_ICACHE_RSP_VAL ",Tcontrol_t ,_param->_nb_context);
135	ALLOC1_SC_SIGNAL(out_ICACHE_RSP_ACK ,"out_ICACHE_RSP_ACK ",Tcontrol_t ,_param->_nb_context);
136	//ALLOC1_SC_SIGNAL( in_ICACHE_RSP_THREAD_ID ," in_ICACHE_RSP_THREAD_ID ",Tcontext_t ,_param->_nb_context);
137	ALLOC1_SC_SIGNAL( in_ICACHE_RSP_PACKET_ID ," in_ICACHE_RSP_PACKET_ID ",Tpacket_t ,_param->_nb_context);
138	ALLOC2_SC_SIGNAL( in_ICACHE_RSP_INSTRUCTION ," in_ICACHE_RSP_INSTRUCTION ",Ticache_instruction_t,_param->_nb_context,_param->_nb_inst_fetch[it1]);
139	ALLOC1_SC_SIGNAL( in_ICACHE_RSP_ERROR ," in_ICACHE_RSP_ERROR ",Ticache_error_t ,_param->_nb_context);
140	ALLOC1_SC_SIGNAL(out_DECOD_VAL ,"out_DECOD_VAL ",Tcontrol_t ,_param->_sum_inst_decod);
141	ALLOC1_SC_SIGNAL( in_DECOD_ACK ," in_DECOD_ACK ",Tcontrol_t ,_param->_sum_inst_decod);
142	ALLOC1_SC_SIGNAL(out_DECOD_CONTEXT_ID ,"out_DECOD_CONTEXT_ID ",Tcontext_t ,_param->_sum_inst_decod);
143	ALLOC1_SC_SIGNAL(out_DECOD_DEPTH ,"out_DECOD_DEPTH ",Tdepth_t ,_param->_sum_inst_decod);
144	ALLOC1_SC_SIGNAL(out_DECOD_TYPE ,"out_DECOD_TYPE ",Ttype_t ,_param->_sum_inst_decod);
145	ALLOC1_SC_SIGNAL(out_DECOD_OPERATION ,"out_DECOD_OPERATION ",Toperation_t ,_param->_sum_inst_decod);
146	ALLOC1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,"out_DECOD_NO_EXECUTE ",Tcontrol_t ,_param->_sum_inst_decod);
147	ALLOC1_SC_SIGNAL(out_DECOD_LAST_EVENT ,"out_DECOD_LAST_EVENT ",Tcontrol_t ,_param->_sum_inst_decod);
148	ALLOC1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,"out_DECOD_IS_DELAY_SLOT ",Tcontrol_t ,_param->_sum_inst_decod);
149	ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS ,"out_DECOD_ADDRESS ",Tgeneral_data_t ,_param->_sum_inst_decod);
150	ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS_NEXT ,"out_DECOD_ADDRESS_NEXT ",Tgeneral_data_t ,_param->_sum_inst_decod);
151	ALLOC1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT ,"out_DECOD_HAS_IMMEDIAT ",Tcontrol_t ,_param->_sum_inst_decod);
152	ALLOC1_SC_SIGNAL(out_DECOD_IMMEDIAT ,"out_DECOD_IMMEDIAT ",Tgeneral_data_t ,_param->_sum_inst_decod);
153	ALLOC1_SC_SIGNAL(out_DECOD_READ_RA ,"out_DECOD_READ_RA ",Tcontrol_t ,_param->_sum_inst_decod);
154	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RA ,"out_DECOD_NUM_REG_RA ",Tgeneral_address_t ,_param->_sum_inst_decod);
155	ALLOC1_SC_SIGNAL(out_DECOD_READ_RB ,"out_DECOD_READ_RB ",Tcontrol_t ,_param->_sum_inst_decod);
156	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RB ,"out_DECOD_NUM_REG_RB ",Tgeneral_address_t ,_param->_sum_inst_decod);
157	ALLOC1_SC_SIGNAL(out_DECOD_READ_RC ,"out_DECOD_READ_RC ",Tcontrol_t ,_param->_sum_inst_decod);
158	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RC ,"out_DECOD_NUM_REG_RC ",Tspecial_address_t ,_param->_sum_inst_decod);
159	ALLOC1_SC_SIGNAL(out_DECOD_WRITE_RD ,"out_DECOD_WRITE_RD ",Tcontrol_t ,_param->_sum_inst_decod);
160	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RD ,"out_DECOD_NUM_REG_RD ",Tgeneral_address_t ,_param->_sum_inst_decod);
161	ALLOC1_SC_SIGNAL(out_DECOD_WRITE_RE ,"out_DECOD_WRITE_RE ",Tcontrol_t ,_param->_sum_inst_decod);
162	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RE ,"out_DECOD_NUM_REG_RE ",Tspecial_address_t ,_param->_sum_inst_decod);
163	ALLOC1_SC_SIGNAL(out_DECOD_EXCEPTION_USE ,"out_DECOD_EXCEPTION_USE ",Texception_t ,_param->_sum_inst_decod);
164	ALLOC1_SC_SIGNAL(out_DECOD_EXCEPTION ,"out_DECOD_EXCEPTION ",Texception_t ,_param->_sum_inst_decod);
165	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ," in_BRANCH_COMPLETE_VAL ",Tcontrol_t ,_param->_nb_inst_branch_complete);
166	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,"out_BRANCH_COMPLETE_ACK ",Tcontrol_t ,_param->_nb_inst_branch_complete);
167	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ," in_BRANCH_COMPLETE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_branch_complete);
168	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ," in_BRANCH_COMPLETE_DEPTH ",Tdepth_t ,_param->_nb_inst_branch_complete);
169	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ," in_BRANCH_COMPLETE_ADDRESS ",Taddress_t ,_param->_nb_inst_branch_complete);
170	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_NO_SEQUENCE ," in_BRANCH_COMPLETE_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_inst_branch_complete);
171	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION,"out_BRANCH_COMPLETE_MISS_PREDICTION",Tcontrol_t ,_param->_nb_inst_branch_complete);
172	ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_VAL ," in_COMMIT_EVENT_VAL ",Tcontrol_t );
173	ALLOC0_SC_SIGNAL(out_COMMIT_EVENT_ACK ,"out_COMMIT_EVENT_ACK ",Tcontrol_t );
174	ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_CONTEXT_ID ," in_COMMIT_EVENT_CONTEXT_ID ",Tcontext_t );
175	ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_DEPTH ," in_COMMIT_EVENT_DEPTH ",Tdepth_t );
176	ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_TYPE ," in_COMMIT_EVENT_TYPE ",Tevent_type_t );
177	ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_IS_DELAY_SLOT ," in_COMMIT_EVENT_IS_DELAY_SLOT ",Tcontrol_t );
178	ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS ," in_COMMIT_EVENT_ADDRESS ",Taddress_t );
179	ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR_VAL ," in_COMMIT_EVENT_ADDRESS_EPCR_VAL ",Tcontrol_t );
180	ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR ," in_COMMIT_EVENT_ADDRESS_EPCR ",Taddress_t );
181	ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ," in_COMMIT_EVENT_ADDRESS_EEAR_VAL ",Tcontrol_t );
182	ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR ," in_COMMIT_EVENT_ADDRESS_EEAR ",Tgeneral_data_t );
183	ALLOC1_SC_SIGNAL(out_EVENT_VAL ,"out_EVENT_VAL ",Tcontrol_t ,_param->_nb_context);
184	ALLOC1_SC_SIGNAL( in_EVENT_ACK ," in_EVENT_ACK ",Tcontrol_t ,_param->_nb_context);
185	ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS ,"out_EVENT_ADDRESS ",Taddress_t ,_param->_nb_context);
186	ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT ,"out_EVENT_ADDRESS_NEXT ",Taddress_t ,_param->_nb_context);
187	ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,"out_EVENT_ADDRESS_NEXT_VAL ",Tcontrol_t ,_param->_nb_context);
188	ALLOC1_SC_SIGNAL(out_EVENT_IS_DS_TAKE ,"out_EVENT_IS_DS_TAKE ",Tcontrol_t ,_param->_nb_context);
189	ALLOC1_SC_SIGNAL(out_SPR_EVENT_VAL ,"out_SPR_EVENT_VAL ",Tcontrol_t ,_param->_nb_context);
190	ALLOC1_SC_SIGNAL( in_SPR_EVENT_ACK ," in_SPR_EVENT_ACK ",Tcontrol_t ,_param->_nb_context);
191	ALLOC1_SC_SIGNAL(out_SPR_EVENT_EPCR ,"out_SPR_EVENT_EPCR ",Tspr_t ,_param->_nb_context);
192	ALLOC1_SC_SIGNAL(out_SPR_EVENT_EEAR_WEN ,"out_SPR_EVENT_EEAR_WEN ",Tcontrol_t ,_param->_nb_context);
193	ALLOC1_SC_SIGNAL(out_SPR_EVENT_EEAR ,"out_SPR_EVENT_EEAR ",Tspr_t ,_param->_nb_context);
194	ALLOC1_SC_SIGNAL(out_SPR_EVENT_SR_DSX ,"out_SPR_EVENT_SR_DSX ",Tcontrol_t ,_param->_nb_context);
195	ALLOC1_SC_SIGNAL(out_SPR_EVENT_SR_TO_ESR ,"out_SPR_EVENT_SR_TO_ESR ",Tcontrol_t ,_param->_nb_context);
196	ALLOC1_SC_SIGNAL( in_NB_INST_COMMIT_ALL ," in_NB_INST_COMMIT_ALL ",Tcounter_t ,_param->_nb_context);
197	ALLOC1_SC_SIGNAL( in_NB_INST_COMMIT_MEM ," in_NB_INST_COMMIT_MEM ",Tcounter_t ,_param->_nb_context);
198	ALLOC1_SC_SIGNAL(out_NB_INST_DECOD_ALL ,"out_NB_INST_DECOD_ALL ",Tcounter_t ,_param->_nb_context);
199	ALLOC1_SC_SIGNAL(out_DEPTH_MIN ,"out_DEPTH_MIN ",Tdepth_t ,_param->_nb_context);
200	ALLOC1_SC_SIGNAL(out_DEPTH_MAX ,"out_DEPTH_MAX ",Tdepth_t ,_param->_nb_context);
201	ALLOC1_SC_SIGNAL(out_DEPTH_FULL ,"out_DEPTH_FULL ",Tcontrol_t ,_param->_nb_context);
202	ALLOC1_SC_SIGNAL( in_SPR_SR_IEE ," in_SPR_SR_IEE ",Tcontrol_t ,_param->_nb_context);
203	ALLOC1_SC_SIGNAL( in_SPR_SR_EPH ," in_SPR_SR_EPH ",Tcontrol_t ,_param->_nb_context);
204	ALLOC1_SC_SIGNAL( in_INTERRUPT_ENABLE ," in_INTERRUPT_ENABLE ",Tcontrol_t ,_param->_nb_context);
205
206	/********************************************************
207	* Instanciation
208	********************************************************/
209
210	msg(_("<%s> : Instanciation of _Front_end.\n"),name.c_str());
211
212	((_Front_end->in_CLOCK)) ((in_CLOCK));
213	((_Front_end->in_NRESET)) ((in_NRESET));
214
215	INSTANCE1_SC_SIGNAL(_Front_end,out_ICACHE_REQ_VAL ,_param->_nb_context);
216	INSTANCE1_SC_SIGNAL(_Front_end, in_ICACHE_REQ_ACK ,_param->_nb_context);
217	//INSTANCE1_SC_SIGNAL(_Front_end,out_ICACHE_REQ_THREAD_ID ,_param->_nb_context);
218	if (_param->_have_port_ifetch_queue_ptr)
219	INSTANCE1_SC_SIGNAL(_Front_end,out_ICACHE_REQ_PACKET_ID ,_param->_nb_context);
220	INSTANCE1_SC_SIGNAL(_Front_end,out_ICACHE_REQ_ADDRESS ,_param->_nb_context);
221	INSTANCE1_SC_SIGNAL(_Front_end,out_ICACHE_REQ_TYPE ,_param->_nb_context);
222	INSTANCE1_SC_SIGNAL(_Front_end, in_ICACHE_RSP_VAL ,_param->_nb_context);
223	INSTANCE1_SC_SIGNAL(_Front_end,out_ICACHE_RSP_ACK ,_param->_nb_context);
224	//INSTANCE1_SC_SIGNAL(_Front_end, in_ICACHE_RSP_THREAD_ID ,_param->_nb_context);
225	if (_param->_have_port_ifetch_queue_ptr)
226	INSTANCE1_SC_SIGNAL(_Front_end, in_ICACHE_RSP_PACKET_ID ,_param->_nb_context);
227	INSTANCE2_SC_SIGNAL(_Front_end, in_ICACHE_RSP_INSTRUCTION ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
228	INSTANCE1_SC_SIGNAL(_Front_end, in_ICACHE_RSP_ERROR ,_param->_nb_context);
229	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_VAL ,_param->_sum_inst_decod);
230	INSTANCE1_SC_SIGNAL(_Front_end, in_DECOD_ACK ,_param->_sum_inst_decod);
231	if (_param->_have_port_context_id)
232	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_CONTEXT_ID ,_param->_sum_inst_decod);
233	if (_param->_have_port_depth)
234	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_DEPTH ,_param->_sum_inst_decod);
235	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_TYPE ,_param->_sum_inst_decod);
236	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_OPERATION ,_param->_sum_inst_decod);
237	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_NO_EXECUTE ,_param->_sum_inst_decod);
238	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_LAST_EVENT ,_param->_sum_inst_decod);
239	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_IS_DELAY_SLOT ,_param->_sum_inst_decod);
240	#ifdef DEBUG
241	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_ADDRESS ,_param->_sum_inst_decod);
242	#endif
243	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_ADDRESS_NEXT ,_param->_sum_inst_decod);
244	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_HAS_IMMEDIAT ,_param->_sum_inst_decod);
245	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_IMMEDIAT ,_param->_sum_inst_decod);
246	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_READ_RA ,_param->_sum_inst_decod);
247	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_NUM_REG_RA ,_param->_sum_inst_decod);
248	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_READ_RB ,_param->_sum_inst_decod);
249	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_NUM_REG_RB ,_param->_sum_inst_decod);
250	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_READ_RC ,_param->_sum_inst_decod);
251	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_NUM_REG_RC ,_param->_sum_inst_decod);
252	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_WRITE_RD ,_param->_sum_inst_decod);
253	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_NUM_REG_RD ,_param->_sum_inst_decod);
254	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_WRITE_RE ,_param->_sum_inst_decod);
255	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_NUM_REG_RE ,_param->_sum_inst_decod);
256	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_EXCEPTION_USE ,_param->_sum_inst_decod);
257	INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_EXCEPTION ,_param->_sum_inst_decod);
258	INSTANCE1_SC_SIGNAL(_Front_end, in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete);
259	INSTANCE1_SC_SIGNAL(_Front_end,out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete);
260	if (_param->_have_port_context_id)
261	INSTANCE1_SC_SIGNAL(_Front_end, in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete);
262	if (_param->_have_port_depth)
263	INSTANCE1_SC_SIGNAL(_Front_end, in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete);
264	INSTANCE1_SC_SIGNAL(_Front_end, in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete);
265	INSTANCE1_SC_SIGNAL(_Front_end, in_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete);
266	INSTANCE1_SC_SIGNAL(_Front_end,out_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete);
267	INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_VAL );
268	INSTANCE0_SC_SIGNAL(_Front_end,out_COMMIT_EVENT_ACK );
269	if (_param->_have_port_context_id)
270	INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_CONTEXT_ID );
271	if (_param->_have_port_depth)
272	INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_DEPTH );
273	INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_TYPE );
274	INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_IS_DELAY_SLOT );
275	INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_ADDRESS );
276	INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_ADDRESS_EPCR_VAL );
277	INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_ADDRESS_EPCR );
278	INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_ADDRESS_EEAR_VAL );
279	INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_ADDRESS_EEAR );
280	INSTANCE1_SC_SIGNAL(_Front_end,out_EVENT_VAL ,_param->_nb_context);
281	INSTANCE1_SC_SIGNAL(_Front_end, in_EVENT_ACK ,_param->_nb_context);
282	INSTANCE1_SC_SIGNAL(_Front_end,out_EVENT_ADDRESS ,_param->_nb_context);
283	INSTANCE1_SC_SIGNAL(_Front_end,out_EVENT_ADDRESS_NEXT ,_param->_nb_context);
284	INSTANCE1_SC_SIGNAL(_Front_end,out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context);
285	INSTANCE1_SC_SIGNAL(_Front_end,out_EVENT_IS_DS_TAKE ,_param->_nb_context);
286	INSTANCE1_SC_SIGNAL(_Front_end,out_SPR_EVENT_VAL ,_param->_nb_context);
287	INSTANCE1_SC_SIGNAL(_Front_end, in_SPR_EVENT_ACK ,_param->_nb_context);
288	INSTANCE1_SC_SIGNAL(_Front_end,out_SPR_EVENT_EPCR ,_param->_nb_context);
289	INSTANCE1_SC_SIGNAL(_Front_end,out_SPR_EVENT_EEAR_WEN ,_param->_nb_context);
290	INSTANCE1_SC_SIGNAL(_Front_end,out_SPR_EVENT_EEAR ,_param->_nb_context);
291	INSTANCE1_SC_SIGNAL(_Front_end,out_SPR_EVENT_SR_DSX ,_param->_nb_context);
292	INSTANCE1_SC_SIGNAL(_Front_end,out_SPR_EVENT_SR_TO_ESR ,_param->_nb_context);
293	INSTANCE1_SC_SIGNAL(_Front_end, in_NB_INST_COMMIT_ALL ,_param->_nb_context);
294	INSTANCE1_SC_SIGNAL(_Front_end, in_NB_INST_COMMIT_MEM ,_param->_nb_context);
295	INSTANCE1_SC_SIGNAL(_Front_end,out_NB_INST_DECOD_ALL ,_param->_nb_context);
296	if (_param->_have_port_depth)
297	{
298	INSTANCE1_SC_SIGNAL(_Front_end,out_DEPTH_MIN ,_param->_nb_context);
299	INSTANCE1_SC_SIGNAL(_Front_end,out_DEPTH_MAX ,_param->_nb_context);
300	}
301	INSTANCE1_SC_SIGNAL(_Front_end,out_DEPTH_FULL ,_param->_nb_context);
302	INSTANCE1_SC_SIGNAL(_Front_end, in_SPR_SR_IEE ,_param->_nb_context);
303	INSTANCE1_SC_SIGNAL(_Front_end, in_SPR_SR_EPH ,_param->_nb_context);
304	INSTANCE1_SC_SIGNAL(_Front_end, in_INTERRUPT_ENABLE ,_param->_nb_context);
305
306	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
307
308	Time * _time = new Time();
309
310	/********************************************************
311	* Simulation - Begin
312	********************************************************/
313
314	// Initialisation
315
316	const uint32_t seed = 0;
317	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
318
319	srand(seed);
320
321	SC_START(0);
322	LABEL("Initialisation");
323
324	// for (uint32_t i=0; i<_param->_nb_context; ++i)
325	// {
326	// in_ICACHE_REQ_ACK [i]->write(0);
327	// in_ICACHE_RSP_VAL [i]->write(0);
328	// in_EVENT_ACK [i]->write(0);
329	// in_SPR_EVENT_ACK [i]->write(0);
330	// in_NB_INST_COMMIT_ALL [i]->write(0); // no inst
331	// in_NB_INST_COMMIT_MEM [i]->write(0); // no inst
332	// in_SPR_SR_IEE [i]->write(0); // interrupt disable
333	// in_SPR_SR_EPH [i]->write(0); // exception msb = 0
334	// in_INTERRUPT_ENABLE [i]->write(0); // no interrupt
335	// }
336	// for (uint32_t i=0; i<_param->_sum_inst_decod; ++i)
337	// in_DECOD_ACK [i]->write(0);
338	// for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i)
339	// in_BRANCH_COMPLETE_VAL [i]->write(0);
340	// in_COMMIT_EVENT_VAL->write(0);
341
342
343	// for (uint32_t i=0; i<_param->_nb_context; ++i)
344	// {
345	// TEST(Tcontrol_t,out_ICACHE_REQ_VAL [i]->read(),0);
346	// TEST(Tcontrol_t,out_ICACHE_RSP_ACK [i]->read(),1); // Can accept a respons
347	// TEST(Tcontrol_t,out_EVENT_VAL [i]->read(),0);
348	// TEST(Tcontrol_t,out_SPR_EVENT_VAL [i]->read(),0);
349	// TEST(Tdepth_t ,out_DEPTH_MIN [i]->read(),0); // no branch speculated
350	// TEST(Tdepth_t ,out_DEPTH_MAX [i]->read(),0); // no branch speculated
351	// TEST(Tdepth_t ,out_DEPTH_FULL [i]->read(),0); // no branch speculated
352	// }
353	// for (uint32_t i=0; i<_param->_sum_inst_decod; ++i)
354	// TEST(Tcontrol_t,out_DECOD_VAL [i]->read(),0);
355	// for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i)
356	// TEST(Tcontrol_t,out_BRANCH_COMPLETE_ACK [i]->read(),0); // can't accept (interactive)
357	// TEST(Tcontrol_t,out_COMMIT_EVENT_ACK ->read(),1); // can accept
358
359	LABEL("Reset");
360	in_NRESET->write(0);
361	SC_START(5);
362	in_NRESET->write(1);
363
364	LABEL("Loop of Test");
365
366	for (uint32_t iteration=0; iteration< NB_ITERATION; iteration ++)
367	{
368	LABEL("Iteration %d",iteration);
369
370	SC_START(1);
371	}
372
373	/********************************************************
374	* Simulation - End
375	********************************************************/
376
377	TEST_OK ("End of Simulation");
378	delete _time;
379
380	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
381
382	delete in_CLOCK;
383	delete in_NRESET;
384
385	DELETE1_SC_SIGNAL(out_ICACHE_REQ_VAL ,_param->_nb_context);
386	DELETE1_SC_SIGNAL( in_ICACHE_REQ_ACK ,_param->_nb_context);
387	//DELETE1_SC_SIGNAL(out_ICACHE_REQ_THREAD_ID ,_param->_nb_context);
388	DELETE1_SC_SIGNAL(out_ICACHE_REQ_PACKET_ID ,_param->_nb_context);
389	DELETE1_SC_SIGNAL(out_ICACHE_REQ_ADDRESS ,_param->_nb_context);
390	DELETE1_SC_SIGNAL(out_ICACHE_REQ_TYPE ,_param->_nb_context);
391	DELETE1_SC_SIGNAL( in_ICACHE_RSP_VAL ,_param->_nb_context);
392	DELETE1_SC_SIGNAL(out_ICACHE_RSP_ACK ,_param->_nb_context);
393	//DELETE1_SC_SIGNAL( in_ICACHE_RSP_THREAD_ID ,_param->_nb_context);
394	DELETE1_SC_SIGNAL( in_ICACHE_RSP_PACKET_ID ,_param->_nb_context);
395	DELETE2_SC_SIGNAL( in_ICACHE_RSP_INSTRUCTION ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
396	DELETE1_SC_SIGNAL( in_ICACHE_RSP_ERROR ,_param->_nb_context);
397	DELETE1_SC_SIGNAL(out_DECOD_VAL ,_param->_sum_inst_decod);
398	DELETE1_SC_SIGNAL( in_DECOD_ACK ,_param->_sum_inst_decod);
399	DELETE1_SC_SIGNAL(out_DECOD_CONTEXT_ID ,_param->_sum_inst_decod);
400	DELETE1_SC_SIGNAL(out_DECOD_DEPTH ,_param->_sum_inst_decod);
401	DELETE1_SC_SIGNAL(out_DECOD_TYPE ,_param->_sum_inst_decod);
402	DELETE1_SC_SIGNAL(out_DECOD_OPERATION ,_param->_sum_inst_decod);
403	DELETE1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,_param->_sum_inst_decod);
404	DELETE1_SC_SIGNAL(out_DECOD_LAST_EVENT ,_param->_sum_inst_decod);
405	DELETE1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,_param->_sum_inst_decod);
406	DELETE1_SC_SIGNAL(out_DECOD_ADDRESS ,_param->_sum_inst_decod);
407	DELETE1_SC_SIGNAL(out_DECOD_ADDRESS_NEXT ,_param->_sum_inst_decod);
408	DELETE1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT ,_param->_sum_inst_decod);
409	DELETE1_SC_SIGNAL(out_DECOD_IMMEDIAT ,_param->_sum_inst_decod);
410	DELETE1_SC_SIGNAL(out_DECOD_READ_RA ,_param->_sum_inst_decod);
411	DELETE1_SC_SIGNAL(out_DECOD_NUM_REG_RA ,_param->_sum_inst_decod);
412	DELETE1_SC_SIGNAL(out_DECOD_READ_RB ,_param->_sum_inst_decod);
413	DELETE1_SC_SIGNAL(out_DECOD_NUM_REG_RB ,_param->_sum_inst_decod);
414	DELETE1_SC_SIGNAL(out_DECOD_READ_RC ,_param->_sum_inst_decod);
415	DELETE1_SC_SIGNAL(out_DECOD_NUM_REG_RC ,_param->_sum_inst_decod);
416	DELETE1_SC_SIGNAL(out_DECOD_WRITE_RD ,_param->_sum_inst_decod);
417	DELETE1_SC_SIGNAL(out_DECOD_NUM_REG_RD ,_param->_sum_inst_decod);
418	DELETE1_SC_SIGNAL(out_DECOD_WRITE_RE ,_param->_sum_inst_decod);
419	DELETE1_SC_SIGNAL(out_DECOD_NUM_REG_RE ,_param->_sum_inst_decod);
420	DELETE1_SC_SIGNAL(out_DECOD_EXCEPTION_USE ,_param->_sum_inst_decod);
421	DELETE1_SC_SIGNAL(out_DECOD_EXCEPTION ,_param->_sum_inst_decod);
422	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete);
423	DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete);
424	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete);
425	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete);
426	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete);
427	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete);
428	DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete);
429	DELETE0_SC_SIGNAL( in_COMMIT_EVENT_VAL );
430	DELETE0_SC_SIGNAL(out_COMMIT_EVENT_ACK );
431	DELETE0_SC_SIGNAL( in_COMMIT_EVENT_CONTEXT_ID );
432	DELETE0_SC_SIGNAL( in_COMMIT_EVENT_DEPTH );
433	DELETE0_SC_SIGNAL( in_COMMIT_EVENT_TYPE );
434	DELETE0_SC_SIGNAL( in_COMMIT_EVENT_IS_DELAY_SLOT );
435	DELETE0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS );
436	DELETE0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR_VAL );
437	DELETE0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR );
438	DELETE0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR_VAL );
439	DELETE0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR );
440	DELETE1_SC_SIGNAL(out_EVENT_VAL ,_param->_nb_context);
441	DELETE1_SC_SIGNAL( in_EVENT_ACK ,_param->_nb_context);
442	DELETE1_SC_SIGNAL(out_EVENT_ADDRESS ,_param->_nb_context);
443	DELETE1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT ,_param->_nb_context);
444	DELETE1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context);
445	DELETE1_SC_SIGNAL(out_EVENT_IS_DS_TAKE ,_param->_nb_context);
446	DELETE1_SC_SIGNAL(out_SPR_EVENT_VAL ,_param->_nb_context);
447	DELETE1_SC_SIGNAL( in_SPR_EVENT_ACK ,_param->_nb_context);
448	DELETE1_SC_SIGNAL(out_SPR_EVENT_EPCR ,_param->_nb_context);
449	DELETE1_SC_SIGNAL(out_SPR_EVENT_EEAR_WEN ,_param->_nb_context);
450	DELETE1_SC_SIGNAL(out_SPR_EVENT_EEAR ,_param->_nb_context);
451	DELETE1_SC_SIGNAL(out_SPR_EVENT_SR_DSX ,_param->_nb_context);
452	DELETE1_SC_SIGNAL(out_SPR_EVENT_SR_TO_ESR ,_param->_nb_context);
453	DELETE1_SC_SIGNAL( in_NB_INST_COMMIT_ALL ,_param->_nb_context);
454	DELETE1_SC_SIGNAL( in_NB_INST_COMMIT_MEM ,_param->_nb_context);
455	DELETE1_SC_SIGNAL(out_NB_INST_DECOD_ALL ,_param->_nb_context);
456	DELETE1_SC_SIGNAL(out_DEPTH_MIN ,_param->_nb_context);
457	DELETE1_SC_SIGNAL(out_DEPTH_MAX ,_param->_nb_context);
458	DELETE1_SC_SIGNAL(out_DEPTH_FULL ,_param->_nb_context);
459	DELETE1_SC_SIGNAL( in_SPR_SR_IEE ,_param->_nb_context);
460	DELETE1_SC_SIGNAL( in_SPR_SR_EPH ,_param->_nb_context);
461	DELETE1_SC_SIGNAL( in_INTERRUPT_ENABLE ,_param->_nb_context);
462	}
463	#endif
464
465	delete _Front_end;
466	#ifdef STATISTICS
467	delete _parameters_statistics;
468	#endif
469	}

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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/test.cpp @ 131

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