[88] | 1 | #ifndef morpheo_behavioural_core_multi_ooo_engine_ooo_engine_commit_unit_Commit_unit_h |
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| 2 | #define morpheo_behavioural_core_multi_ooo_engine_ooo_engine_commit_unit_Commit_unit_h |
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| 3 | |
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| 4 | /* |
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| 5 | * $Id: Commit_unit.h 122 2009-06-03 08:15:51Z rosiere $ |
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| 6 | * |
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| 7 | * [ Description ] |
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| 8 | * |
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| 9 | */ |
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| 10 | |
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| 11 | #ifdef SYSTEMC |
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| 12 | #include "systemc.h" |
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| 13 | #endif |
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| 14 | |
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| 15 | |
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| 16 | #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Parameters.h" |
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| 17 | #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h" |
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| 18 | #ifdef STATISTICS |
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| 19 | #include "Behavioural/include/Stat.h" |
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| 20 | #endif |
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| 21 | #include "Behavioural/include/Component.h" |
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| 22 | #ifdef VHDL |
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| 23 | #include "Behavioural/include/Vhdl.h" |
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| 24 | #endif |
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| 25 | #include "Behavioural/include/Usage.h" |
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| 26 | |
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| 27 | #include "Common/include/ToString.h" |
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| 28 | #include "Common/include/Debug.h" |
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| 29 | |
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| 30 | #include "Behavioural/Generic/Priority/include/Priority.h" |
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| 31 | |
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| 32 | #include <iostream> |
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[111] | 33 | #include <fstream> |
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[88] | 34 | |
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| 35 | namespace morpheo { |
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| 36 | namespace behavioural { |
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| 37 | |
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| 38 | namespace core { |
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| 39 | namespace multi_ooo_engine { |
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| 40 | namespace ooo_engine { |
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| 41 | namespace commit_unit { |
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| 42 | |
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| 43 | |
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| 44 | class Commit_unit |
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| 45 | #if SYSTEMC |
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| 46 | : public sc_module |
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| 47 | #endif |
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| 48 | { |
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| 49 | // -----[ fields ]---------------------------------------------------- |
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| 50 | // Parameters |
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| 51 | protected : const std::string _name; |
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| 52 | protected : const Parameters * _param; |
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| 53 | private : const Tusage_t _usage; |
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| 54 | |
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| 55 | #ifdef STATISTICS |
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| 56 | public : Stat * _stat; |
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[110] | 57 | public : counter_t ** _stat_nb_inst_insert ;//[nb_rename_unit] |
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| 58 | public : counter_t ** _stat_nb_inst_retire ;//[nb_rename_unit] |
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| 59 | public : counter_t * _stat_nb_inst_commit ; |
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[88] | 60 | public : counter_t * _stat_nb_inst_commit_conflit_access; |
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[110] | 61 | public : counter_t ** _stat_nb_inst_retire_ok ;//[nb_thread] |
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| 62 | public : counter_t ** _stat_nb_inst_retire_ko ;//[nb_thread] |
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| 63 | public : counter_t ** _stat_nb_inst_type ;//[nb_type] |
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| 64 | public : counter_t ** _stat_bank_nb_inst ;//[nb_bank] |
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[88] | 65 | #endif |
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| 66 | |
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| 67 | public : Component * _component; |
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| 68 | private : Interfaces * _interfaces; |
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| 69 | |
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| 70 | #ifdef SYSTEMC |
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| 71 | // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 72 | // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 73 | public : SC_CLOCK * in_CLOCK ; |
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| 74 | public : SC_IN (Tcontrol_t) * in_NRESET ; |
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| 75 | |
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| 76 | // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 77 | public : SC_IN (Tcontrol_t ) *** in_INSERT_VAL ;//[nb_rename_unit][nb_inst_insert] |
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| 78 | public : SC_OUT(Tcontrol_t ) *** out_INSERT_ACK ;//[nb_rename_unit][nb_inst_insert] |
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| 79 | public : SC_IN (Tcontext_t ) *** in_INSERT_FRONT_END_ID ;//[nb_rename_unit][nb_inst_insert] |
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| 80 | public : SC_IN (Tcontext_t ) *** in_INSERT_CONTEXT_ID ;//[nb_rename_unit][nb_inst_insert] |
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| 81 | public : SC_OUT(Tpacket_t ) *** out_INSERT_PACKET_ID ;//[nb_rename_unit][nb_inst_insert] |
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| 82 | //public : SC_IN (Tcontext_t ) *** in_INSERT_RENAME_UNIT_ID ;//[nb_rename_unit][nb_inst_insert] |
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| 83 | public : SC_IN (Tdepth_t ) *** in_INSERT_DEPTH ;//[nb_rename_unit][nb_inst_insert] |
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| 84 | public : SC_IN (Ttype_t ) *** in_INSERT_TYPE ;//[nb_rename_unit][nb_inst_insert] |
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| 85 | public : SC_IN (Toperation_t ) *** in_INSERT_OPERATION ;//[nb_rename_unit][nb_inst_insert] |
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| 86 | public : SC_IN (Tcontrol_t ) *** in_INSERT_NO_EXECUTE ;//[nb_rename_unit][nb_inst_insert] |
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| 87 | public : SC_IN (Tcontrol_t ) *** in_INSERT_IS_DELAY_SLOT ;//[nb_rename_unit][nb_inst_insert] |
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[108] | 88 | #ifdef DEBUG |
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| 89 | public : SC_IN (Taddress_t ) *** in_INSERT_ADDRESS ;//[nb_rename_unit][nb_inst_insert] |
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| 90 | #endif |
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[105] | 91 | public : SC_IN (Taddress_t ) *** in_INSERT_ADDRESS_NEXT ;//[nb_rename_unit][nb_inst_insert] |
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[88] | 92 | public : SC_IN (Texception_t ) *** in_INSERT_EXCEPTION ;//[nb_rename_unit][nb_inst_insert] |
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| 93 | public : SC_IN (Texception_t ) *** in_INSERT_EXCEPTION_USE ;//[nb_rename_unit][nb_inst_insert] |
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| 94 | public : SC_IN (Tlsq_ptr_t ) *** in_INSERT_STORE_QUEUE_PTR_WRITE ;//[nb_rename_unit][nb_inst_insert] |
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| 95 | public : SC_IN (Tlsq_ptr_t ) *** in_INSERT_LOAD_QUEUE_PTR_WRITE ;//[nb_rename_unit][nb_inst_insert] |
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[121] | 96 | #ifdef DEBUG |
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[88] | 97 | public : SC_IN (Tcontrol_t ) *** in_INSERT_READ_RA ;//[nb_rename_unit][nb_inst_insert] |
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| 98 | public : SC_IN (Tgeneral_address_t ) *** in_INSERT_NUM_REG_RA_LOG ;//[nb_rename_unit][nb_inst_insert] |
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| 99 | public : SC_IN (Tgeneral_address_t ) *** in_INSERT_NUM_REG_RA_PHY ;//[nb_rename_unit][nb_inst_insert] |
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| 100 | public : SC_IN (Tcontrol_t ) *** in_INSERT_READ_RB ;//[nb_rename_unit][nb_inst_insert] |
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| 101 | public : SC_IN (Tgeneral_address_t ) *** in_INSERT_NUM_REG_RB_LOG ;//[nb_rename_unit][nb_inst_insert] |
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| 102 | public : SC_IN (Tgeneral_address_t ) *** in_INSERT_NUM_REG_RB_PHY ;//[nb_rename_unit][nb_inst_insert] |
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| 103 | public : SC_IN (Tcontrol_t ) *** in_INSERT_READ_RC ;//[nb_rename_unit][nb_inst_insert] |
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| 104 | public : SC_IN (Tspecial_address_t ) *** in_INSERT_NUM_REG_RC_LOG ;//[nb_rename_unit][nb_inst_insert] |
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| 105 | public : SC_IN (Tspecial_address_t ) *** in_INSERT_NUM_REG_RC_PHY ;//[nb_rename_unit][nb_inst_insert] |
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[121] | 106 | #endif |
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[88] | 107 | public : SC_IN (Tcontrol_t ) *** in_INSERT_WRITE_RD ;//[nb_rename_unit][nb_inst_insert] |
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| 108 | public : SC_IN (Tgeneral_address_t ) *** in_INSERT_NUM_REG_RD_LOG ;//[nb_rename_unit][nb_inst_insert] |
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| 109 | public : SC_IN (Tgeneral_address_t ) *** in_INSERT_NUM_REG_RD_PHY_OLD ;//[nb_rename_unit][nb_inst_insert] |
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| 110 | public : SC_IN (Tgeneral_address_t ) *** in_INSERT_NUM_REG_RD_PHY_NEW ;//[nb_rename_unit][nb_inst_insert] |
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| 111 | public : SC_IN (Tcontrol_t ) *** in_INSERT_WRITE_RE ;//[nb_rename_unit][nb_inst_insert] |
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| 112 | public : SC_IN (Tspecial_address_t ) *** in_INSERT_NUM_REG_RE_LOG ;//[nb_rename_unit][nb_inst_insert] |
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| 113 | public : SC_IN (Tspecial_address_t ) *** in_INSERT_NUM_REG_RE_PHY_OLD ;//[nb_rename_unit][nb_inst_insert] |
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| 114 | public : SC_IN (Tspecial_address_t ) *** in_INSERT_NUM_REG_RE_PHY_NEW ;//[nb_rename_unit][nb_inst_insert] |
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| 115 | |
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| 116 | // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 117 | public : SC_OUT(Tcontrol_t ) *** out_RETIRE_VAL ;//[nb_rename_unit][nb_inst_retire] |
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| 118 | public : SC_IN (Tcontrol_t ) *** in_RETIRE_ACK ;//[nb_rename_unit][nb_inst_retire] |
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| 119 | public : SC_OUT(Tcontext_t ) *** out_RETIRE_FRONT_END_ID ;//[nb_rename_unit][nb_inst_retire] |
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| 120 | public : SC_OUT(Tcontext_t ) *** out_RETIRE_CONTEXT_ID ;//[nb_rename_unit][nb_inst_retire] |
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| 121 | //public : SC_OUT(Tcontext_t ) *** out_RETIRE_RENAME_UNIT_ID ;//[nb_rename_unit][nb_inst_retire] |
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| 122 | public : SC_OUT(Tcontrol_t ) *** out_RETIRE_USE_STORE_QUEUE ;//[nb_rename_unit][nb_inst_retire] |
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| 123 | public : SC_OUT(Tcontrol_t ) *** out_RETIRE_USE_LOAD_QUEUE ;//[nb_rename_unit][nb_inst_retire] |
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| 124 | public : SC_OUT(Tlsq_ptr_t ) *** out_RETIRE_STORE_QUEUE_PTR_WRITE ;//[nb_rename_unit][nb_inst_retire] |
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| 125 | public : SC_OUT(Tlsq_ptr_t ) *** out_RETIRE_LOAD_QUEUE_PTR_WRITE ;//[nb_rename_unit][nb_inst_retire] |
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[121] | 126 | //public : SC_OUT(Tcontrol_t ) *** out_RETIRE_READ_RA ;//[nb_rename_unit][nb_inst_retire] |
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| 127 | //public : SC_OUT(Tgeneral_address_t ) *** out_RETIRE_NUM_REG_RA_PHY ;//[nb_rename_unit][nb_inst_retire] |
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| 128 | //public : SC_OUT(Tcontrol_t ) *** out_RETIRE_READ_RB ;//[nb_rename_unit][nb_inst_retire] |
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| 129 | //public : SC_OUT(Tgeneral_address_t ) *** out_RETIRE_NUM_REG_RB_PHY ;//[nb_rename_unit][nb_inst_retire] |
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| 130 | //public : SC_OUT(Tcontrol_t ) *** out_RETIRE_READ_RC ;//[nb_rename_unit][nb_inst_retire] |
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| 131 | //public : SC_OUT(Tspecial_address_t ) *** out_RETIRE_NUM_REG_RC_PHY ;//[nb_rename_unit][nb_inst_retire] |
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[88] | 132 | public : SC_OUT(Tcontrol_t ) *** out_RETIRE_WRITE_RD ;//[nb_rename_unit][nb_inst_retire] |
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| 133 | public : SC_OUT(Tgeneral_address_t ) *** out_RETIRE_NUM_REG_RD_LOG ;//[nb_rename_unit][nb_inst_retire] |
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| 134 | public : SC_OUT(Tgeneral_address_t ) *** out_RETIRE_NUM_REG_RD_PHY_OLD ;//[nb_rename_unit][nb_inst_retire] |
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| 135 | public : SC_OUT(Tgeneral_address_t ) *** out_RETIRE_NUM_REG_RD_PHY_NEW ;//[nb_rename_unit][nb_inst_retire] |
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| 136 | public : SC_OUT(Tcontrol_t ) *** out_RETIRE_WRITE_RE ;//[nb_rename_unit][nb_inst_retire] |
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| 137 | public : SC_OUT(Tspecial_address_t ) *** out_RETIRE_NUM_REG_RE_LOG ;//[nb_rename_unit][nb_inst_retire] |
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| 138 | public : SC_OUT(Tspecial_address_t ) *** out_RETIRE_NUM_REG_RE_PHY_OLD ;//[nb_rename_unit][nb_inst_retire] |
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| 139 | public : SC_OUT(Tspecial_address_t ) *** out_RETIRE_NUM_REG_RE_PHY_NEW ;//[nb_rename_unit][nb_inst_retire] |
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[104] | 140 | |
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| 141 | // ~~~~~[ Interface : "commit" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 142 | public : SC_OUT(Tcontrol_t ) *** out_RETIRE_EVENT_VAL ;//[nb_front_end][nb_context] |
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| 143 | public : SC_IN (Tcontrol_t ) *** in_RETIRE_EVENT_ACK ;//[nb_front_end][nb_context] |
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| 144 | public : SC_OUT(Tevent_state_t ) *** out_RETIRE_EVENT_STATE ;//[nb_front_end][nb_context] |
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[122] | 145 | public : SC_OUT(Tcontrol_t ) *** out_RETIRE_EVENT_FLUSH ;//[nb_front_end][nb_context] |
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| 146 | public : SC_OUT(Tcontrol_t ) *** out_RETIRE_EVENT_STOP ;//[nb_front_end][nb_context] |
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[88] | 147 | |
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| 148 | // ~~~~~[ Interface : "commit" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 149 | public : SC_IN (Tcontrol_t ) ** in_COMMIT_VAL ;//[nb_inst_commit] |
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| 150 | public : SC_OUT(Tcontrol_t ) ** out_COMMIT_ACK ;//[nb_inst_commit] |
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| 151 | public : SC_IN (Tcontrol_t ) ** in_COMMIT_WEN ;//[nb_inst_commit] |
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| 152 | public : SC_IN (Tpacket_t ) ** in_COMMIT_PACKET_ID ;//[nb_inst_commit] |
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| 153 | //public : SC_IN (Toperation_t ) ** in_COMMIT_OPERATION ;//[nb_inst_commit] |
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| 154 | //public : SC_IN (Ttype_t ) ** in_COMMIT_TYPE ;//[nb_inst_commit] |
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| 155 | public : SC_IN (Tspecial_data_t ) ** in_COMMIT_FLAGS ;//[nb_inst_commit] |
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| 156 | public : SC_IN (Texception_t ) ** in_COMMIT_EXCEPTION ;//[nb_inst_commit] |
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| 157 | public : SC_IN (Tcontrol_t ) ** in_COMMIT_NO_SEQUENCE ;//[nb_inst_commit] |
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[97] | 158 | public : SC_IN (Taddress_t ) ** in_COMMIT_ADDRESS ;//[nb_inst_commit] |
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[88] | 159 | public : SC_OUT(Tgeneral_address_t ) ** out_COMMIT_NUM_REG_RD ;//[nb_inst_commit] |
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| 160 | |
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| 161 | // ~~~~~[ Interface : "reexecute" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 162 | public : SC_OUT(Tcontrol_t ) ** out_REEXECUTE_VAL ;//[nb_inst_reexecute] |
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| 163 | public : SC_IN (Tcontrol_t ) ** in_REEXECUTE_ACK ;//[nb_inst_reexecute] |
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| 164 | public : SC_OUT(Tcontext_t ) ** out_REEXECUTE_CONTEXT_ID ;//[nb_inst_reexecute] |
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| 165 | public : SC_OUT(Tcontext_t ) ** out_REEXECUTE_FRONT_END_ID ;//[nb_inst_reexecute] |
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| 166 | public : SC_OUT(Tpacket_t ) ** out_REEXECUTE_PACKET_ID ;//[nb_inst_reexecute] |
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| 167 | public : SC_OUT(Toperation_t ) ** out_REEXECUTE_OPERATION ;//[nb_inst_reexecute] |
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| 168 | public : SC_OUT(Ttype_t ) ** out_REEXECUTE_TYPE ;//[nb_inst_reexecute] |
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| 169 | public : SC_OUT(Tlsq_ptr_t ) ** out_REEXECUTE_STORE_QUEUE_PTR_WRITE ;//[nb_inst_reexecute] |
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| 170 | |
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| 171 | // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 172 | public : SC_OUT(Tcontrol_t ) ** out_BRANCH_COMPLETE_VAL ;//[nb_inst_branch_complete] |
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| 173 | public : SC_IN (Tcontrol_t ) ** in_BRANCH_COMPLETE_ACK ;//[nb_inst_branch_complete] |
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| 174 | public : SC_OUT(Tcontext_t ) ** out_BRANCH_COMPLETE_CONTEXT_ID ;//[nb_inst_branch_complete] |
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| 175 | public : SC_OUT(Tcontext_t ) ** out_BRANCH_COMPLETE_FRONT_END_ID ;//[nb_inst_branch_complete] |
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| 176 | public : SC_OUT(Tdepth_t ) ** out_BRANCH_COMPLETE_DEPTH ;//[nb_inst_branch_complete] |
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| 177 | public : SC_OUT(Taddress_t ) ** out_BRANCH_COMPLETE_ADDRESS ;//[nb_inst_branch_complete] |
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[98] | 178 | //public : SC_OUT(Tcontrol_t ) ** out_BRANCH_COMPLETE_FLAG ;//[nb_inst_branch_complete] |
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| 179 | public : SC_OUT(Tcontrol_t ) ** out_BRANCH_COMPLETE_NO_SEQUENCE ;//[nb_inst_branch_complete] |
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[88] | 180 | public : SC_IN (Tcontrol_t ) ** in_BRANCH_COMPLETE_MISS_PREDICTION ;//[nb_inst_branch_complete] |
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| 181 | |
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| 182 | // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 183 | public : SC_OUT(Tcontrol_t ) * out_UPDATE_VAL ; |
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| 184 | public : SC_IN (Tcontrol_t ) * in_UPDATE_ACK ; |
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| 185 | public : SC_OUT(Tcontext_t ) * out_UPDATE_CONTEXT_ID ; |
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| 186 | public : SC_OUT(Tcontext_t ) * out_UPDATE_FRONT_END_ID ; |
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| 187 | public : SC_OUT(Tdepth_t ) * out_UPDATE_DEPTH ; |
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| 188 | public : SC_OUT(Tevent_type_t ) * out_UPDATE_TYPE ; |
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| 189 | public : SC_OUT(Tcontrol_t ) * out_UPDATE_IS_DELAY_SLOT ; |
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| 190 | public : SC_OUT(Taddress_t ) * out_UPDATE_ADDRESS ; |
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[105] | 191 | public : SC_OUT(Tcontrol_t ) * out_UPDATE_ADDRESS_EPCR_VAL ; |
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[88] | 192 | public : SC_OUT(Taddress_t ) * out_UPDATE_ADDRESS_EPCR ; |
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| 193 | public : SC_OUT(Tcontrol_t ) * out_UPDATE_ADDRESS_EEAR_VAL ; |
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[97] | 194 | public : SC_OUT(Tgeneral_data_t ) * out_UPDATE_ADDRESS_EEAR ; |
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[88] | 195 | |
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| 196 | // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 197 | public : SC_IN (Tcontrol_t ) *** in_EVENT_VAL ;//[nb_front_end][nb_context] |
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| 198 | public : SC_OUT(Tcontrol_t ) *** out_EVENT_ACK ;//[nb_front_end][nb_context] |
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| 199 | public : SC_IN (Taddress_t ) *** in_EVENT_ADDRESS ;//[nb_front_end][nb_context] |
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| 200 | public : SC_IN (Taddress_t ) *** in_EVENT_ADDRESS_NEXT ;//[nb_front_end][nb_context] |
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| 201 | public : SC_IN (Tcontrol_t ) *** in_EVENT_ADDRESS_NEXT_VAL ;//[nb_front_end][nb_context] |
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| 202 | public : SC_IN (Tcontrol_t ) *** in_EVENT_IS_DS_TAKE ;//[nb_front_end][nb_context] |
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| 203 | |
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| 204 | // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 205 | public : SC_OUT(Tcounter_t ) *** out_NB_INST_COMMIT_ALL ;//[nb_front_end][nb_context] |
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| 206 | public : SC_OUT(Tcounter_t ) *** out_NB_INST_COMMIT_MEM ;//[nb_front_end][nb_context] |
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[108] | 207 | public : SC_IN (Tcounter_t ) *** in_NB_INST_DECOD_ALL ;//[nb_front_end][nb_context] |
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[88] | 208 | |
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| 209 | // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 210 | public : SC_IN (Tdepth_t ) *** in_DEPTH_MIN ;//[nb_front_end][nb_context] |
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| 211 | public : SC_IN (Tdepth_t ) *** in_DEPTH_MAX ;//[nb_front_end][nb_context] |
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[101] | 212 | public : SC_IN (Tcontrol_t ) *** in_DEPTH_FULL ;//[nb_front_end][nb_context] |
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[88] | 213 | |
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| 214 | // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 215 | public : SC_IN (Tcontrol_t ) *** in_SPR_READ_SR_OVE ;//[nb_front_end][nb_context] |
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| 216 | |
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| 217 | // ~~~~~[ Interface : "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 218 | public : SC_OUT(Tcontrol_t ) *** out_SPR_WRITE_VAL ;//[nb_front_end][nb_context] |
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| 219 | public : SC_IN (Tcontrol_t ) *** in_SPR_WRITE_ACK ;//[nb_front_end][nb_context] |
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| 220 | public : SC_OUT(Tcontrol_t ) *** out_SPR_WRITE_SR_F_VAL ;//[nb_front_end][nb_context] |
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| 221 | public : SC_OUT(Tcontrol_t ) *** out_SPR_WRITE_SR_F ;//[nb_front_end][nb_context] |
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| 222 | public : SC_OUT(Tcontrol_t ) *** out_SPR_WRITE_SR_CY_VAL ;//[nb_front_end][nb_context] |
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| 223 | public : SC_OUT(Tcontrol_t ) *** out_SPR_WRITE_SR_CY ;//[nb_front_end][nb_context] |
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| 224 | public : SC_OUT(Tcontrol_t ) *** out_SPR_WRITE_SR_OV_VAL ;//[nb_front_end][nb_context] |
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| 225 | public : SC_OUT(Tcontrol_t ) *** out_SPR_WRITE_SR_OV ;//[nb_front_end][nb_context] |
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| 226 | |
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| 227 | // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 228 | private : generic::priority::Priority * _priority_insert ; |
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| 229 | |
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| 230 | // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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[109] | 231 | private : double ** _nb_cycle_idle; |
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| 232 | |
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[88] | 233 | private : std::list<entry_t*> * _rob ;//[nb_bank] |
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| 234 | |
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| 235 | private : uint32_t reg_NUM_BANK_HEAD ; |
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| 236 | private : uint32_t reg_NUM_BANK_TAIL ; |
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[122] | 237 | private : uint32_t reg_NUM_PTR_TAIL ; |
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[88] | 238 | private : uint32_t * reg_BANK_PTR ;//[nb_bank] |
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| 239 | |
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| 240 | private : Tcounter_t ** reg_NB_INST_COMMIT_ALL ;//[nb_front_end][nb_context] |
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| 241 | private : Tcounter_t ** reg_NB_INST_COMMIT_MEM ;//[nb_front_end][nb_context] |
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[100] | 242 | |
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[122] | 243 | private : Tcommit_event_state_t ** reg_EVENT_STATE ;//[nb_front_end][nb_context] |
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| 244 | //private : bool ** reg_EVENT_FLUSH ;//[nb_front_end][nb_context] |
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[112] | 245 | private : bool ** reg_EVENT_STOP ;//[nb_front_end][nb_context] |
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[122] | 246 | private : uint32_t ** reg_EVENT_NUM_BANK ;//[nb_front_end][nb_context] |
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| 247 | private : uint32_t ** reg_EVENT_NUM_PTR ;//[nb_front_end][nb_context] |
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| 248 | private : bool ** reg_EVENT_CAN_RESTART ;//[nb_front_end][nb_context] |
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| 249 | private : uint32_t ** reg_EVENT_PACKET ;//[nb_front_end][nb_context] |
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| 250 | private : bool ** reg_EVENT_LAST ;//[nb_front_end][nb_context] |
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| 251 | private : uint32_t ** reg_EVENT_LAST_NUM_BANK ;//[nb_front_end][nb_context] |
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| 252 | private : uint32_t ** reg_EVENT_LAST_NUM_PTR ;//[nb_front_end][nb_context] |
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[104] | 253 | |
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[105] | 254 | //private : Taddress_t ** reg_PC_PREVIOUS ;//[nb_front_end][nb_context] |
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[104] | 255 | private : Taddress_t ** reg_PC_CURRENT ;//[nb_front_end][nb_context] |
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| 256 | private : Taddress_t ** reg_PC_CURRENT_IS_DS ;//[nb_front_end][nb_context] |
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| 257 | private : Taddress_t ** reg_PC_CURRENT_IS_DS_TAKE ;//[nb_front_end][nb_context] |
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| 258 | private : Taddress_t ** reg_PC_NEXT ;//[nb_front_end][nb_context] |
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[88] | 259 | |
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| 260 | // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 261 | private : Tcontrol_t * internal_BANK_INSERT_VAL ;//[nb_bank] |
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| 262 | private : uint32_t * internal_BANK_INSERT_NUM_RENAME_UNIT ;//[nb_bank] |
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| 263 | private : uint32_t * internal_BANK_INSERT_NUM_INST ;//[nb_bank] |
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| 264 | |
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| 265 | #ifdef STATISTICS |
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| 266 | private : uint32_t internal_BANK_COMMIT_CONFLIT_ACCESS ; |
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| 267 | #endif |
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| 268 | private : Tcontrol_t ** internal_BANK_COMMIT_VAL ;//[nb_bank][nb_bank_access_commit] |
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| 269 | private : uint32_t ** internal_BANK_COMMIT_NUM_INST ;//[nb_bank][nb_bank_access_commit] |
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| 270 | private : entry_t * ** internal_BANK_COMMIT_ENTRY ;//[nb_bank][nb_bank_access_commit] |
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| 271 | |
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[110] | 272 | private : uint32_t internal_BANK_RETIRE_HEAD ; |
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[88] | 273 | private : Tcontrol_t * internal_BANK_RETIRE_VAL ;//[nb_bank] |
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| 274 | private : uint32_t * internal_BANK_RETIRE_NUM_RENAME_UNIT ;//[nb_bank] |
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| 275 | private : uint32_t * internal_BANK_RETIRE_NUM_INST ;//[nb_bank] |
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| 276 | |
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| 277 | private : Tcontrol_t * internal_REEXECUTE_VAL ;//[nb_inst_reexecute] |
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| 278 | private : uint32_t * internal_REEXECUTE_NUM_BANK ;//[nb_inst_reexecute] |
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| 279 | |
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| 280 | private : Tcontrol_t * internal_BRANCH_COMPLETE_VAL ;//[nb_inst_branch_complete] |
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| 281 | private : uint32_t * internal_BRANCH_COMPLETE_NUM_BANK ;//[nb_inst_branch_complete] |
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| 282 | |
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| 283 | private : Tcontrol_t internal_UPDATE_VAL ; |
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| 284 | private : uint32_t internal_UPDATE_NUM_BANK ; |
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| 285 | |
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| 286 | private : Tcontrol_t ** internal_EVENT_ACK ;//[nb_front_end][nb_context] |
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[104] | 287 | |
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| 288 | private : Tcontrol_t ** internal_RETIRE_EVENT_VAL ;//[nb_front_end][nb_context] |
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[88] | 289 | #endif |
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| 290 | |
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[111] | 291 | #if defined(DEBUG) and defined(DEBUG_Commit_unit) and (DEBUG_Commit_unit == true) |
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| 292 | private : std::ofstream * instruction_log_file; |
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| 293 | #endif |
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| 294 | |
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[88] | 295 | // -----[ Methods ]--------------------------------------------------- |
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| 296 | |
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| 297 | #ifdef SYSTEMC |
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| 298 | SC_HAS_PROCESS (Commit_unit); |
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| 299 | #endif |
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| 300 | public : Commit_unit |
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| 301 | ( |
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| 302 | #ifdef SYSTEMC |
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| 303 | sc_module_name name, |
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| 304 | #else |
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| 305 | std::string name, |
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| 306 | #endif |
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| 307 | #ifdef STATISTICS |
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| 308 | morpheo::behavioural::Parameters_Statistics * param_statistics, |
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| 309 | #endif |
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| 310 | Parameters * param, |
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| 311 | morpheo::behavioural::Tusage_t usage |
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| 312 | ); |
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| 313 | public : ~Commit_unit (void); |
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| 314 | |
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| 315 | private : void allocation ( |
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| 316 | #ifdef STATISTICS |
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| 317 | morpheo::behavioural::Parameters_Statistics * param_statistics |
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| 318 | #else |
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| 319 | void |
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| 320 | #endif |
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| 321 | ); |
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| 322 | private : void deallocation (void); |
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| 323 | |
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| 324 | #ifdef SYSTEMC |
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| 325 | public : void transition (void); |
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| 326 | public : void genMoore (void); |
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| 327 | public : void genMealy_insert (void); |
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| 328 | public : void genMealy_retire (void); |
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| 329 | public : void genMealy_commit (void); |
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| 330 | #endif |
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| 331 | |
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| 332 | #if VHDL |
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| 333 | public : void vhdl (void); |
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| 334 | private : void vhdl_declaration (Vhdl * & vhdl); |
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| 335 | private : void vhdl_body (Vhdl * & vhdl); |
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| 336 | #endif |
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| 337 | |
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| 338 | #ifdef STATISTICS |
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| 339 | public : void statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics); |
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| 340 | public : void statistics_deallocation (void); |
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| 341 | #endif |
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| 342 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
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| 343 | private : void end_cycle (void); |
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| 344 | #endif |
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| 345 | }; |
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| 346 | |
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| 347 | }; // end namespace commit_unit |
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| 348 | }; // end namespace ooo_engine |
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| 349 | }; // end namespace multi_ooo_engine |
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| 350 | }; // end namespace core |
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| 351 | |
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| 352 | }; // end namespace behavioural |
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| 353 | }; // end namespace morpheo |
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| 354 | |
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| 355 | #endif |
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