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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h @ 141

Last change on this file since 141 was 141, checked in by rosiere, 14 years ago
Add statistics in stage IFETCH, DECODE and COMMIT (insert, retire and commit)
Property svn:keywords set to `Id`
File size: 26.7 KB

Line
1	#ifndef morpheo_behavioural_core_multi_ooo_engine_ooo_engine_commit_unit_Commit_unit_h
2	#define morpheo_behavioural_core_multi_ooo_engine_ooo_engine_commit_unit_Commit_unit_h
3
4	/*
5	* $Id: Commit_unit.h 141 2010-08-02 18:56:05Z rosiere $
6	*
7	* [ Description ]
8	*
9	*/
10
11	#ifdef SYSTEMC
12	#include "systemc.h"
13	#endif
14
15
16	#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Parameters.h"
17	#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h"
18	#ifdef STATISTICS
19	#include "Behavioural/include/Stat.h"
20	#endif
21	#include "Behavioural/include/Component.h"
22	#ifdef VHDL
23	#include "Behavioural/include/Vhdl.h"
24	#endif
25	#include "Behavioural/include/Usage.h"
26
27	#include "Common/include/ToString.h"
28	#include "Common/include/Debug.h"
29
30	#include "Behavioural/Generic/Priority/include/Priority.h"
31
32	#include <iostream>
33	#include <fstream>
34
35	namespace morpheo {
36	namespace behavioural {
37
38	namespace core {
39	namespace multi_ooo_engine {
40	namespace ooo_engine {
41	namespace commit_unit {
42
43
44	class Commit_unit
45	#if SYSTEMC
46	: public sc_module
47	#endif
48	{
49	// -----[ fields ]----------------------------------------------------
50	// Parameters
51	protected : const std::string _name;
52	protected : const Parameters * _param;
53	private : const Tusage_t _usage;
54
55	#ifdef STATISTICS
56	public : Stat * _stat;
57
58	public : counters_t ** _stat_nb_inst_insert ;//[nb_rename_unit]
59	public : counters_t ** _stat_nb_inst_retire ;//[nb_rename_unit]
60	public : counters_t ** _stat_nb_inst_commit ;//[nb_rename_unit]
61
62	public : counter_t * _stat_nb_inst_commit_conflit_access;
63	public : counter_t ** _stat_nb_inst_retire_ok ;//[nb_thread]
64	public : counter_t ** _stat_nb_inst_retire_ko ;//[nb_thread]
65	public : counter_t ** _stat_nb_inst_instruction ;//[nb_instruction]
66	public : counter_t ** _stat_nb_inst_type ;//[nb_type]
67	public : counter_t ** _stat_bank_nb_inst ;//[nb_bank]
68
69	public : counter_t ** _stat_nb_cycle_state_no_event ;//[nb_thread]
70	public : counter_t ** _stat_nb_cycle_state_not_yet_event ;//[nb_thread]
71	public : counter_t ** _stat_nb_cycle_state_event ;//[nb_thread]
72	public : counter_t ** _stat_nb_cycle_state_wait_end ;//[nb_thread]
73	#endif
74
75	public : Component * _component;
76	private : Interfaces * _interfaces;
77
78	#ifdef SYSTEMC
79	// ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
80	// ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
81	public : SC_CLOCK * in_CLOCK ;
82	public : SC_IN (Tcontrol_t) * in_NRESET ;
83
84	// ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
85	public : SC_IN (Tcontrol_t ) *** in_INSERT_VAL ;//[nb_rename_unit][nb_inst_insert]
86	public : SC_OUT(Tcontrol_t ) *** out_INSERT_ACK ;//[nb_rename_unit][nb_inst_insert]
87	public : SC_IN (Tcontext_t ) *** in_INSERT_FRONT_END_ID ;//[nb_rename_unit][nb_inst_insert]
88	public : SC_IN (Tcontext_t ) *** in_INSERT_CONTEXT_ID ;//[nb_rename_unit][nb_inst_insert]
89	public : SC_OUT(Tpacket_t ) *** out_INSERT_PACKET_ID ;//[nb_rename_unit][nb_inst_insert]
90	//public : SC_IN (Tcontext_t ) *** in_INSERT_RENAME_UNIT_ID ;//[nb_rename_unit][nb_inst_insert]
91	public : SC_IN (Tdepth_t ) *** in_INSERT_DEPTH ;//[nb_rename_unit][nb_inst_insert]
92	#ifdef STATISTICS
93	public : SC_IN (uint32_t ) *** in_INSERT_INSTRUCTION ;//[nb_rename_unit][nb_inst_insert]
94	#endif
95	public : SC_IN (Ttype_t ) *** in_INSERT_TYPE ;//[nb_rename_unit][nb_inst_insert]
96	public : SC_IN (Toperation_t ) *** in_INSERT_OPERATION ;//[nb_rename_unit][nb_inst_insert]
97	public : SC_IN (Tcontrol_t ) *** in_INSERT_NO_EXECUTE ;//[nb_rename_unit][nb_inst_insert]
98	public : SC_IN (Tcontrol_t ) *** in_INSERT_LAST_EVENT ;//[nb_rename_unit][nb_inst_insert]
99	public : SC_IN (Tcontrol_t ) *** in_INSERT_IS_DELAY_SLOT ;//[nb_rename_unit][nb_inst_insert]
100	#ifdef DEBUG
101	public : SC_IN (Taddress_t ) *** in_INSERT_ADDRESS ;//[nb_rename_unit][nb_inst_insert]
102	#endif
103	public : SC_IN (Taddress_t ) *** in_INSERT_ADDRESS_NEXT ;//[nb_rename_unit][nb_inst_insert]
104	public : SC_IN (Texception_t ) *** in_INSERT_EXCEPTION ;//[nb_rename_unit][nb_inst_insert]
105	public : SC_IN (Texception_t ) *** in_INSERT_EXCEPTION_USE ;//[nb_rename_unit][nb_inst_insert]
106	public : SC_IN (Tlsq_ptr_t ) *** in_INSERT_STORE_QUEUE_PTR_WRITE ;//[nb_rename_unit][nb_inst_insert]
107	public : SC_IN (Tlsq_ptr_t ) *** in_INSERT_LOAD_QUEUE_PTR_WRITE ;//[nb_rename_unit][nb_inst_insert]
108	#ifdef DEBUG
109	public : SC_IN (Tcontrol_t ) *** in_INSERT_READ_RA ;//[nb_rename_unit][nb_inst_insert]
110	public : SC_IN (Tgeneral_address_t ) *** in_INSERT_NUM_REG_RA_LOG ;//[nb_rename_unit][nb_inst_insert]
111	public : SC_IN (Tgeneral_address_t ) *** in_INSERT_NUM_REG_RA_PHY ;//[nb_rename_unit][nb_inst_insert]
112	#endif
113	public : SC_IN (Tcontrol_t ) *** in_INSERT_READ_RB ;//[nb_rename_unit][nb_inst_insert]
114	#ifdef DEBUG
115	public : SC_IN (Tgeneral_address_t ) *** in_INSERT_NUM_REG_RB_LOG ;//[nb_rename_unit][nb_inst_insert]
116	public : SC_IN (Tgeneral_address_t ) *** in_INSERT_NUM_REG_RB_PHY ;//[nb_rename_unit][nb_inst_insert]
117	public : SC_IN (Tcontrol_t ) *** in_INSERT_READ_RC ;//[nb_rename_unit][nb_inst_insert]
118	public : SC_IN (Tspecial_address_t ) *** in_INSERT_NUM_REG_RC_LOG ;//[nb_rename_unit][nb_inst_insert]
119	public : SC_IN (Tspecial_address_t ) *** in_INSERT_NUM_REG_RC_PHY ;//[nb_rename_unit][nb_inst_insert]
120	#endif
121	public : SC_IN (Tcontrol_t ) *** in_INSERT_WRITE_RD ;//[nb_rename_unit][nb_inst_insert]
122	public : SC_IN (Tgeneral_address_t ) *** in_INSERT_NUM_REG_RD_LOG ;//[nb_rename_unit][nb_inst_insert]
123	public : SC_IN (Tgeneral_address_t ) *** in_INSERT_NUM_REG_RD_PHY_OLD ;//[nb_rename_unit][nb_inst_insert]
124	public : SC_IN (Tgeneral_address_t ) *** in_INSERT_NUM_REG_RD_PHY_NEW ;//[nb_rename_unit][nb_inst_insert]
125	public : SC_IN (Tcontrol_t ) *** in_INSERT_WRITE_RE ;//[nb_rename_unit][nb_inst_insert]
126	public : SC_IN (Tspecial_address_t ) *** in_INSERT_NUM_REG_RE_LOG ;//[nb_rename_unit][nb_inst_insert]
127	public : SC_IN (Tspecial_address_t ) *** in_INSERT_NUM_REG_RE_PHY_OLD ;//[nb_rename_unit][nb_inst_insert]
128	public : SC_IN (Tspecial_address_t ) *** in_INSERT_NUM_REG_RE_PHY_NEW ;//[nb_rename_unit][nb_inst_insert]
129
130	// ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
131	public : SC_OUT(Tcontrol_t ) *** out_RETIRE_VAL ;//[nb_rename_unit][nb_inst_retire]
132	public : SC_IN (Tcontrol_t ) *** in_RETIRE_ACK ;//[nb_rename_unit][nb_inst_retire]
133	public : SC_OUT(Tcontext_t ) *** out_RETIRE_FRONT_END_ID ;//[nb_rename_unit][nb_inst_retire]
134	public : SC_OUT(Tcontext_t ) *** out_RETIRE_CONTEXT_ID ;//[nb_rename_unit][nb_inst_retire]
135	//public : SC_OUT(Tcontext_t ) *** out_RETIRE_RENAME_UNIT_ID ;//[nb_rename_unit][nb_inst_retire]
136	public : SC_OUT(Tcontrol_t ) *** out_RETIRE_USE_STORE_QUEUE ;//[nb_rename_unit][nb_inst_retire]
137	public : SC_OUT(Tcontrol_t ) *** out_RETIRE_USE_LOAD_QUEUE ;//[nb_rename_unit][nb_inst_retire]
138	public : SC_OUT(Tlsq_ptr_t ) *** out_RETIRE_STORE_QUEUE_PTR_WRITE ;//[nb_rename_unit][nb_inst_retire]
139	public : SC_OUT(Tlsq_ptr_t ) *** out_RETIRE_LOAD_QUEUE_PTR_WRITE ;//[nb_rename_unit][nb_inst_retire]
140	//public : SC_OUT(Tcontrol_t ) *** out_RETIRE_READ_RA ;//[nb_rename_unit][nb_inst_retire]
141	//public : SC_OUT(Tgeneral_address_t ) *** out_RETIRE_NUM_REG_RA_PHY ;//[nb_rename_unit][nb_inst_retire]
142	//public : SC_OUT(Tcontrol_t ) *** out_RETIRE_READ_RB ;//[nb_rename_unit][nb_inst_retire]
143	//public : SC_OUT(Tgeneral_address_t ) *** out_RETIRE_NUM_REG_RB_PHY ;//[nb_rename_unit][nb_inst_retire]
144	//public : SC_OUT(Tcontrol_t ) *** out_RETIRE_READ_RC ;//[nb_rename_unit][nb_inst_retire]
145	//public : SC_OUT(Tspecial_address_t ) *** out_RETIRE_NUM_REG_RC_PHY ;//[nb_rename_unit][nb_inst_retire]
146	public : SC_OUT(Tcontrol_t ) *** out_RETIRE_WRITE_RD ;//[nb_rename_unit][nb_inst_retire]
147	public : SC_OUT(Tgeneral_address_t ) *** out_RETIRE_NUM_REG_RD_LOG ;//[nb_rename_unit][nb_inst_retire]
148	public : SC_OUT(Tgeneral_address_t ) *** out_RETIRE_NUM_REG_RD_PHY_OLD ;//[nb_rename_unit][nb_inst_retire]
149	public : SC_OUT(Tgeneral_address_t ) *** out_RETIRE_NUM_REG_RD_PHY_NEW ;//[nb_rename_unit][nb_inst_retire]
150	public : SC_OUT(Tcontrol_t ) *** out_RETIRE_WRITE_RE ;//[nb_rename_unit][nb_inst_retire]
151	public : SC_OUT(Tspecial_address_t ) *** out_RETIRE_NUM_REG_RE_LOG ;//[nb_rename_unit][nb_inst_retire]
152	public : SC_OUT(Tspecial_address_t ) *** out_RETIRE_NUM_REG_RE_PHY_OLD ;//[nb_rename_unit][nb_inst_retire]
153	public : SC_OUT(Tspecial_address_t ) *** out_RETIRE_NUM_REG_RE_PHY_NEW ;//[nb_rename_unit][nb_inst_retire]
154	public : SC_OUT(Tcontrol_t ) *** out_RETIRE_RESTORE ;//[nb_rename_unit][nb_inst_retire]
155	public : SC_OUT(Tcontrol_t ) *** out_RETIRE_RESTORE_RD_PHY_OLD ;//[nb_rename_unit][nb_inst_retire]
156	public : SC_OUT(Tcontrol_t ) *** out_RETIRE_RESTORE_RE_PHY_OLD ;//[nb_rename_unit][nb_inst_retire]
157
158	// ~~~~~[ Interface : "commit" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
159	public : SC_OUT(Tcontrol_t ) *** out_RETIRE_EVENT_VAL ;//[nb_front_end][nb_context]
160	public : SC_IN (Tcontrol_t ) *** in_RETIRE_EVENT_ACK ;//[nb_front_end][nb_context]
161	public : SC_OUT(Tevent_state_t ) *** out_RETIRE_EVENT_STATE ;//[nb_front_end][nb_context]
162	//public : SC_OUT(Tcontrol_t ) *** out_RETIRE_EVENT_FLUSH ;//[nb_front_end][nb_context]
163	public : SC_OUT(Tcontrol_t ) *** out_RETIRE_EVENT_STOP ;//[nb_front_end][nb_context]
164	public : SC_OUT(Tevent_type_t ) *** out_RETIRE_EVENT_TYPE ;//[nb_front_end][nb_context]
165	public : SC_OUT(Tdepth_t ) *** out_RETIRE_EVENT_DEPTH ;//[nb_front_end][nb_context]
166
167	// ~~~~~[ Interface : "commit" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
168	public : SC_IN (Tcontrol_t ) ** in_COMMIT_VAL ;//[nb_inst_commit]
169	public : SC_OUT(Tcontrol_t ) ** out_COMMIT_ACK ;//[nb_inst_commit]
170	public : SC_IN (Tcontrol_t ) ** in_COMMIT_WEN ;//[nb_inst_commit]
171	public : SC_IN (Tpacket_t ) ** in_COMMIT_PACKET_ID ;//[nb_inst_commit]
172	//public : SC_IN (Toperation_t ) ** in_COMMIT_OPERATION ;//[nb_inst_commit]
173	//public : SC_IN (Ttype_t ) ** in_COMMIT_TYPE ;//[nb_inst_commit]
174	public : SC_IN (Tcontrol_t ) ** in_COMMIT_CANCEL ;//[nb_inst_commit]
175	public : SC_IN (Tspecial_data_t ) ** in_COMMIT_FLAGS ;//[nb_inst_commit]
176	public : SC_IN (Texception_t ) ** in_COMMIT_EXCEPTION ;//[nb_inst_commit]
177	public : SC_IN (Tcontrol_t ) ** in_COMMIT_NO_SEQUENCE ;//[nb_inst_commit]
178	public : SC_IN (Taddress_t ) ** in_COMMIT_ADDRESS ;//[nb_inst_commit]
179	public : SC_OUT(Tgeneral_address_t ) ** out_COMMIT_NUM_REG_RD ;//[nb_inst_commit]
180
181	// ~~~~~[ Interface : "reexecute" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
182	public : SC_OUT(Tcontrol_t ) ** out_REEXECUTE_VAL ;//[nb_inst_reexecute]
183	public : SC_IN (Tcontrol_t ) ** in_REEXECUTE_ACK ;//[nb_inst_reexecute]
184	public : SC_OUT(Tcontext_t ) ** out_REEXECUTE_CONTEXT_ID ;//[nb_inst_reexecute]
185	public : SC_OUT(Tcontext_t ) ** out_REEXECUTE_FRONT_END_ID ;//[nb_inst_reexecute]
186	public : SC_OUT(Tpacket_t ) ** out_REEXECUTE_PACKET_ID ;//[nb_inst_reexecute]
187	public : SC_OUT(Toperation_t ) ** out_REEXECUTE_OPERATION ;//[nb_inst_reexecute]
188	public : SC_OUT(Ttype_t ) ** out_REEXECUTE_TYPE ;//[nb_inst_reexecute]
189	public : SC_OUT(Tlsq_ptr_t ) ** out_REEXECUTE_STORE_QUEUE_PTR_WRITE ;//[nb_inst_reexecute]
190
191	// ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
192	public : SC_OUT(Tcontrol_t ) ** out_BRANCH_COMPLETE_VAL ;//[nb_inst_branch_complete]
193	public : SC_IN (Tcontrol_t ) ** in_BRANCH_COMPLETE_ACK ;//[nb_inst_branch_complete]
194	public : SC_OUT(Tcontext_t ) ** out_BRANCH_COMPLETE_CONTEXT_ID ;//[nb_inst_branch_complete]
195	public : SC_OUT(Tcontext_t ) ** out_BRANCH_COMPLETE_FRONT_END_ID ;//[nb_inst_branch_complete]
196	public : SC_OUT(Tdepth_t ) ** out_BRANCH_COMPLETE_DEPTH ;//[nb_inst_branch_complete]
197	public : SC_OUT(Taddress_t ) ** out_BRANCH_COMPLETE_ADDRESS ;//[nb_inst_branch_complete]
198	//public : SC_OUT(Tcontrol_t ) ** out_BRANCH_COMPLETE_FLAG ;//[nb_inst_branch_complete]
199	public : SC_OUT(Tcontrol_t ) ** out_BRANCH_COMPLETE_NO_SEQUENCE ;//[nb_inst_branch_complete]
200	public : SC_IN (Tcontrol_t ) ** in_BRANCH_COMPLETE_MISS_PREDICTION ;//[nb_inst_branch_complete]
201
202	// ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
203	public : SC_OUT(Tcontrol_t ) * out_UPDATE_VAL ;
204	public : SC_IN (Tcontrol_t ) * in_UPDATE_ACK ;
205	public : SC_OUT(Tcontext_t ) * out_UPDATE_CONTEXT_ID ;
206	public : SC_OUT(Tcontext_t ) * out_UPDATE_FRONT_END_ID ;
207	public : SC_OUT(Tdepth_t ) * out_UPDATE_DEPTH ;
208	public : SC_OUT(Tevent_type_t ) * out_UPDATE_TYPE ;
209	public : SC_OUT(Tcontrol_t ) * out_UPDATE_IS_DELAY_SLOT ;
210	public : SC_OUT(Taddress_t ) * out_UPDATE_ADDRESS ;
211	public : SC_OUT(Tcontrol_t ) * out_UPDATE_ADDRESS_EPCR_VAL ;
212	public : SC_OUT(Taddress_t ) * out_UPDATE_ADDRESS_EPCR ;
213	public : SC_OUT(Tcontrol_t ) * out_UPDATE_ADDRESS_EEAR_VAL ;
214	public : SC_OUT(Tgeneral_data_t ) * out_UPDATE_ADDRESS_EEAR ;
215
216	// ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
217	public : SC_IN (Tcontrol_t ) *** in_EVENT_VAL ;//[nb_front_end][nb_context]
218	public : SC_OUT(Tcontrol_t ) *** out_EVENT_ACK ;//[nb_front_end][nb_context]
219	public : SC_IN (Taddress_t ) *** in_EVENT_ADDRESS ;//[nb_front_end][nb_context]
220	public : SC_IN (Taddress_t ) *** in_EVENT_ADDRESS_NEXT ;//[nb_front_end][nb_context]
221	public : SC_IN (Tcontrol_t ) *** in_EVENT_ADDRESS_NEXT_VAL ;//[nb_front_end][nb_context]
222	public : SC_IN (Tcontrol_t ) *** in_EVENT_IS_DS_TAKE ;//[nb_front_end][nb_context]
223
224	// ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
225	public : SC_OUT(Tcounter_t ) *** out_NB_INST_COMMIT_ALL ;//[nb_front_end][nb_context]
226	public : SC_OUT(Tcounter_t ) *** out_NB_INST_COMMIT_MEM ;//[nb_front_end][nb_context]
227	public : SC_IN (Tcounter_t ) *** in_NB_INST_DECOD_ALL ;//[nb_front_end][nb_context]
228
229	// ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
230	public : SC_IN (Tdepth_t ) *** in_DEPTH_MIN ;//[nb_front_end][nb_context]
231	public : SC_IN (Tdepth_t ) *** in_DEPTH_MAX ;//[nb_front_end][nb_context]
232	public : SC_IN (Tcontrol_t ) *** in_DEPTH_FULL ;//[nb_front_end][nb_context]
233
234	// ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
235	public : SC_IN (Tcontrol_t ) *** in_SPR_READ_SR_OVE ;//[nb_front_end][nb_context]
236
237	// ~~~~~[ Interface : "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
238	public : SC_OUT(Tcontrol_t ) *** out_SPR_WRITE_VAL ;//[nb_front_end][nb_context]
239	public : SC_IN (Tcontrol_t ) *** in_SPR_WRITE_ACK ;//[nb_front_end][nb_context]
240	public : SC_OUT(Tcontrol_t ) *** out_SPR_WRITE_SR_F_VAL ;//[nb_front_end][nb_context]
241	public : SC_OUT(Tcontrol_t ) *** out_SPR_WRITE_SR_F ;//[nb_front_end][nb_context]
242	public : SC_OUT(Tcontrol_t ) *** out_SPR_WRITE_SR_CY_VAL ;//[nb_front_end][nb_context]
243	public : SC_OUT(Tcontrol_t ) *** out_SPR_WRITE_SR_CY ;//[nb_front_end][nb_context]
244	public : SC_OUT(Tcontrol_t ) *** out_SPR_WRITE_SR_OV_VAL ;//[nb_front_end][nb_context]
245	public : SC_OUT(Tcontrol_t ) *** out_SPR_WRITE_SR_OV ;//[nb_front_end][nb_context]
246
247	// ~~~~~[ interface : "info" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
248	#ifdef DEBUG_TEST
249	public : SC_OUT(bool ) * out_INFO_ROB_EMPTY ;
250	#endif
251
252	// ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
253	private : generic::priority::Priority * _priority_insert ;
254
255	// ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
256	private : double ** _nb_cycle_idle;
257
258	private : std::list<entry_t> _rob ;//[nb_bank]
259
260	private : uint32_t reg_NUM_BANK_HEAD ;
261	private : uint32_t reg_NUM_BANK_TAIL ;
262	private : uint32_t reg_NUM_PTR_TAIL ;
263	private : uint32_t * reg_BANK_PTR ;//[nb_bank]
264
265	private : Tcounter_t ** reg_NB_INST_COMMIT_ALL ;//[nb_front_end][nb_context]
266	private : Tcounter_t ** reg_NB_INST_COMMIT_MEM ;//[nb_front_end][nb_context]
267
268	private : Tcommit_event_state_t ** reg_EVENT_STATE ;//[nb_front_end][nb_context]
269	private : Tevent_type_t ** reg_EVENT_TYPE ;//[nb_front_end][nb_context]
270	//private : bool ** reg_EVENT_FLUSH ;//[nb_front_end][nb_context]
271	//private : bool ** reg_EVENT_STOP ;//[nb_front_end][nb_context]
272	//private : uint32_t ** reg_EVENT_NUM_BANK ;//[nb_front_end][nb_context]
273	//private : uint32_t ** reg_EVENT_NUM_PTR ;//[nb_front_end][nb_context]
274	//private : bool ** reg_EVENT_CAN_RESTART ;//[nb_front_end][nb_context]
275	private : uint32_t ** reg_EVENT_PACKET ;//[nb_front_end][nb_context]
276	private : Tdepth_t ** reg_EVENT_DEPTH ;//[nb_front_end][nb_context]
277	private : uint32_t ** reg_EVENT_NB_INST ;//[nb_front_end][nb_context]
278	private : bool ** reg_EVENT_LAST ;//[nb_front_end][nb_context]
279	private : uint32_t ** reg_EVENT_LAST_NUM_BANK ;//[nb_front_end][nb_context]
280	private : uint32_t ** reg_EVENT_LAST_NUM_PTR ;//[nb_front_end][nb_context]
281
282	private : bool ** reg_EVENT_NEXT_STOP ;//[nb_front_end][nb_context]
283	private : uint32_t ** reg_EVENT_NEXT_PACKET ;//[nb_front_end][nb_context]
284
285	//private : Taddress_t ** reg_PC_PREVIOUS ;//[nb_front_end][nb_context]
286	private : Taddress_t ** reg_PC_CURRENT ;//[nb_front_end][nb_context]
287	private : Taddress_t ** reg_PC_CURRENT_IS_DS ;//[nb_front_end][nb_context]
288	private : Taddress_t ** reg_PC_CURRENT_IS_DS_TAKE ;//[nb_front_end][nb_context]
289	private : Taddress_t ** reg_PC_NEXT ;//[nb_front_end][nb_context]
290
291	private : bool *** rat_gpr_update_table ;//[nb_front_end][nb_context][nb_general_register_logic]
292	private : bool *** rat_spr_update_table ;//[nb_front_end][nb_context][nb_special_register_logic]
293
294	// ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
295	private : Tcontrol_t * internal_BANK_INSERT_VAL ;//[nb_bank]
296	private : uint32_t * internal_BANK_INSERT_NUM_RENAME_UNIT ;//[nb_bank]
297	private : uint32_t * internal_BANK_INSERT_NUM_INST ;//[nb_bank]
298
299	#ifdef STATISTICS
300	private : uint32_t internal_BANK_COMMIT_CONFLIT_ACCESS ;
301	#endif
302	private : Tcontrol_t ** internal_BANK_COMMIT_VAL ;//[nb_bank][nb_bank_access_commit]
303	private : uint32_t ** internal_BANK_COMMIT_NUM_INST ;//[nb_bank][nb_bank_access_commit]
304	private : entry_t * ** internal_BANK_COMMIT_ENTRY ;//[nb_bank][nb_bank_access_commit]
305
306	private : uint32_t internal_BANK_RETIRE_HEAD ;
307	private : Tcontrol_t * internal_BANK_RETIRE_VAL ;//[nb_bank]
308	private : uint32_t * internal_BANK_RETIRE_NUM_RENAME_UNIT ;//[nb_bank]
309	private : uint32_t * internal_BANK_RETIRE_NUM_INST ;//[nb_bank]
310	//private : Tcontrol_t * internal_BANK_RETIRE_RESTORE ;//[nb_bank]
311	private : Tcontrol_t * internal_BANK_RETIRE_RESTORE_RD_PHY_OLD;//[nb_bank]
312	private : Tcontrol_t * internal_BANK_RETIRE_RESTORE_RE_PHY_OLD;//[nb_bank]
313
314	private : Tcontrol_t * internal_REEXECUTE_VAL ;//[nb_inst_reexecute]
315	private : uint32_t * internal_REEXECUTE_NUM_BANK ;//[nb_inst_reexecute]
316
317	private : Tcontrol_t * internal_BRANCH_COMPLETE_VAL ;//[nb_inst_branch_complete]
318	private : uint32_t * internal_BRANCH_COMPLETE_NUM_BANK ;//[nb_inst_branch_complete]
319
320	private : Tcontrol_t internal_UPDATE_VAL ;
321	private : uint32_t internal_UPDATE_NUM_BANK ;
322
323	private : Tcontrol_t ** internal_EVENT_ACK ;//[nb_front_end][nb_context]
324
325	private : Tcontrol_t ** internal_RETIRE_EVENT_VAL ;//[nb_front_end][nb_context]
326
327	private : bool *** internal_rat_gpr_update_table;//[nb_front_end][nb_context][nb_general_register_logic]
328	private : bool *** internal_rat_spr_update_table;//[nb_front_end][nb_context][nb_special_register_logic]
329	#endif
330
331	#if defined(DEBUG) and defined(DEBUG_Commit_unit) and (DEBUG_Commit_unit == true)
332	private : std::ofstream * instruction_log_file;
333	#endif
334
335	// -----[ Methods ]---------------------------------------------------
336
337	#ifdef SYSTEMC
338	SC_HAS_PROCESS (Commit_unit);
339	#endif
340	public : Commit_unit
341	(
342	#ifdef SYSTEMC
343	sc_module_name name,
344	#else
345	std::string name,
346	#endif
347	#ifdef STATISTICS
348	morpheo::behavioural::Parameters_Statistics * param_statistics,
349	#endif
350	Parameters * param,
351	morpheo::behavioural::Tusage_t usage
352	);
353	public : ~Commit_unit (void);
354
355	private : void allocation (
356	#ifdef STATISTICS
357	morpheo::behavioural::Parameters_Statistics * param_statistics
358	#else
359	void
360	#endif
361	);
362	private : void deallocation (void);
363
364	#ifdef SYSTEMC
365	public : void constant (void);
366	public : void transition (void);
367	public : void genMoore (void);
368	public : void genMealy_insert (void);
369	public : void genMealy_retire (void);
370	public : void genMealy_commit (void);
371	#endif
372
373	#if VHDL
374	public : void vhdl (void);
375	private : void vhdl_declaration (Vhdl * & vhdl);
376	private : void vhdl_body (Vhdl * & vhdl);
377	#endif
378
379	#ifdef STATISTICS
380	public : void statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics);
381	public : void statistics_deallocation (void);
382	#endif
383	#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
384	private : void end_cycle (void);
385	#endif
386	};
387
388	}; // end namespace commit_unit
389	}; // end namespace ooo_engine
390	}; // end namespace multi_ooo_engine
391	}; // end namespace core
392
393	}; // end namespace behavioural
394	}; // end namespace morpheo
395
396	#endif

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