[88] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id: Commit_unit_genMealy_insert.cpp 88 2008-12-10 18:31:39Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_ooo_engine { |
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| 15 | namespace ooo_engine { |
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| 16 | namespace commit_unit { |
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| 17 | |
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| 18 | |
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| 19 | #undef FUNCTION |
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| 20 | #define FUNCTION "Commit_unit::genMealy_insert" |
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| 21 | void Commit_unit::genMealy_insert (void) |
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| 22 | { |
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| 23 | log_begin(Commit_unit,FUNCTION); |
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| 24 | log_function(Commit_unit,FUNCTION,_name.c_str()); |
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| 25 | |
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| 26 | Tcontrol_t bank_full [_param->_nb_bank]; |
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| 27 | Tcontrol_t insert_ack [_param->_nb_rename_unit][_param->_max_nb_inst_insert]; |
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| 28 | #ifdef SYSTEMC_VHDL_COMPATIBILITY |
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| 29 | Tpacket_t insert_packet_id [_param->_nb_rename_unit][_param->_max_nb_inst_insert]; |
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| 30 | #endif |
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| 31 | bool can_rename_select [_param->_nb_rename_unit]; |
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| 32 | |
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| 33 | // Initialisation |
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| 34 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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| 35 | { |
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| 36 | internal_BANK_INSERT_VAL [i] = false; |
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| 37 | bank_full [i] = not (_rob[i].size() < _param->_size_bank); |
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| 38 | } |
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| 39 | for (uint32_t i=0; i<_param->_nb_rename_unit; i++) |
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| 40 | { |
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| 41 | can_rename_select [i] = true; |
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| 42 | for (uint32_t j=0; j<_param->_nb_inst_insert[i]; j++) |
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| 43 | { |
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| 44 | insert_ack [i][j] = false; |
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| 45 | #ifdef SYSTEMC_VHDL_COMPATIBILITY |
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| 46 | insert_packet_id [i][j] = false; |
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| 47 | #endif |
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| 48 | } |
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| 49 | } |
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| 50 | |
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| 51 | // insert interface |
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| 52 | // log_printf(TRACE,Commit_unit,FUNCTION," * reg_NUM_BANK_TAIL : %d",reg_NUM_BANK_TAIL); |
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| 53 | |
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| 54 | std::list<generic::priority::select_t> * select_insert = _priority_insert ->select(); // same select for all insert |
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| 55 | std::list<generic::priority::select_t>::iterator it=select_insert ->begin(); |
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| 56 | |
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| 57 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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| 58 | { |
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| 59 | // compute the bank number (num_bank_tail is the older write slot) |
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| 60 | uint32_t num_bank = (reg_NUM_BANK_TAIL+i)%_param->_nb_bank; |
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| 61 | |
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| 62 | // log_printf(TRACE,Commit_unit,FUNCTION," * BANK : %d", num_bank); |
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| 63 | // log_printf(TRACE,Commit_unit,FUNCTION," * val : %d", internal_BANK_INSERT_VAL [num_bank]); |
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| 64 | // log_printf(TRACE,Commit_unit,FUNCTION," * full : %d", bank_full [num_bank]); |
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| 65 | |
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| 66 | while (it!=select_insert ->end()) |
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| 67 | { |
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| 68 | uint32_t num_rename_unit = it->grp; |
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| 69 | uint32_t num_inst_insert = it->elt; |
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| 70 | |
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| 71 | it++; |
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| 72 | |
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| 73 | log_printf(TRACE,Commit_unit,FUNCTION," * INSERT [%d][%d]", num_rename_unit,num_inst_insert); |
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| 74 | // log_printf(TRACE,Commit_unit,FUNCTION," * INSERT_VAL : %d", PORT_READ(in_INSERT_VAL [num_rename_unit][num_inst_insert])); |
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| 75 | log_printf(TRACE,Commit_unit,FUNCTION," * can_rename_select : %d", can_rename_select [num_rename_unit]); |
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| 76 | |
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| 77 | // Test if have instruction |
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| 78 | // -> rename_unit_glue test the in-order insert !!!!! |
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| 79 | if (can_rename_select [num_rename_unit] // and |
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| 80 | // PORT_READ(in_INSERT_VAL [num_rename_unit][num_inst_insert]) |
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| 81 | ) |
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| 82 | { |
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| 83 | log_printf(TRACE,Commit_unit,FUNCTION," * have instruction"); |
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| 84 | log_printf(TRACE,Commit_unit,FUNCTION," * bank_full : %d",bank_full [num_bank]); |
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| 85 | |
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| 86 | // test if bank is not busy (full or previous access) |
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| 87 | if (not bank_full [num_bank]) |
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| 88 | { |
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| 89 | // find |
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| 90 | insert_ack [num_rename_unit][num_inst_insert] = true; |
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| 91 | |
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| 92 | Tpacket_t packet_id = ((num_bank << _param->_shift_num_bank) | reg_BANK_PTR [num_bank]); |
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| 93 | |
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| 94 | #ifdef SYSTEMC_VHDL_COMPATIBILITY |
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| 95 | insert_packet_id [num_rename_unit][num_inst_insert] = packet_id; |
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| 96 | #else |
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| 97 | if (_param->_have_port_rob_ptr ) |
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| 98 | PORT_WRITE(out_INSERT_PACKET_ID [num_rename_unit][num_inst_insert],packet_id); |
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| 99 | #endif |
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| 100 | internal_BANK_INSERT_VAL [num_bank] = true; |
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| 101 | internal_BANK_INSERT_NUM_RENAME_UNIT [num_bank] = num_rename_unit; |
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| 102 | internal_BANK_INSERT_NUM_INST [num_bank] = num_inst_insert; |
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| 103 | |
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| 104 | break; |
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| 105 | } |
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| 106 | } |
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| 107 | |
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| 108 | // is a valid instruction, but it's not send at a bank |
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| 109 | // ... invalid this rename_unit (because, insert in_order) |
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| 110 | can_rename_select [num_rename_unit] = false; |
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| 111 | } |
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| 112 | } |
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| 113 | |
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| 114 | for (uint32_t i=0; i<_param->_nb_rename_unit; i++) |
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| 115 | for (uint32_t j=0; j<_param->_nb_inst_insert[i]; j++) |
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| 116 | { |
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| 117 | PORT_WRITE(out_INSERT_ACK [i][j],insert_ack [i][j]); |
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| 118 | log_printf(TRACE,Commit_unit,FUNCTION," * INSERT [%d][%d] -> ack %d",i,j,insert_ack[i][j]); |
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| 119 | |
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| 120 | #ifdef SYSTEMC_VHDL_COMPATIBILITY |
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| 121 | if (_param->_have_port_rob_ptr ) |
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| 122 | PORT_WRITE(out_INSERT_PACKET_ID [i][j],insert_packet_id [i][j]); |
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| 123 | #endif |
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| 124 | } |
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| 125 | |
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| 126 | log_end(Commit_unit,FUNCTION); |
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| 127 | }; |
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| 128 | |
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| 129 | }; // end namespace commit_unit |
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| 130 | }; // end namespace ooo_engine |
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| 131 | }; // end namespace multi_ooo_engine |
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| 132 | }; // end namespace core |
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| 133 | }; // end namespace behavioural |
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| 134 | }; // end namespace morpheo |
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| 135 | #endif |
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