1 | #ifdef SYSTEMC |
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2 | /* |
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3 | * $Id: Commit_unit_genMealy_insert.cpp 124 2009-06-17 12:11:25Z rosiere $ |
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4 | * |
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5 | * [ Description ] |
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6 | * |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | namespace core { |
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14 | namespace multi_ooo_engine { |
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15 | namespace ooo_engine { |
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16 | namespace commit_unit { |
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17 | |
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18 | |
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19 | #undef FUNCTION |
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20 | #define FUNCTION "Commit_unit::genMealy_insert" |
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21 | void Commit_unit::genMealy_insert (void) |
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22 | { |
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23 | log_begin(Commit_unit,FUNCTION); |
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24 | log_function(Commit_unit,FUNCTION,_name.c_str()); |
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25 | |
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26 | if (PORT_READ(in_NRESET)) |
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27 | { |
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28 | Tcontrol_t bank_full [_param->_nb_bank]; |
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29 | Tcontrol_t insert_ack [_param->_nb_rename_unit][_param->_max_nb_inst_insert]; |
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30 | #ifdef SYSTEMC_VHDL_COMPATIBILITY |
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31 | Tpacket_t insert_packet_id [_param->_nb_rename_unit][_param->_max_nb_inst_insert]; |
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32 | #endif |
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33 | bool can_rename_select [_param->_nb_rename_unit]; |
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34 | // bool event_stop; |
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35 | |
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36 | // // Initialisation |
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37 | // event_stop = false; // one signal for all context. |
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38 | // for (uint32_t i=0; i<_param->_nb_front_end; ++i) |
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39 | // for (uint32_t j=0; j<_param->_nb_context[i]; ++j) |
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40 | // event_stop |= reg_EVENT_STOP [i][j]; |
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41 | |
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42 | // Initialisation |
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43 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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44 | { |
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45 | internal_BANK_INSERT_VAL [i] = false; |
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46 | bank_full [i] = not (_rob[i].size() < _param->_size_bank); |
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47 | } |
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48 | for (uint32_t i=0; i<_param->_nb_rename_unit; i++) |
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49 | { |
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50 | can_rename_select [i] = true; |
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51 | for (uint32_t j=0; j<_param->_nb_inst_insert[i]; j++) |
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52 | { |
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53 | insert_ack [i][j] = false; |
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54 | #ifdef SYSTEMC_VHDL_COMPATIBILITY |
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55 | insert_packet_id [i][j] = false; |
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56 | #endif |
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57 | } |
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58 | } |
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59 | |
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60 | // insert interface |
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61 | // log_printf(TRACE,Commit_unit,FUNCTION," * reg_NUM_BANK_TAIL : %d",reg_NUM_BANK_TAIL); |
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62 | |
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63 | // if (not event_stop) |
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64 | { |
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65 | std::list<generic::priority::select_t> * select_insert = _priority_insert ->select(); // same select for all insert |
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66 | std::list<generic::priority::select_t>::iterator it=select_insert ->begin(); |
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67 | |
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68 | // Scan all bank ... |
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69 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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70 | { |
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71 | // compute the bank number (num_bank_tail is the older write slot) |
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72 | uint32_t num_bank = (reg_NUM_BANK_TAIL+i)%_param->_nb_bank; |
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73 | |
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74 | // log_printf(TRACE,Commit_unit,FUNCTION," * BANK : %d", num_bank); |
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75 | // log_printf(TRACE,Commit_unit,FUNCTION," * val : %d", internal_BANK_INSERT_VAL [num_bank]); |
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76 | // log_printf(TRACE,Commit_unit,FUNCTION," * full : %d", bank_full [num_bank]); |
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77 | |
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78 | // Scan all insert interface to find a valid transaction |
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79 | while (it!=select_insert ->end()) |
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80 | { |
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81 | uint32_t num_rename_unit = it->grp; |
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82 | uint32_t num_inst_insert = it->elt; |
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83 | |
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84 | it++; |
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85 | |
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86 | log_printf(TRACE,Commit_unit,FUNCTION," * INSERT [%d][%d]", num_rename_unit,num_inst_insert); |
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87 | // log_printf(TRACE,Commit_unit,FUNCTION," * INSERT_VAL : %d", PORT_READ(in_INSERT_VAL [num_rename_unit][num_inst_insert])); |
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88 | log_printf(TRACE,Commit_unit,FUNCTION," * can_rename_select : %d", can_rename_select [num_rename_unit]); |
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89 | |
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90 | // Test if have instruction |
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91 | // -> rename_unit_glue test the in-order insert !!!!! |
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92 | if (can_rename_select [num_rename_unit] // and |
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93 | // PORT_READ(in_INSERT_VAL [num_rename_unit][num_inst_insert]) |
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94 | ) |
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95 | { |
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96 | log_printf(TRACE,Commit_unit,FUNCTION," * have instruction"); |
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97 | log_printf(TRACE,Commit_unit,FUNCTION," * num_bank : %d",num_bank); |
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98 | log_printf(TRACE,Commit_unit,FUNCTION," * bank_full : %d",bank_full [num_bank]); |
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99 | |
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100 | // test if bank is not busy (full or previous access) |
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101 | if (not bank_full [num_bank]) |
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102 | { |
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103 | // find !!! |
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104 | insert_ack [num_rename_unit][num_inst_insert] = true; |
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105 | |
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106 | Tpacket_t packet_id = ((reg_BANK_PTR [num_bank] << _param->_shift_num_slot) | num_bank); |
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107 | |
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108 | #ifdef SYSTEMC_VHDL_COMPATIBILITY |
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109 | insert_packet_id [num_rename_unit][num_inst_insert] = packet_id; |
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110 | #else |
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111 | if (_param->_have_port_rob_ptr ) |
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112 | PORT_WRITE(out_INSERT_PACKET_ID [num_rename_unit][num_inst_insert],packet_id); |
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113 | #endif |
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114 | internal_BANK_INSERT_VAL [num_bank] = true; |
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115 | internal_BANK_INSERT_NUM_RENAME_UNIT [num_bank] = num_rename_unit; |
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116 | internal_BANK_INSERT_NUM_INST [num_bank] = num_inst_insert; |
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117 | |
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118 | break; |
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119 | } |
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120 | } |
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121 | |
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122 | // is a valid instruction, but it's not send at a bank |
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123 | // ... invalid this rename_unit (because, insert in_order) |
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124 | can_rename_select [num_rename_unit] = false; |
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125 | } |
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126 | } |
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127 | } |
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128 | |
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129 | // Write output |
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130 | for (uint32_t i=0; i<_param->_nb_rename_unit; i++) |
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131 | for (uint32_t j=0; j<_param->_nb_inst_insert[i]; j++) |
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132 | { |
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133 | PORT_WRITE(out_INSERT_ACK [i][j],insert_ack [i][j]); |
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134 | log_printf(TRACE,Commit_unit,FUNCTION," * INSERT [%d][%d] -> ack %d",i,j,insert_ack[i][j]); |
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135 | |
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136 | #ifdef SYSTEMC_VHDL_COMPATIBILITY |
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137 | if (_param->_have_port_rob_ptr ) |
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138 | PORT_WRITE(out_INSERT_PACKET_ID [i][j],insert_packet_id [i][j]); |
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139 | #endif |
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140 | } |
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141 | } |
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142 | else |
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143 | { |
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144 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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145 | internal_BANK_INSERT_VAL [i] = false; |
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146 | for (uint32_t i=0; i<_param->_nb_rename_unit; i++) |
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147 | for (uint32_t j=0; j<_param->_nb_inst_insert[i]; j++) |
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148 | PORT_WRITE(out_INSERT_ACK [i][j],0); |
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149 | |
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150 | } |
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151 | |
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152 | log_end(Commit_unit,FUNCTION); |
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153 | }; |
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154 | |
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155 | }; // end namespace commit_unit |
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156 | }; // end namespace ooo_engine |
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157 | }; // end namespace multi_ooo_engine |
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158 | }; // end namespace core |
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159 | }; // end namespace behavioural |
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160 | }; // end namespace morpheo |
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161 | #endif |
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