[88] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id: Commit_unit_genMealy_retire.cpp 88 2008-12-10 18:31:39Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_ooo_engine { |
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| 15 | namespace ooo_engine { |
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| 16 | namespace commit_unit { |
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| 17 | |
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| 18 | |
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| 19 | #undef FUNCTION |
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| 20 | #define FUNCTION "Commit_unit::genMealy_retire" |
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| 21 | void Commit_unit::genMealy_retire (void) |
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| 22 | { |
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| 23 | log_begin(Commit_unit,FUNCTION); |
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| 24 | log_function(Commit_unit,FUNCTION,_name.c_str()); |
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| 25 | |
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| 26 | Tcontrol_t retire_val [_param->_nb_rename_unit][_param->_max_nb_inst_retire]; |
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| 27 | uint32_t num_inst_retire [_param->_nb_rename_unit]; |
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| 28 | bool can_retire [_param->_nb_rename_unit]; |
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| 29 | |
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| 30 | Tcontrol_t spr_write_val [_param->_nb_front_end][_param->_max_nb_context]; |
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| 31 | Tcontrol_t spr_write_sr_f_val [_param->_nb_front_end][_param->_max_nb_context]; |
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| 32 | Tcontrol_t spr_write_sr_f [_param->_nb_front_end][_param->_max_nb_context]; |
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| 33 | Tcontrol_t spr_write_sr_cy_val [_param->_nb_front_end][_param->_max_nb_context]; |
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| 34 | Tcontrol_t spr_write_sr_cy [_param->_nb_front_end][_param->_max_nb_context]; |
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| 35 | Tcontrol_t spr_write_sr_ov_val [_param->_nb_front_end][_param->_max_nb_context]; |
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| 36 | Tcontrol_t spr_write_sr_ov [_param->_nb_front_end][_param->_max_nb_context]; |
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| 37 | |
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| 38 | |
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| 39 | // Initialisation |
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| 40 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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| 41 | internal_BANK_RETIRE_VAL [i] = false; |
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| 42 | |
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| 43 | for (uint32_t i=0; i<_param->_nb_rename_unit; i++) |
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| 44 | { |
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| 45 | num_inst_retire [i] = 0; |
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| 46 | can_retire [i] = true ; |
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| 47 | for (uint32_t j=0; j<_param->_nb_inst_retire[i]; j++) |
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| 48 | retire_val [i][j] = false; |
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| 49 | } |
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| 50 | |
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| 51 | for (uint32_t i=0; i<_param->_nb_front_end; ++i) |
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| 52 | for (uint32_t j=0; j<_param->_nb_context[i]; ++j) |
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| 53 | spr_write_val [i][j] = 0; |
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| 54 | |
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| 55 | // Scan Top of each bank |
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| 56 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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| 57 | { |
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| 58 | uint32_t num_bank = (reg_NUM_BANK_HEAD+i)%_param->_nb_bank; |
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| 59 | |
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| 60 | if (not _rob[num_bank].empty()) |
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| 61 | { |
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| 62 | // Scan all instruction in windows and test if instruction is speculative |
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| 63 | entry_t * entry = _rob [num_bank].front(); |
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| 64 | uint32_t x = entry->rename_unit_id; |
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| 65 | uint32_t y = num_inst_retire [x]; |
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| 66 | |
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| 67 | if (can_retire [x] and // in-order |
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| 68 | (y < _param->_nb_inst_retire [x]) and |
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| 69 | PORT_READ(in_RETIRE_ACK [x][y])) // not busy |
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| 70 | { |
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| 71 | rob_state_t state = entry->state; |
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| 72 | |
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| 73 | if ((state == ROB_END_OK ) or |
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| 74 | (state == ROB_END_KO ) or |
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| 75 | (state == ROB_END_MISS)// or |
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| 76 | // (state == ROB_END_EXCEPTION) |
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| 77 | ) |
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| 78 | { |
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| 79 | Tcontext_t front_end_id = entry->front_end_id; |
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| 80 | Tcontext_t context_id = entry->context_id; |
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| 81 | Tcontrol_t write_re = entry->write_re; |
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| 82 | Tspecial_address_t num_reg_re_log = entry->num_reg_re_log; |
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| 83 | |
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| 84 | // if state is ok, when write flags in the SR regsiters |
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| 85 | bool spr_write_ack = true; |
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| 86 | |
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| 87 | if ((state == ROB_END_OK ) and write_re) |
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| 88 | { |
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| 89 | spr_write_ack = PORT_READ(in_SPR_WRITE_ACK [front_end_id][context_id]); |
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| 90 | |
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| 91 | // retire_ack is set !!! |
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| 92 | spr_write_val [front_end_id][context_id] = 1; |
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| 93 | |
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| 94 | Tspecial_data_t flags = entry->flags; |
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| 95 | |
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| 96 | switch (num_reg_re_log) |
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| 97 | { |
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| 98 | case SPR_LOGIC_SR_F : |
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| 99 | { |
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| 100 | spr_write_sr_f_val [front_end_id][context_id] = 1; |
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| 101 | spr_write_sr_f [front_end_id][context_id] = (flags & FLAG_F )!=0; |
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| 102 | |
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| 103 | break; |
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| 104 | } |
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| 105 | case SPR_LOGIC_SR_CY_OV : |
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| 106 | { |
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| 107 | spr_write_sr_cy_val [front_end_id][context_id] = 1; |
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| 108 | spr_write_sr_ov_val [front_end_id][context_id] = 1; |
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| 109 | spr_write_sr_cy [front_end_id][context_id] = (flags & FLAG_CY)!=0; |
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| 110 | spr_write_sr_ov [front_end_id][context_id] = (flags & FLAG_OV)!=0; |
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| 111 | |
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| 112 | break; |
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| 113 | } |
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| 114 | default : |
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| 115 | { |
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| 116 | #ifdef DEBUG_TEST |
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| 117 | throw ERRORMORPHEO(FUNCTION,_("Invalid num_reg_re_log.\n")); |
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| 118 | #endif |
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| 119 | } |
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| 120 | } |
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| 121 | } |
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| 122 | |
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| 123 | // find an instruction can be retire, and in order |
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| 124 | |
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| 125 | if (spr_write_ack) |
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| 126 | { |
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| 127 | retire_val [x][y] = 1; |
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| 128 | num_inst_retire [x] ++; |
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| 129 | internal_BANK_RETIRE_VAL [num_bank] = true; |
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| 130 | } |
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| 131 | |
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| 132 | internal_BANK_RETIRE_NUM_RENAME_UNIT [num_bank] = x; |
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| 133 | internal_BANK_RETIRE_NUM_INST [num_bank] = y; |
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| 134 | |
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| 135 | if (_param->_have_port_front_end_id) |
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| 136 | PORT_WRITE(out_RETIRE_FRONT_END_ID [x][y], front_end_id ); |
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| 137 | if (_param->_have_port_context_id) |
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| 138 | PORT_WRITE(out_RETIRE_CONTEXT_ID [x][y], context_id ); |
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| 139 | // PORT_WRITE(out_RETIRE_RENAME_UNIT_ID [x][y], entry->rename_unit_id ); |
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| 140 | PORT_WRITE(out_RETIRE_EVENT_STATE [x][y], entry->event_state ); |
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| 141 | PORT_WRITE(out_RETIRE_USE_STORE_QUEUE [x][y], entry->use_store_queue ); |
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| 142 | PORT_WRITE(out_RETIRE_USE_LOAD_QUEUE [x][y], entry->use_load_queue ); |
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| 143 | PORT_WRITE(out_RETIRE_STORE_QUEUE_PTR_WRITE [x][y], entry->store_queue_ptr_write); |
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| 144 | if (_param->_have_port_load_queue_ptr) |
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| 145 | PORT_WRITE(out_RETIRE_LOAD_QUEUE_PTR_WRITE [x][y], entry->load_queue_ptr_write ); |
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| 146 | PORT_WRITE(out_RETIRE_READ_RA [x][y], entry->read_ra ); |
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| 147 | PORT_WRITE(out_RETIRE_NUM_REG_RA_PHY [x][y], entry->num_reg_ra_phy ); |
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| 148 | PORT_WRITE(out_RETIRE_READ_RB [x][y], entry->read_rb ); |
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| 149 | PORT_WRITE(out_RETIRE_NUM_REG_RB_PHY [x][y], entry->num_reg_rb_phy ); |
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| 150 | PORT_WRITE(out_RETIRE_READ_RC [x][y], entry->read_rc ); |
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| 151 | PORT_WRITE(out_RETIRE_NUM_REG_RC_PHY [x][y], entry->num_reg_rc_phy ); |
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| 152 | PORT_WRITE(out_RETIRE_WRITE_RD [x][y], entry->write_rd ); |
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| 153 | PORT_WRITE(out_RETIRE_NUM_REG_RD_LOG [x][y], entry->num_reg_rd_log ); |
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| 154 | PORT_WRITE(out_RETIRE_NUM_REG_RD_PHY_OLD [x][y], entry->num_reg_rd_phy_old ); |
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| 155 | PORT_WRITE(out_RETIRE_NUM_REG_RD_PHY_NEW [x][y], entry->num_reg_rd_phy_new ); |
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| 156 | PORT_WRITE(out_RETIRE_WRITE_RE [x][y], write_re ); |
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| 157 | PORT_WRITE(out_RETIRE_NUM_REG_RE_LOG [x][y], num_reg_re_log ); |
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| 158 | PORT_WRITE(out_RETIRE_NUM_REG_RE_PHY_OLD [x][y], entry->num_reg_re_phy_old ); |
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| 159 | PORT_WRITE(out_RETIRE_NUM_REG_RE_PHY_NEW [x][y], entry->num_reg_re_phy_new ); |
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| 160 | } |
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| 161 | } |
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| 162 | |
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| 163 | // Retire "in-order" |
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| 164 | can_retire [x] &= retire_val [x][y]; |
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| 165 | } |
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| 166 | } |
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| 167 | |
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| 168 | for (uint32_t i=0; i<_param->_nb_rename_unit; i++) |
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| 169 | for (uint32_t j=0; j<_param->_nb_inst_retire[i]; j++) |
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| 170 | PORT_WRITE(out_RETIRE_VAL [i][j],retire_val [i][j]); |
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| 171 | |
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| 172 | for (uint32_t i=0; i<_param->_nb_front_end; ++i) |
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| 173 | for (uint32_t j=0; j<_param->_nb_context[i]; ++j) |
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| 174 | { |
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| 175 | PORT_WRITE(out_SPR_WRITE_VAL [i][j], spr_write_val [i][j]); |
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| 176 | PORT_WRITE(out_SPR_WRITE_SR_F_VAL [i][j], spr_write_sr_f_val [i][j]); |
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| 177 | PORT_WRITE(out_SPR_WRITE_SR_F [i][j], spr_write_sr_f [i][j]); |
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| 178 | PORT_WRITE(out_SPR_WRITE_SR_CY_VAL [i][j], spr_write_sr_cy_val [i][j]); |
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| 179 | PORT_WRITE(out_SPR_WRITE_SR_CY [i][j], spr_write_sr_cy [i][j]); |
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| 180 | PORT_WRITE(out_SPR_WRITE_SR_OV_VAL [i][j], spr_write_sr_ov_val [i][j]); |
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| 181 | PORT_WRITE(out_SPR_WRITE_SR_OV [i][j], spr_write_sr_ov [i][j]); |
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| 182 | } |
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| 183 | |
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| 184 | log_end(Commit_unit,FUNCTION); |
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| 185 | }; |
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| 186 | |
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| 187 | }; // end namespace commit_unit |
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| 188 | }; // end namespace ooo_engine |
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| 189 | }; // end namespace multi_ooo_engine |
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| 190 | }; // end namespace core |
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| 191 | }; // end namespace behavioural |
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| 192 | }; // end namespace morpheo |
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| 193 | #endif |
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