1 | #ifdef SYSTEMC |
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2 | /* |
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3 | * $Id: Commit_unit_genMealy_retire.cpp 133 2009-07-13 15:19:10Z rosiere $ |
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4 | * |
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5 | * [ Description ] |
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6 | * |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | namespace core { |
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14 | namespace multi_ooo_engine { |
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15 | namespace ooo_engine { |
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16 | namespace commit_unit { |
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17 | |
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18 | |
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19 | #undef FUNCTION |
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20 | #define FUNCTION "Commit_unit::genMealy_retire" |
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21 | void Commit_unit::genMealy_retire (void) |
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22 | { |
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23 | log_begin(Commit_unit,FUNCTION); |
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24 | log_function(Commit_unit,FUNCTION,_name.c_str()); |
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25 | |
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26 | if (PORT_READ(in_NRESET)) |
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27 | { |
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28 | Tcontrol_t retire_val [_param->_nb_rename_unit][_param->_max_nb_inst_retire]; |
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29 | uint32_t num_inst_retire [_param->_nb_rename_unit]; |
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30 | bool can_retire [_param->_nb_rename_unit]; |
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31 | |
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32 | Tcontrol_t spr_write_val [_param->_nb_front_end][_param->_max_nb_context]; |
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33 | Tcontrol_t spr_write_sr_f_val [_param->_nb_front_end][_param->_max_nb_context]; |
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34 | Tcontrol_t spr_write_sr_f [_param->_nb_front_end][_param->_max_nb_context]; |
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35 | Tcontrol_t spr_write_sr_cy_val [_param->_nb_front_end][_param->_max_nb_context]; |
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36 | Tcontrol_t spr_write_sr_cy [_param->_nb_front_end][_param->_max_nb_context]; |
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37 | Tcontrol_t spr_write_sr_ov_val [_param->_nb_front_end][_param->_max_nb_context]; |
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38 | Tcontrol_t spr_write_sr_ov [_param->_nb_front_end][_param->_max_nb_context]; |
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39 | |
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40 | // Initialisation |
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41 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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42 | internal_BANK_RETIRE_VAL [i] = false; |
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43 | |
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44 | for (uint32_t i=0; i<_param->_nb_rename_unit; i++) |
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45 | { |
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46 | num_inst_retire [i] = 0; |
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47 | can_retire [i] = true ; |
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48 | for (uint32_t j=0; j<_param->_nb_inst_retire[i]; j++) |
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49 | retire_val [i][j] = false; |
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50 | } |
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51 | for (uint32_t i=0; i<_param->_nb_front_end; ++i) |
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52 | for (uint32_t j=0; j<_param->_nb_context[i]; ++j) |
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53 | { |
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54 | spr_write_val [i][j] = 0; |
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55 | spr_write_sr_f_val [i][j] = 0; |
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56 | spr_write_sr_cy_val [i][j] = 0; |
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57 | spr_write_sr_ov_val [i][j] = 0; |
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58 | |
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59 | spr_write_sr_f [i][j] = 0; // not necessary |
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60 | spr_write_sr_cy [i][j] = 0; // not necessary |
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61 | spr_write_sr_ov [i][j] = 0; // not necessary |
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62 | } |
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63 | |
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64 | // Scan Top of each bank |
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65 | internal_BANK_RETIRE_HEAD = reg_NUM_BANK_HEAD; |
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66 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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67 | { |
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68 | uint32_t num_bank = (internal_BANK_RETIRE_HEAD+i)%_param->_nb_bank; |
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69 | |
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70 | log_printf(TRACE,Commit_unit,FUNCTION," * BANK [%d]",num_bank); |
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71 | |
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72 | // Test if have instruction |
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73 | if (not _rob[num_bank].empty()) |
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74 | { |
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75 | // Scan all instruction in windows and test if instruction is speculative |
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76 | entry_t * entry = _rob [num_bank].front(); |
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77 | uint32_t x = entry->rename_unit_id; |
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78 | uint32_t y = num_inst_retire [x]; |
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79 | |
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80 | log_printf(TRACE,Commit_unit,FUNCTION," * num_rename_unit : %d",x); |
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81 | log_printf(TRACE,Commit_unit,FUNCTION," * num_inst_retire : %d",y); |
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82 | |
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83 | if (y < _param->_nb_inst_retire [x]) |
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84 | { |
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85 | #ifdef DEBUG_TEST |
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86 | if (x >= _param->_nb_rename_unit) |
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87 | throw ERRORMORPHEO(FUNCTION,toString(_("Invalid rename_unit number (%d, max is %d).\n"),x,_param->_nb_rename_unit)); |
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88 | #endif |
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89 | bool bypass= false; |
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90 | |
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91 | log_printf(TRACE,Commit_unit,FUNCTION," * can_retire : %d",can_retire [x]); |
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92 | log_printf(TRACE,Commit_unit,FUNCTION," * RETIRE_ACK : %d",PORT_READ(in_RETIRE_ACK [x][y])); |
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93 | |
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94 | // test if : |
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95 | // * can retire (all previous instruction is retired) |
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96 | // * all structure is ok (not busy) |
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97 | if (can_retire [x] and // in-order |
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98 | PORT_READ(in_RETIRE_ACK [x][y])) // not busy |
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99 | { |
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100 | log_printf(TRACE,Commit_unit,FUNCTION," * valid !!!"); |
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101 | |
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102 | rob_state_t state = entry->state; |
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103 | Tcontext_t front_end_id = entry->front_end_id; |
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104 | Tcontext_t context_id = entry->context_id; |
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105 | |
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106 | log_printf(TRACE,Commit_unit,FUNCTION," * state : %s",toString(state).c_str()); |
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107 | log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id); |
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108 | log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id ); |
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109 | |
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110 | if ((state == ROB_END_OK ) or |
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111 | (state == ROB_END_KO ) or |
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112 | (state == ROB_END_BRANCH_MISS) or |
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113 | (state == ROB_END_LOAD_MISS ) or |
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114 | (state == ROB_END_MISS )// or |
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115 | // (state == ROB_END_EXCEPTION) |
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116 | ) |
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117 | { |
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118 | Tcontrol_t write_re = entry->write_re; |
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119 | Tspecial_address_t num_reg_re_log = entry->num_reg_re_log; |
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120 | |
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121 | // if state is ok, when write flags in the SR regsiters |
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122 | bool spr_write_ack = true; |
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123 | |
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124 | // Write in SR the good flag |
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125 | if ((state == ROB_END_OK ) and write_re) |
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126 | // ROB_END_BRANCH_MISS is a valid branch instruction but don't modify RE |
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127 | { |
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128 | log_printf(TRACE,Commit_unit,FUNCTION," * need write SR flags"); |
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129 | log_printf(TRACE,Commit_unit,FUNCTION," * SPR_WRITE_ACK : %d",PORT_READ(in_SPR_WRITE_ACK [front_end_id][context_id])); |
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130 | |
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131 | spr_write_ack = PORT_READ(in_SPR_WRITE_ACK [front_end_id][context_id]); |
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132 | |
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133 | // retire_ack is set !!! |
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134 | spr_write_val [front_end_id][context_id] = 1; |
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135 | |
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136 | Tspecial_data_t flags = entry->flags; |
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137 | |
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138 | switch (num_reg_re_log) |
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139 | { |
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140 | case SPR_LOGIC_SR_F : |
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141 | { |
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142 | spr_write_sr_f_val [front_end_id][context_id] = 1; |
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143 | spr_write_sr_f [front_end_id][context_id] = (flags & FLAG_F )!=0; |
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144 | |
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145 | break; |
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146 | } |
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147 | case SPR_LOGIC_SR_CY_OV : |
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148 | { |
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149 | spr_write_sr_cy_val [front_end_id][context_id] = 1; |
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150 | spr_write_sr_ov_val [front_end_id][context_id] = 1; |
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151 | spr_write_sr_cy [front_end_id][context_id] = (flags & FLAG_CY)!=0; |
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152 | spr_write_sr_ov [front_end_id][context_id] = (flags & FLAG_OV)!=0; |
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153 | |
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154 | break; |
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155 | } |
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156 | default : |
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157 | { |
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158 | #ifdef DEBUG_TEST |
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159 | throw ERRORMORPHEO(FUNCTION,_("Invalid num_reg_re_log.\n")); |
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160 | #endif |
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161 | } |
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162 | } |
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163 | } |
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164 | |
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165 | // find an instruction can be retire, and in order |
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166 | |
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167 | if (spr_write_ack) |
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168 | { |
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169 | retire_val [x][y] = 1; |
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170 | num_inst_retire [x] ++; |
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171 | internal_BANK_RETIRE_VAL [num_bank] = true; |
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172 | } |
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173 | |
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174 | internal_BANK_RETIRE_NUM_RENAME_UNIT [num_bank] = x; |
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175 | internal_BANK_RETIRE_NUM_INST [num_bank] = y; |
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176 | |
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177 | if (_param->_have_port_front_end_id) |
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178 | PORT_WRITE(out_RETIRE_FRONT_END_ID [x][y], front_end_id ); |
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179 | if (_param->_have_port_context_id) |
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180 | PORT_WRITE(out_RETIRE_CONTEXT_ID [x][y], context_id ); |
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181 | // PORT_WRITE(out_RETIRE_RENAME_UNIT_ID [x][y], entry->rename_unit_id ); |
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182 | PORT_WRITE(out_RETIRE_USE_STORE_QUEUE [x][y], entry->use_store_queue ); |
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183 | PORT_WRITE(out_RETIRE_USE_LOAD_QUEUE [x][y], entry->use_load_queue ); |
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184 | PORT_WRITE(out_RETIRE_STORE_QUEUE_PTR_WRITE [x][y], entry->store_queue_ptr_write); |
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185 | if (_param->_have_port_load_queue_ptr) |
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186 | PORT_WRITE(out_RETIRE_LOAD_QUEUE_PTR_WRITE [x][y], entry->load_queue_ptr_write ); |
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187 | // PORT_WRITE(out_RETIRE_READ_RA [x][y], entry->read_ra ); |
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188 | // PORT_WRITE(out_RETIRE_NUM_REG_RA_PHY [x][y], entry->num_reg_ra_phy ); |
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189 | // PORT_WRITE(out_RETIRE_READ_RB [x][y], entry->read_rb ); |
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190 | // PORT_WRITE(out_RETIRE_NUM_REG_RB_PHY [x][y], entry->num_reg_rb_phy ); |
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191 | // PORT_WRITE(out_RETIRE_READ_RC [x][y], entry->read_rc ); |
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192 | // PORT_WRITE(out_RETIRE_NUM_REG_RC_PHY [x][y], entry->num_reg_rc_phy ); |
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193 | PORT_WRITE(out_RETIRE_WRITE_RD [x][y], entry->write_rd ); |
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194 | PORT_WRITE(out_RETIRE_NUM_REG_RD_LOG [x][y], entry->num_reg_rd_log ); |
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195 | PORT_WRITE(out_RETIRE_NUM_REG_RD_PHY_OLD [x][y], entry->num_reg_rd_phy_old ); |
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196 | PORT_WRITE(out_RETIRE_NUM_REG_RD_PHY_NEW [x][y], entry->num_reg_rd_phy_new ); |
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197 | PORT_WRITE(out_RETIRE_WRITE_RE [x][y], write_re ); |
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198 | PORT_WRITE(out_RETIRE_NUM_REG_RE_LOG [x][y], num_reg_re_log ); |
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199 | PORT_WRITE(out_RETIRE_NUM_REG_RE_PHY_OLD [x][y], entry->num_reg_re_phy_old ); |
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200 | PORT_WRITE(out_RETIRE_NUM_REG_RE_PHY_NEW [x][y], entry->num_reg_re_phy_new ); |
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201 | |
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202 | // Event -> rob must be manage this event |
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203 | if ((state == ROB_END_BRANCH_MISS) or |
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204 | (state == ROB_END_LOAD_MISS)) |
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205 | can_retire [x] = false; |
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206 | } |
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207 | |
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208 | log_printf(TRACE,Commit_unit,FUNCTION," * bypass (before) : %d",bypass); |
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209 | |
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210 | bypass = ((state == ROB_END ) or |
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211 | (state == ROB_STORE_OK ) or |
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212 | (state == ROB_STORE_KO ) or |
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213 | (state == ROB_STORE_OK_WAIT_END) or |
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214 | (state == ROB_STORE_KO_WAIT_END)); |
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215 | |
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216 | log_printf(TRACE,Commit_unit,FUNCTION," * bypass (after) : %d",bypass); |
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217 | |
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218 | uint32_t packet = ((entry->ptr << _param->_shift_num_slot) | num_bank); |
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219 | |
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220 | log_printf(TRACE,Commit_unit,FUNCTION," * packet : %d",packet); |
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221 | |
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222 | // if future event, don't update after this event |
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223 | if ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_NOT_YET_EVENT) and |
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224 | (reg_EVENT_PACKET [front_end_id][context_id] == packet)) |
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225 | { |
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226 | log_printf(TRACE,Commit_unit,FUNCTION," * is the event instruction, stop bypass !!!"); |
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227 | bypass = false; |
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228 | } |
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229 | } |
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230 | |
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231 | // Retire "in-order" |
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232 | can_retire [x] &= (retire_val [x][y] or bypass); |
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233 | } |
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234 | } |
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235 | } |
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236 | |
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237 | for (uint32_t i=0; i<_param->_nb_rename_unit; i++) |
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238 | for (uint32_t j=0; j<_param->_nb_inst_retire[i]; j++) |
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239 | PORT_WRITE(out_RETIRE_VAL [i][j],retire_val [i][j]); |
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240 | |
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241 | for (uint32_t i=0; i<_param->_nb_front_end; ++i) |
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242 | for (uint32_t j=0; j<_param->_nb_context[i]; ++j) |
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243 | { |
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244 | PORT_WRITE(out_SPR_WRITE_VAL [i][j], spr_write_val [i][j]); |
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245 | PORT_WRITE(out_SPR_WRITE_SR_F_VAL [i][j], spr_write_sr_f_val [i][j]); |
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246 | PORT_WRITE(out_SPR_WRITE_SR_F [i][j], spr_write_sr_f [i][j]); |
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247 | PORT_WRITE(out_SPR_WRITE_SR_CY_VAL [i][j], spr_write_sr_cy_val [i][j]); |
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248 | PORT_WRITE(out_SPR_WRITE_SR_CY [i][j], spr_write_sr_cy [i][j]); |
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249 | PORT_WRITE(out_SPR_WRITE_SR_OV_VAL [i][j], spr_write_sr_ov_val [i][j]); |
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250 | PORT_WRITE(out_SPR_WRITE_SR_OV [i][j], spr_write_sr_ov [i][j]); |
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251 | } |
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252 | } |
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253 | else |
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254 | { |
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255 | for (uint32_t i=0; i<_param->_nb_rename_unit; i++) |
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256 | for (uint32_t j=0; j<_param->_nb_inst_retire[i]; j++) |
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257 | PORT_WRITE(out_RETIRE_VAL [i][j],0); |
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258 | |
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259 | for (uint32_t i=0; i<_param->_nb_front_end; ++i) |
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260 | for (uint32_t j=0; j<_param->_nb_context[i]; ++j) |
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261 | PORT_WRITE(out_SPR_WRITE_VAL [i][j], 0); |
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262 | } |
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263 | |
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264 | log_end(Commit_unit,FUNCTION); |
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265 | }; |
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266 | |
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267 | }; // end namespace commit_unit |
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268 | }; // end namespace ooo_engine |
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269 | }; // end namespace multi_ooo_engine |
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270 | }; // end namespace core |
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271 | }; // end namespace behavioural |
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272 | }; // end namespace morpheo |
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273 | #endif |
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