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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp @ 121

Last change on this file since 121 was 121, checked in by rosiere, 15 years ago
1) Commit_unit : remove read information of ROB
Property svn:keywords set to `Id`
File size: 9.6 KB

Line
1	#ifdef SYSTEMC
2	/*
3	* $Id: Commit_unit_genMealy_retire.cpp 121 2009-05-27 10:13:56Z rosiere $
4	*
5	* [ Description ]
6	*
7	*/
8
9	#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_ooo_engine {
15	namespace ooo_engine {
16	namespace commit_unit {
17
18
19	#undef FUNCTION
20	#define FUNCTION "Commit_unit::genMealy_retire"
21	void Commit_unit::genMealy_retire (void)
22	{
23	log_begin(Commit_unit,FUNCTION);
24	log_function(Commit_unit,FUNCTION,_name.c_str());
25
26	Tcontrol_t retire_val [_param->_nb_rename_unit][_param->_max_nb_inst_retire];
27	uint32_t num_inst_retire [_param->_nb_rename_unit];
28	bool can_retire [_param->_nb_rename_unit];
29
30	Tcontrol_t spr_write_val [_param->_nb_front_end][_param->_max_nb_context];
31	Tcontrol_t spr_write_sr_f_val [_param->_nb_front_end][_param->_max_nb_context];
32	Tcontrol_t spr_write_sr_f [_param->_nb_front_end][_param->_max_nb_context];
33	Tcontrol_t spr_write_sr_cy_val [_param->_nb_front_end][_param->_max_nb_context];
34	Tcontrol_t spr_write_sr_cy [_param->_nb_front_end][_param->_max_nb_context];
35	Tcontrol_t spr_write_sr_ov_val [_param->_nb_front_end][_param->_max_nb_context];
36	Tcontrol_t spr_write_sr_ov [_param->_nb_front_end][_param->_max_nb_context];
37
38	// Initialisation
39	for (uint32_t i=0; i<_param->_nb_bank; i++)
40	internal_BANK_RETIRE_VAL [i] = false;
41
42	for (uint32_t i=0; i<_param->_nb_rename_unit; i++)
43	{
44	num_inst_retire [i] = 0;
45	can_retire [i] = true ;
46	for (uint32_t j=0; j<_param->_nb_inst_retire[i]; j++)
47	retire_val [i][j] = false;
48	}
49	for (uint32_t i=0; i<_param->_nb_front_end; ++i)
50	for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
51	{
52	spr_write_val [i][j] = 0;
53	spr_write_sr_f_val [i][j] = 0;
54	spr_write_sr_cy_val [i][j] = 0;
55	spr_write_sr_ov_val [i][j] = 0;
56
57	}
58	// Scan Top of each bank
59	internal_BANK_RETIRE_HEAD = reg_NUM_BANK_HEAD;
60	for (uint32_t i=0; i<_param->_nb_bank; i++)
61	{
62	uint32_t num_bank = (internal_BANK_RETIRE_HEAD+i)%_param->_nb_bank;
63
64	if (not _rob[num_bank].empty())
65	{
66	// Scan all instruction in windows and test if instruction is speculative
67	entry_t * entry = _rob [num_bank].front();
68	uint32_t x = entry->rename_unit_id;
69	uint32_t y = num_inst_retire [x];
70
71	// test if :
72	// * can retire (all previous instruction is retired)
73	// * all structure is ok (not busy)
74	if (can_retire [x] and // in-order
75	(y < _param->_nb_inst_retire [x]) and
76	PORT_READ(in_RETIRE_ACK [x][y])) // not busy
77	{
78	rob_state_t state = entry->state;
79	if ((state == ROB_END_OK ) or
80	(state == ROB_END_KO ) or
81	(state == ROB_END_BRANCH_MISS) or
82	(state == ROB_END_LOAD_MISS ) or
83	(state == ROB_END_MISS )// or
84	// (state == ROB_END_EXCEPTION)
85	)
86	{
87	Tcontrol_t write_re = entry->write_re;
88	Tspecial_address_t num_reg_re_log = entry->num_reg_re_log;
89	Tcontext_t front_end_id = entry->front_end_id;
90	Tcontext_t context_id = entry->context_id;
91
92	// if state is ok, when write flags in the SR regsiters
93	bool spr_write_ack = true;
94
95	// Write in SR the good flag
96	if ((state == ROB_END_OK ) and write_re)
97	// ROB_END_BRANCH_MISS is a valid branch instruction but don't modify RE
98	{
99	spr_write_ack = PORT_READ(in_SPR_WRITE_ACK [front_end_id][context_id]);
100
101	// retire_ack is set !!!
102	spr_write_val [front_end_id][context_id] = 1;
103
104	Tspecial_data_t flags = entry->flags;
105
106	switch (num_reg_re_log)
107	{
108	case SPR_LOGIC_SR_F :
109	{
110	spr_write_sr_f_val [front_end_id][context_id] = 1;
111	spr_write_sr_f [front_end_id][context_id] = (flags & FLAG_F )!=0;
112
113	break;
114	}
115	case SPR_LOGIC_SR_CY_OV :
116	{
117	spr_write_sr_cy_val [front_end_id][context_id] = 1;
118	spr_write_sr_ov_val [front_end_id][context_id] = 1;
119	spr_write_sr_cy [front_end_id][context_id] = (flags & FLAG_CY)!=0;
120	spr_write_sr_ov [front_end_id][context_id] = (flags & FLAG_OV)!=0;
121
122	break;
123	}
124	default :
125	{
126	#ifdef DEBUG_TEST
127	throw ERRORMORPHEO(FUNCTION,_("Invalid num_reg_re_log.\n"));
128	#endif
129	}
130	}
131	}
132
133	// find an instruction can be retire, and in order
134
135	if (spr_write_ack)
136	{
137	retire_val [x][y] = 1;
138	num_inst_retire [x] ++;
139	internal_BANK_RETIRE_VAL [num_bank] = true;
140	}
141
142	internal_BANK_RETIRE_NUM_RENAME_UNIT [num_bank] = x;
143	internal_BANK_RETIRE_NUM_INST [num_bank] = y;
144
145	if (_param->_have_port_front_end_id)
146	PORT_WRITE(out_RETIRE_FRONT_END_ID [x][y], front_end_id );
147	if (_param->_have_port_context_id)
148	PORT_WRITE(out_RETIRE_CONTEXT_ID [x][y], context_id );
149	// PORT_WRITE(out_RETIRE_RENAME_UNIT_ID [x][y], entry->rename_unit_id );
150	PORT_WRITE(out_RETIRE_USE_STORE_QUEUE [x][y], entry->use_store_queue );
151	PORT_WRITE(out_RETIRE_USE_LOAD_QUEUE [x][y], entry->use_load_queue );
152	PORT_WRITE(out_RETIRE_STORE_QUEUE_PTR_WRITE [x][y], entry->store_queue_ptr_write);
153	if (_param->_have_port_load_queue_ptr)
154	PORT_WRITE(out_RETIRE_LOAD_QUEUE_PTR_WRITE [x][y], entry->load_queue_ptr_write );
155	// PORT_WRITE(out_RETIRE_READ_RA [x][y], entry->read_ra );
156	// PORT_WRITE(out_RETIRE_NUM_REG_RA_PHY [x][y], entry->num_reg_ra_phy );
157	// PORT_WRITE(out_RETIRE_READ_RB [x][y], entry->read_rb );
158	// PORT_WRITE(out_RETIRE_NUM_REG_RB_PHY [x][y], entry->num_reg_rb_phy );
159	// PORT_WRITE(out_RETIRE_READ_RC [x][y], entry->read_rc );
160	// PORT_WRITE(out_RETIRE_NUM_REG_RC_PHY [x][y], entry->num_reg_rc_phy );
161	PORT_WRITE(out_RETIRE_WRITE_RD [x][y], entry->write_rd );
162	PORT_WRITE(out_RETIRE_NUM_REG_RD_LOG [x][y], entry->num_reg_rd_log );
163	PORT_WRITE(out_RETIRE_NUM_REG_RD_PHY_OLD [x][y], entry->num_reg_rd_phy_old );
164	PORT_WRITE(out_RETIRE_NUM_REG_RD_PHY_NEW [x][y], entry->num_reg_rd_phy_new );
165	PORT_WRITE(out_RETIRE_WRITE_RE [x][y], write_re );
166	PORT_WRITE(out_RETIRE_NUM_REG_RE_LOG [x][y], num_reg_re_log );
167	PORT_WRITE(out_RETIRE_NUM_REG_RE_PHY_OLD [x][y], entry->num_reg_re_phy_old );
168	PORT_WRITE(out_RETIRE_NUM_REG_RE_PHY_NEW [x][y], entry->num_reg_re_phy_new );
169
170	// Event -> rob must be manage this event
171	if ((state == ROB_END_BRANCH_MISS) or
172	(state == ROB_END_LOAD_MISS))
173	can_retire [x] = false;
174	}
175	}
176
177	// Retire "in-order"
178	can_retire [x] &= retire_val [x][y];
179	}
180	}
181
182	for (uint32_t i=0; i<_param->_nb_rename_unit; i++)
183	for (uint32_t j=0; j<_param->_nb_inst_retire[i]; j++)
184	PORT_WRITE(out_RETIRE_VAL [i][j],retire_val [i][j]);
185
186	for (uint32_t i=0; i<_param->_nb_front_end; ++i)
187	for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
188	{
189	PORT_WRITE(out_SPR_WRITE_VAL [i][j], spr_write_val [i][j]);
190	PORT_WRITE(out_SPR_WRITE_SR_F_VAL [i][j], spr_write_sr_f_val [i][j]);
191	PORT_WRITE(out_SPR_WRITE_SR_F [i][j], spr_write_sr_f [i][j]);
192	PORT_WRITE(out_SPR_WRITE_SR_CY_VAL [i][j], spr_write_sr_cy_val [i][j]);
193	PORT_WRITE(out_SPR_WRITE_SR_CY [i][j], spr_write_sr_cy [i][j]);
194	PORT_WRITE(out_SPR_WRITE_SR_OV_VAL [i][j], spr_write_sr_ov_val [i][j]);
195	PORT_WRITE(out_SPR_WRITE_SR_OV [i][j], spr_write_sr_ov [i][j]);
196	}
197
198	log_end(Commit_unit,FUNCTION);
199	};
200
201	}; // end namespace commit_unit
202	}; // end namespace ooo_engine
203	}; // end namespace multi_ooo_engine
204	}; // end namespace core
205	}; // end namespace behavioural
206	}; // end namespace morpheo
207	#endif

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