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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp @ 88

Last change on this file since 88 was 88, checked in by rosiere, 16 years ago
Almost complete design with Test and test platform
Property svn:keywords set to `Id`
File size: 7.3 KB

Line
1	#ifdef SYSTEMC
2	/*
3	* $Id: Commit_unit_genMealy_retire.cpp 88 2008-12-10 18:31:39Z rosiere $
4	*
5	* [ Description ]
6	*
7	*/
8
9	#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_ooo_engine {
15	namespace ooo_engine {
16	namespace commit_unit {
17
18
19	#undef FUNCTION
20	#define FUNCTION "Commit_unit::genMealy_retire"
21	void Commit_unit::genMealy_retire (void)
22	{
23	log_begin(Commit_unit,FUNCTION);
24	log_function(Commit_unit,FUNCTION,_name.c_str());
25
26	Tcontrol_t retire_val [_param->_nb_rename_unit][_param->_max_nb_inst_retire];
27	uint32_t num_inst_retire [_param->_nb_rename_unit];
28	bool can_retire [_param->_nb_rename_unit];
29
30	Tcontrol_t spr_write_val [_param->_nb_front_end][_param->_max_nb_context];
31	Tcontrol_t spr_write_sr_f_val [_param->_nb_front_end][_param->_max_nb_context];
32	Tcontrol_t spr_write_sr_f [_param->_nb_front_end][_param->_max_nb_context];
33	Tcontrol_t spr_write_sr_cy_val [_param->_nb_front_end][_param->_max_nb_context];
34	Tcontrol_t spr_write_sr_cy [_param->_nb_front_end][_param->_max_nb_context];
35	Tcontrol_t spr_write_sr_ov_val [_param->_nb_front_end][_param->_max_nb_context];
36	Tcontrol_t spr_write_sr_ov [_param->_nb_front_end][_param->_max_nb_context];
37
38
39	// Initialisation
40	for (uint32_t i=0; i<_param->_nb_bank; i++)
41	internal_BANK_RETIRE_VAL [i] = false;
42
43	for (uint32_t i=0; i<_param->_nb_rename_unit; i++)
44	{
45	num_inst_retire [i] = 0;
46	can_retire [i] = true ;
47	for (uint32_t j=0; j<_param->_nb_inst_retire[i]; j++)
48	retire_val [i][j] = false;
49	}
50
51	for (uint32_t i=0; i<_param->_nb_front_end; ++i)
52	for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
53	spr_write_val [i][j] = 0;
54
55	// Scan Top of each bank
56	for (uint32_t i=0; i<_param->_nb_bank; i++)
57	{
58	uint32_t num_bank = (reg_NUM_BANK_HEAD+i)%_param->_nb_bank;
59
60	if (not _rob[num_bank].empty())
61	{
62	// Scan all instruction in windows and test if instruction is speculative
63	entry_t * entry = _rob [num_bank].front();
64	uint32_t x = entry->rename_unit_id;
65	uint32_t y = num_inst_retire [x];
66
67	if (can_retire [x] and // in-order
68	(y < _param->_nb_inst_retire [x]) and
69	PORT_READ(in_RETIRE_ACK [x][y])) // not busy
70	{
71	rob_state_t state = entry->state;
72
73	if ((state == ROB_END_OK ) or
74	(state == ROB_END_KO ) or
75	(state == ROB_END_MISS)// or
76	// (state == ROB_END_EXCEPTION)
77	)
78	{
79	Tcontext_t front_end_id = entry->front_end_id;
80	Tcontext_t context_id = entry->context_id;
81	Tcontrol_t write_re = entry->write_re;
82	Tspecial_address_t num_reg_re_log = entry->num_reg_re_log;
83
84	// if state is ok, when write flags in the SR regsiters
85	bool spr_write_ack = true;
86
87	if ((state == ROB_END_OK ) and write_re)
88	{
89	spr_write_ack = PORT_READ(in_SPR_WRITE_ACK [front_end_id][context_id]);
90
91	// retire_ack is set !!!
92	spr_write_val [front_end_id][context_id] = 1;
93
94	Tspecial_data_t flags = entry->flags;
95
96	switch (num_reg_re_log)
97	{
98	case SPR_LOGIC_SR_F :
99	{
100	spr_write_sr_f_val [front_end_id][context_id] = 1;
101	spr_write_sr_f [front_end_id][context_id] = (flags & FLAG_F )!=0;
102
103	break;
104	}
105	case SPR_LOGIC_SR_CY_OV :
106	{
107	spr_write_sr_cy_val [front_end_id][context_id] = 1;
108	spr_write_sr_ov_val [front_end_id][context_id] = 1;
109	spr_write_sr_cy [front_end_id][context_id] = (flags & FLAG_CY)!=0;
110	spr_write_sr_ov [front_end_id][context_id] = (flags & FLAG_OV)!=0;
111
112	break;
113	}
114	default :
115	{
116	#ifdef DEBUG_TEST
117	throw ERRORMORPHEO(FUNCTION,_("Invalid num_reg_re_log.\n"));
118	#endif
119	}
120	}
121	}
122
123	// find an instruction can be retire, and in order
124
125	if (spr_write_ack)
126	{
127	retire_val [x][y] = 1;
128	num_inst_retire [x] ++;
129	internal_BANK_RETIRE_VAL [num_bank] = true;
130	}
131
132	internal_BANK_RETIRE_NUM_RENAME_UNIT [num_bank] = x;
133	internal_BANK_RETIRE_NUM_INST [num_bank] = y;
134
135	if (_param->_have_port_front_end_id)
136	PORT_WRITE(out_RETIRE_FRONT_END_ID [x][y], front_end_id );
137	if (_param->_have_port_context_id)
138	PORT_WRITE(out_RETIRE_CONTEXT_ID [x][y], context_id );
139	// PORT_WRITE(out_RETIRE_RENAME_UNIT_ID [x][y], entry->rename_unit_id );
140	PORT_WRITE(out_RETIRE_EVENT_STATE [x][y], entry->event_state );
141	PORT_WRITE(out_RETIRE_USE_STORE_QUEUE [x][y], entry->use_store_queue );
142	PORT_WRITE(out_RETIRE_USE_LOAD_QUEUE [x][y], entry->use_load_queue );
143	PORT_WRITE(out_RETIRE_STORE_QUEUE_PTR_WRITE [x][y], entry->store_queue_ptr_write);
144	if (_param->_have_port_load_queue_ptr)
145	PORT_WRITE(out_RETIRE_LOAD_QUEUE_PTR_WRITE [x][y], entry->load_queue_ptr_write );
146	PORT_WRITE(out_RETIRE_READ_RA [x][y], entry->read_ra );
147	PORT_WRITE(out_RETIRE_NUM_REG_RA_PHY [x][y], entry->num_reg_ra_phy );
148	PORT_WRITE(out_RETIRE_READ_RB [x][y], entry->read_rb );
149	PORT_WRITE(out_RETIRE_NUM_REG_RB_PHY [x][y], entry->num_reg_rb_phy );
150	PORT_WRITE(out_RETIRE_READ_RC [x][y], entry->read_rc );
151	PORT_WRITE(out_RETIRE_NUM_REG_RC_PHY [x][y], entry->num_reg_rc_phy );
152	PORT_WRITE(out_RETIRE_WRITE_RD [x][y], entry->write_rd );
153	PORT_WRITE(out_RETIRE_NUM_REG_RD_LOG [x][y], entry->num_reg_rd_log );
154	PORT_WRITE(out_RETIRE_NUM_REG_RD_PHY_OLD [x][y], entry->num_reg_rd_phy_old );
155	PORT_WRITE(out_RETIRE_NUM_REG_RD_PHY_NEW [x][y], entry->num_reg_rd_phy_new );
156	PORT_WRITE(out_RETIRE_WRITE_RE [x][y], write_re );
157	PORT_WRITE(out_RETIRE_NUM_REG_RE_LOG [x][y], num_reg_re_log );
158	PORT_WRITE(out_RETIRE_NUM_REG_RE_PHY_OLD [x][y], entry->num_reg_re_phy_old );
159	PORT_WRITE(out_RETIRE_NUM_REG_RE_PHY_NEW [x][y], entry->num_reg_re_phy_new );
160	}
161	}
162
163	// Retire "in-order"
164	can_retire [x] &= retire_val [x][y];
165	}
166	}
167
168	for (uint32_t i=0; i<_param->_nb_rename_unit; i++)
169	for (uint32_t j=0; j<_param->_nb_inst_retire[i]; j++)
170	PORT_WRITE(out_RETIRE_VAL [i][j],retire_val [i][j]);
171
172	for (uint32_t i=0; i<_param->_nb_front_end; ++i)
173	for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
174	{
175	PORT_WRITE(out_SPR_WRITE_VAL [i][j], spr_write_val [i][j]);
176	PORT_WRITE(out_SPR_WRITE_SR_F_VAL [i][j], spr_write_sr_f_val [i][j]);
177	PORT_WRITE(out_SPR_WRITE_SR_F [i][j], spr_write_sr_f [i][j]);
178	PORT_WRITE(out_SPR_WRITE_SR_CY_VAL [i][j], spr_write_sr_cy_val [i][j]);
179	PORT_WRITE(out_SPR_WRITE_SR_CY [i][j], spr_write_sr_cy [i][j]);
180	PORT_WRITE(out_SPR_WRITE_SR_OV_VAL [i][j], spr_write_sr_ov_val [i][j]);
181	PORT_WRITE(out_SPR_WRITE_SR_OV [i][j], spr_write_sr_ov [i][j]);
182	}
183
184	log_end(Commit_unit,FUNCTION);
185	};
186
187	}; // end namespace commit_unit
188	}; // end namespace ooo_engine
189	}; // end namespace multi_ooo_engine
190	}; // end namespace core
191	}; // end namespace behavioural
192	}; // end namespace morpheo
193	#endif

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