[88] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id: Commit_unit_genMoore.cpp 105 2009-02-05 11:18:31Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_ooo_engine { |
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| 15 | namespace ooo_engine { |
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| 16 | namespace commit_unit { |
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| 17 | |
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| 18 | |
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| 19 | #undef FUNCTION |
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| 20 | #define FUNCTION "Commit_unit::genMoore" |
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| 21 | void Commit_unit::genMoore (void) |
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| 22 | { |
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| 23 | log_begin(Commit_unit,FUNCTION); |
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| 24 | log_function(Commit_unit,FUNCTION,_name.c_str()); |
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| 25 | |
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| 26 | // =================================================================== |
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| 27 | // =====[ REEXECUTE ]================================================= |
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| 28 | // =================================================================== |
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| 29 | { |
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[100] | 30 | // Store instruction comming Out Of Order in Load Store Unit. |
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| 31 | // Must be executed in no speculative mode. Also, send a signal when an Store is in head of ROB |
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| 32 | |
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[88] | 33 | Tcontrol_t val = false; |
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| 34 | |
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| 35 | if (not _rob[reg_NUM_BANK_HEAD].empty()) |
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| 36 | { |
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| 37 | entry_t * entry = _rob [reg_NUM_BANK_HEAD].front(); |
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| 38 | rob_state_t state = entry->state; |
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| 39 | |
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[100] | 40 | // Test state |
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[88] | 41 | val = ((state == ROB_STORE_HEAD_OK) or |
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| 42 | (state == ROB_STORE_HEAD_KO)); |
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| 43 | |
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| 44 | if (val) |
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| 45 | { |
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[100] | 46 | // Reexecute store |
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[88] | 47 | if (_param->_have_port_context_id) |
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| 48 | PORT_WRITE(out_REEXECUTE_CONTEXT_ID [0], entry->context_id ); |
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| 49 | if (_param->_have_port_front_end_id) |
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| 50 | PORT_WRITE(out_REEXECUTE_FRONT_END_ID [0], entry->front_end_id ); |
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| 51 | if (_param->_have_port_rob_ptr ) |
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| 52 | PORT_WRITE(out_REEXECUTE_PACKET_ID [0], entry->ptr ); |
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| 53 | PORT_WRITE(out_REEXECUTE_TYPE [0], entry->type ); |
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| 54 | PORT_WRITE(out_REEXECUTE_STORE_QUEUE_PTR_WRITE [0], entry->store_queue_ptr_write); |
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| 55 | PORT_WRITE(out_REEXECUTE_OPERATION [0], (state == ROB_STORE_HEAD_OK)?OPERATION_MEMORY_STORE_HEAD_OK:OPERATION_MEMORY_STORE_HEAD_KO); |
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| 56 | } |
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| 57 | } |
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| 58 | |
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| 59 | internal_REEXECUTE_VAL [0] = val; |
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| 60 | internal_REEXECUTE_NUM_BANK [0] = reg_NUM_BANK_HEAD; |
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| 61 | |
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| 62 | PORT_WRITE(out_REEXECUTE_VAL[0], internal_REEXECUTE_VAL [0]); |
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| 63 | } |
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| 64 | |
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| 65 | // =================================================================== |
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| 66 | // =====[ BRANCH_COMPLETE ]=========================================== |
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| 67 | // =================================================================== |
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| 68 | { |
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[100] | 69 | // Branchement must be send at the prediction unit |
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[88] | 70 | uint32_t nb_scan_bank = 0; |
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| 71 | |
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[100] | 72 | // for each port, find a valid branchement. |
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[88] | 73 | for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) |
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| 74 | { |
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| 75 | Tcontrol_t val = false; |
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| 76 | |
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| 77 | for (uint32_t j=nb_scan_bank; j<_param->_nb_bank; j++) |
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| 78 | { |
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| 79 | nb_scan_bank ++; |
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| 80 | |
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[100] | 81 | // translate bank number |
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[88] | 82 | uint32_t num_bank = (reg_NUM_BANK_HEAD+j)%_param->_nb_bank; |
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| 83 | |
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| 84 | if (not _rob [num_bank].empty()) |
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| 85 | { |
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| 86 | entry_t * entry = _rob [num_bank].front(); |
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| 87 | rob_state_t state = entry->state; |
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| 88 | |
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| 89 | if (state == ROB_BRANCH_COMPLETE) |
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| 90 | { |
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| 91 | val = true; |
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| 92 | |
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| 93 | internal_BRANCH_COMPLETE_NUM_BANK [i] = num_bank; |
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| 94 | |
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| 95 | if (_param->_have_port_context_id) |
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[98] | 96 | PORT_WRITE(out_BRANCH_COMPLETE_CONTEXT_ID [i], entry->context_id ); |
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[88] | 97 | if (_param->_have_port_front_end_id) |
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[98] | 98 | PORT_WRITE(out_BRANCH_COMPLETE_FRONT_END_ID [i], entry->front_end_id ); |
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[88] | 99 | if (_param->_have_port_depth) |
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[98] | 100 | PORT_WRITE(out_BRANCH_COMPLETE_DEPTH [i], entry->depth ); |
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[105] | 101 | PORT_WRITE(out_BRANCH_COMPLETE_ADDRESS [i], entry->address_next ); |
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[98] | 102 | // PORT_WRITE(out_BRANCH_COMPLETE_FLAG [i],(entry->flags&FLAG_F)!=0); |
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| 103 | PORT_WRITE(out_BRANCH_COMPLETE_NO_SEQUENCE [i], entry->no_sequence ); |
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[88] | 104 | |
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| 105 | break; |
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| 106 | } |
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| 107 | } |
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| 108 | } |
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| 109 | |
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| 110 | internal_BRANCH_COMPLETE_VAL [i] = val; |
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| 111 | PORT_WRITE(out_BRANCH_COMPLETE_VAL [i], internal_BRANCH_COMPLETE_VAL [i]); |
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| 112 | } |
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| 113 | } |
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| 114 | |
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| 115 | // =================================================================== |
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| 116 | // =====[ UPDATE ]==================================================== |
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| 117 | // =================================================================== |
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| 118 | { |
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[105] | 119 | internal_UPDATE_VAL = 0; |
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| 120 | internal_UPDATE_NUM_BANK = reg_NUM_BANK_HEAD; |
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[88] | 121 | |
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[105] | 122 | if (not _rob[internal_UPDATE_NUM_BANK].empty()) |
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[88] | 123 | { |
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[105] | 124 | log_printf(TRACE,Commit_unit,FUNCTION," * UPDATE"); |
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| 125 | log_printf(TRACE,Commit_unit,FUNCTION," * num_bank : %d",internal_UPDATE_NUM_BANK); |
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[88] | 126 | |
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[105] | 127 | entry_t * entry = _rob [internal_UPDATE_NUM_BANK].front(); |
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| 128 | |
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| 129 | switch (entry->state) |
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| 130 | { |
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| 131 | case ROB_END_EXCEPTION_UPDATE : |
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| 132 | { |
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| 133 | internal_UPDATE_VAL = 1; |
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| 134 | throw ERRORMORPHEO(FUNCTION,_("Moore : exception is not yet supported (Coming Soon).\n")); |
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| 135 | break; |
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| 136 | } |
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| 137 | case ROB_END_LOAD_MISS_UPDATE : |
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| 138 | { |
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| 139 | log_printf(TRACE,Commit_unit,FUNCTION," * ROB_END_LOAD_MISS_UPDATE"); |
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| 140 | |
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| 141 | internal_UPDATE_VAL = 1; |
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| 142 | |
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| 143 | Tcontext_t front_end_id = entry->front_end_id; |
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| 144 | Tcontext_t context_id = entry->context_id ; |
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| 145 | |
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| 146 | log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id); |
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| 147 | log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id ); |
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| 148 | |
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| 149 | if (_param->_have_port_front_end_id) |
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| 150 | PORT_WRITE(out_UPDATE_FRONT_END_ID ,front_end_id); |
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| 151 | if (_param->_have_port_context_id) |
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| 152 | PORT_WRITE(out_UPDATE_CONTEXT_ID ,context_id ); |
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| 153 | if (_param->_have_port_depth) |
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| 154 | PORT_WRITE(out_UPDATE_DEPTH ,entry->depth); |
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| 155 | PORT_WRITE(out_UPDATE_TYPE ,EVENT_TYPE_LOAD_MISS_SPECULATION); |
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| 156 | // PORT_WRITE(out_UPDATE_IS_DELAY_SLOT ,reg_PC_CURRENT_IS_DS [front_end_id][context_id]); |
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| 157 | // PORT_WRITE(out_UPDATE_ADDRESS ,reg_PC_CURRENT [front_end_id][context_id]); |
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| 158 | // PORT_WRITE(out_UPDATE_ADDRESS_EPCR_VAL,reg_PC_CURRENT_IS_DS_TAKE [front_end_id][context_id]); |
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| 159 | // PORT_WRITE(out_UPDATE_ADDRESS_EPCR ,reg_PC_NEXT [front_end_id][context_id]); |
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| 160 | // PORT_WRITE(out_UPDATE_ADDRESS_EEAR_VAL,0); |
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| 161 | // // PORT_WRITE(out_UPDATE_ADDRESS_EEAR ,); |
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| 162 | |
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| 163 | PORT_WRITE(out_UPDATE_IS_DELAY_SLOT ,0); |
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| 164 | PORT_WRITE(out_UPDATE_ADDRESS ,reg_PC_NEXT [front_end_id][context_id]); |
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| 165 | PORT_WRITE(out_UPDATE_ADDRESS_EPCR_VAL,0); |
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| 166 | // PORT_WRITE(out_UPDATE_ADDRESS_EPCR ,); |
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| 167 | PORT_WRITE(out_UPDATE_ADDRESS_EEAR_VAL,0); |
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| 168 | // PORT_WRITE(out_UPDATE_ADDRESS_EEAR ,); |
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| 169 | |
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| 170 | break; |
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| 171 | } |
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| 172 | default : |
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| 173 | { |
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| 174 | // internal_UPDATE_VAL = 0; |
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| 175 | } |
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| 176 | } |
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[88] | 177 | } |
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[105] | 178 | |
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| 179 | PORT_WRITE(out_UPDATE_VAL, internal_UPDATE_VAL); |
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| 180 | |
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| 181 | log_printf(TRACE,Commit_unit,FUNCTION," * UPDATE (end)"); |
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[88] | 182 | } |
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| 183 | |
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| 184 | // =================================================================== |
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| 185 | // =====[ NB_INST ]=================================================== |
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| 186 | // =================================================================== |
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| 187 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
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| 188 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
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| 189 | { |
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| 190 | PORT_WRITE(out_NB_INST_COMMIT_ALL [i][j], reg_NB_INST_COMMIT_ALL [i][j]); |
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| 191 | PORT_WRITE(out_NB_INST_COMMIT_MEM [i][j], reg_NB_INST_COMMIT_MEM [i][j]); |
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| 192 | } |
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| 193 | |
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[104] | 194 | // =================================================================== |
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| 195 | // =====[ RETIRE_EVENT ]============================================== |
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| 196 | // =================================================================== |
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| 197 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
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| 198 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
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| 199 | PORT_WRITE(out_RETIRE_EVENT_STATE [i][j], reg_EVENT_STATE[i][j]); |
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[88] | 200 | |
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| 201 | log_end(Commit_unit,FUNCTION); |
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| 202 | }; |
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| 203 | |
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| 204 | }; // end namespace commit_unit |
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| 205 | }; // end namespace ooo_engine |
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| 206 | }; // end namespace multi_ooo_engine |
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| 207 | }; // end namespace core |
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| 208 | }; // end namespace behavioural |
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| 209 | }; // end namespace morpheo |
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| 210 | #endif |
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