1 | #ifdef SYSTEMC |
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2 | /* |
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3 | * $Id: Commit_unit_transition.cpp 117 2009-05-16 14:42:39Z rosiere $ |
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4 | * |
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5 | * [ Description ] |
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6 | * |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h" |
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10 | #include "Behavioural/include/Simulation.h" |
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11 | |
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12 | namespace morpheo { |
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13 | namespace behavioural { |
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14 | namespace core { |
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15 | namespace multi_ooo_engine { |
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16 | namespace ooo_engine { |
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17 | namespace commit_unit { |
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18 | |
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19 | |
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20 | #undef FUNCTION |
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21 | #define FUNCTION "Commit_unit::transition" |
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22 | void Commit_unit::transition (void) |
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23 | { |
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24 | log_begin(Commit_unit,FUNCTION); |
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25 | log_function(Commit_unit,FUNCTION,_name.c_str()); |
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26 | |
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27 | if (PORT_READ(in_NRESET) == 0) |
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28 | { |
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29 | // Clear all bank |
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30 | for (uint32_t i=0; i<_param->_nb_bank; ++i) |
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31 | { |
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32 | while(not _rob[i].empty()) |
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33 | { |
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34 | delete _rob[i].front(); |
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35 | _rob[i].pop_front(); |
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36 | } |
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37 | reg_BANK_PTR [i] = 0; |
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38 | } |
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39 | |
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40 | // Reset pointer |
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41 | reg_NUM_BANK_HEAD = 0; |
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42 | reg_NUM_BANK_TAIL = 0; |
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43 | |
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44 | // Reset counter |
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45 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
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46 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
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47 | { |
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48 | _nb_cycle_idle [i][j] = 0; |
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49 | |
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50 | reg_NB_INST_COMMIT_ALL [i][j] = 0; |
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51 | reg_NB_INST_COMMIT_MEM [i][j] = 0; |
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52 | |
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53 | reg_EVENT_STATE [i][j] = EVENT_STATE_NO_EVENT; |
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54 | reg_EVENT_FLUSH [i][j] = false; |
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55 | reg_EVENT_STOP [i][j] = false; |
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56 | |
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57 | // reg_PC_PREVIOUS [i][j] = (0x100-4)>>2; |
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58 | reg_PC_CURRENT [i][j] = (0x100 )>>2; |
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59 | reg_PC_CURRENT_IS_DS [i][j] = 0; |
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60 | reg_PC_CURRENT_IS_DS_TAKE [i][j] = 0; |
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61 | reg_PC_NEXT [i][j] = (0x100+4)>>2; |
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62 | } |
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63 | |
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64 | // Reset priority algorithm |
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65 | _priority_insert->reset(); |
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66 | } |
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67 | else |
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68 | { |
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69 | // Increase number idle cycle |
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70 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
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71 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
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72 | _nb_cycle_idle [i][j] ++; |
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73 | |
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74 | // Compute next priority |
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75 | _priority_insert->transition(); |
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76 | |
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77 | // =================================================================== |
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78 | // =====[ GARBAGE COLLECTOR ]========================================= |
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79 | // =================================================================== |
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80 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
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81 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
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82 | switch (reg_EVENT_STATE [i][j]) |
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83 | { |
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84 | case EVENT_STATE_EVENT : |
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85 | { |
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86 | if (internal_RETIRE_EVENT_VAL [i][j] and in_RETIRE_EVENT_ACK [i][j]) |
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87 | reg_EVENT_STATE [i][j] = EVENT_STATE_WAITEND ; |
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88 | break; |
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89 | } |
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90 | case EVENT_STATE_WAITEND : |
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91 | { |
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92 | Tcounter_t nb_inst_all = PORT_READ(in_NB_INST_DECOD_ALL [i][j]) + reg_NB_INST_COMMIT_ALL [i][j]; |
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93 | if (nb_inst_all == 0) |
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94 | { |
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95 | reg_EVENT_STATE [i][j] = EVENT_STATE_END; |
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96 | reg_EVENT_FLUSH [i][j] = false; |
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97 | //reg_EVENT_STOP [i][j] = false; |
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98 | } |
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99 | break; |
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100 | } |
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101 | case EVENT_STATE_END : |
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102 | { |
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103 | reg_EVENT_STATE [i][j] = EVENT_STATE_NO_EVENT; |
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104 | break; |
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105 | } |
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106 | // case EVENT_STATE_NO_EVENT : |
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107 | default : break; |
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108 | } |
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109 | |
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110 | // =================================================================== |
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111 | // =====[ INSERT ]==================================================== |
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112 | // =================================================================== |
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113 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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114 | if (internal_BANK_INSERT_VAL [i]) |
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115 | { |
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116 | // get rename unit source and instruction. |
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117 | uint32_t x = internal_BANK_INSERT_NUM_RENAME_UNIT [i]; |
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118 | uint32_t y = internal_BANK_INSERT_NUM_INST [i]; |
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119 | |
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120 | if (PORT_READ(in_INSERT_VAL [x][y])) |
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121 | { |
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122 | log_printf(TRACE,Commit_unit,FUNCTION," * INSERT [%d][%d]",x,y); |
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123 | |
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124 | // get information |
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125 | Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_INSERT_FRONT_END_ID [x][y]):0; |
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126 | Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_INSERT_CONTEXT_ID [x][y]):0; |
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127 | Ttype_t type = PORT_READ(in_INSERT_TYPE [x][y]); |
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128 | Toperation_t operation = PORT_READ(in_INSERT_OPERATION [x][y]); |
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129 | bool is_store = is_operation_memory_store(operation); |
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130 | |
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131 | Texception_t exception = PORT_READ(in_INSERT_EXCEPTION [x][y]); |
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132 | Tcontrol_t no_execute = PORT_READ(in_INSERT_NO_EXECUTE [x][y]); |
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133 | |
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134 | log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id); |
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135 | log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id); |
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136 | log_printf(TRACE,Commit_unit,FUNCTION," * type : %s",toString(type).c_str()); |
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137 | log_printf(TRACE,Commit_unit,FUNCTION," * operation : %d",operation ); |
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138 | log_printf(TRACE,Commit_unit,FUNCTION," * exception : %d",exception ); |
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139 | |
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140 | // Create new entry. |
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141 | entry_t * entry = new entry_t; |
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142 | |
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143 | entry->ptr = reg_BANK_PTR [i]; |
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144 | entry->front_end_id = front_end_id; |
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145 | entry->context_id = context_id ; |
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146 | entry->rename_unit_id = x; |
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147 | entry->depth = (_param->_have_port_depth)?PORT_READ(in_INSERT_DEPTH [x][y]):0; |
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148 | entry->type = type; |
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149 | entry->operation = operation; |
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150 | entry->is_delay_slot = PORT_READ(in_INSERT_IS_DELAY_SLOT [x][y]); |
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151 | // entry->address = PORT_READ(in_INSERT_ADDRESS [x][y]); |
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152 | entry->exception = exception; |
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153 | entry->exception_use = PORT_READ(in_INSERT_EXCEPTION_USE [x][y]); |
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154 | entry->use_store_queue = (type == TYPE_MEMORY) and ( is_store) and (not no_execute); |
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155 | entry->use_load_queue = (type == TYPE_MEMORY) and (not is_store) and (not no_execute); |
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156 | entry->store_queue_ptr_write = PORT_READ(in_INSERT_STORE_QUEUE_PTR_WRITE [x][y]); |
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157 | entry->load_queue_ptr_write = (_param->_have_port_load_queue_ptr)?PORT_READ(in_INSERT_LOAD_QUEUE_PTR_WRITE [x][y]):0; |
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158 | entry->read_ra = PORT_READ(in_INSERT_READ_RA [x][y]); |
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159 | entry->num_reg_ra_log = PORT_READ(in_INSERT_NUM_REG_RA_LOG [x][y]); |
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160 | entry->num_reg_ra_phy = PORT_READ(in_INSERT_NUM_REG_RA_PHY [x][y]); |
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161 | entry->read_rb = PORT_READ(in_INSERT_READ_RB [x][y]); |
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162 | entry->num_reg_rb_log = PORT_READ(in_INSERT_NUM_REG_RB_LOG [x][y]); |
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163 | entry->num_reg_rb_phy = PORT_READ(in_INSERT_NUM_REG_RB_PHY [x][y]); |
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164 | entry->read_rc = PORT_READ(in_INSERT_READ_RC [x][y]); |
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165 | entry->num_reg_rc_log = PORT_READ(in_INSERT_NUM_REG_RC_LOG [x][y]); |
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166 | entry->num_reg_rc_phy = PORT_READ(in_INSERT_NUM_REG_RC_PHY [x][y]); |
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167 | entry->write_rd = PORT_READ(in_INSERT_WRITE_RD [x][y]); |
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168 | entry->num_reg_rd_log = PORT_READ(in_INSERT_NUM_REG_RD_LOG [x][y]); |
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169 | entry->num_reg_rd_phy_old = PORT_READ(in_INSERT_NUM_REG_RD_PHY_OLD [x][y]); |
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170 | entry->num_reg_rd_phy_new = PORT_READ(in_INSERT_NUM_REG_RD_PHY_NEW [x][y]); |
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171 | entry->write_re = PORT_READ(in_INSERT_WRITE_RE [x][y]); |
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172 | entry->num_reg_re_log = PORT_READ(in_INSERT_NUM_REG_RE_LOG [x][y]); |
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173 | entry->num_reg_re_phy_old = PORT_READ(in_INSERT_NUM_REG_RE_PHY_OLD [x][y]); |
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174 | entry->num_reg_re_phy_new = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [x][y]); |
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175 | entry->no_sequence = type == TYPE_BRANCH; |
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176 | entry->speculative = true; |
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177 | #ifdef DEBUG |
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178 | entry->address = PORT_READ(in_INSERT_ADDRESS [x][y]); |
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179 | #endif |
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180 | entry->address_next = PORT_READ(in_INSERT_ADDRESS_NEXT [x][y]); |
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181 | #ifdef DEBUG |
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182 | entry->cycle_rob_in = simulation_cycle(); |
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183 | entry->cycle_commit = simulation_cycle(); |
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184 | #endif |
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185 | |
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186 | // Test if exception : |
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187 | // * yes : no execute instruction, wait ROB Head |
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188 | // * no : test type |
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189 | // * BRANCH : l.j -> branch is ended |
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190 | // other -> wait the execution end of branchment |
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191 | // * MEMORY : store -> wait store is at head of ROB |
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192 | // other -> wait end of instruction |
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193 | // * OTHER |
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194 | |
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195 | // bool flush = reg_EVENT_FLUSH [front_end_id][context_id]; |
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196 | |
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197 | // log_printf(TRACE,Commit_unit,FUNCTION," * flush : %d",flush); |
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198 | |
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199 | // if (flush) |
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200 | // { |
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201 | // entry->state = ROB_END_MISS; // All type (branch, memory and others), because, is not execute |
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202 | // } |
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203 | // else |
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204 | { |
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205 | if (exception == EXCEPTION_NONE) |
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206 | { |
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207 | // no_execute : l.j, l.nop, l.rfe |
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208 | |
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209 | log_printf(TRACE,Commit_unit,FUNCTION," * no_execute : %d",no_execute); |
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210 | |
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211 | switch (type) |
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212 | { |
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213 | case TYPE_BRANCH : {entry->state=(no_execute==1)?ROB_BRANCH_COMPLETE:ROB_BRANCH_WAIT_END ; break;} |
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214 | case TYPE_MEMORY : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:(entry->state=(is_store ==1)?ROB_STORE_WAIT_HEAD_OK:ROB_OTHER_WAIT_END); break;} |
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215 | default : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:ROB_OTHER_WAIT_END; break;} |
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216 | } |
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217 | } |
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218 | else |
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219 | { |
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220 | // Have an exception : wait head of ROB |
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221 | |
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222 | // in_INSERT_NO_EXECUTE [x][y] : l.sys, l.trap |
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223 | |
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224 | entry->state = ROB_END_EXCEPTION_WAIT_HEAD; |
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225 | } |
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226 | } |
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227 | |
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228 | #ifdef STATISTICS |
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229 | if (usage_is_set(_usage,USE_STATISTICS)) |
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230 | (*_stat_nb_inst_insert [x]) ++; |
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231 | #endif |
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232 | |
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233 | // Push in rob |
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234 | _rob[i].push_back(entry); |
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235 | |
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236 | // Update counter and pointer |
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237 | reg_NB_INST_COMMIT_ALL [front_end_id][context_id] ++; |
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238 | if (type == TYPE_MEMORY) |
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239 | reg_NB_INST_COMMIT_MEM [front_end_id][context_id] ++; |
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240 | |
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241 | reg_NUM_BANK_TAIL = (reg_NUM_BANK_TAIL+1)%_param->_nb_bank; |
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242 | reg_BANK_PTR [i] = (reg_BANK_PTR [i]+1)%_param->_size_bank; |
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243 | } |
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244 | } |
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245 | |
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246 | // =================================================================== |
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247 | // =====[ COMMIT ]==================================================== |
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248 | // =================================================================== |
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249 | |
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250 | #ifdef STATISTICS |
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251 | if (usage_is_set(_usage,USE_STATISTICS)) |
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252 | (*_stat_nb_inst_commit_conflit_access) += internal_BANK_COMMIT_CONFLIT_ACCESS; |
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253 | #endif |
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254 | |
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255 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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256 | for (uint32_t j=0; j<_param->_nb_bank_access_commit; j++) |
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257 | if (internal_BANK_COMMIT_VAL [i][j]) |
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258 | { |
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259 | // An instruction is executed. Change state of this instruction |
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260 | |
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261 | uint32_t x = internal_BANK_COMMIT_NUM_INST [i][j]; |
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262 | |
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263 | if (PORT_READ(in_COMMIT_VAL [x]) and PORT_READ(in_COMMIT_WEN [x])) |
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264 | { |
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265 | log_printf(TRACE,Commit_unit,FUNCTION," * COMMIT [%d]",x); |
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266 | |
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267 | #ifdef STATISTICS |
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268 | if (usage_is_set(_usage,USE_STATISTICS)) |
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269 | (*_stat_nb_inst_commit) ++; |
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270 | #endif |
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271 | |
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272 | log_printf(TRACE,Commit_unit,FUNCTION," * num_bank : %d",i); |
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273 | |
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274 | // find the good entry !!! |
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275 | entry_t * entry = internal_BANK_COMMIT_ENTRY [i][j]; |
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276 | |
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277 | //Toperation_t operation = PORT_READ(in_COMMIT_OPERATION [x]); |
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278 | //Ttype_t type = PORT_READ(in_COMMIT_TYPE [x]); |
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279 | Texception_t exception = PORT_READ(in_COMMIT_EXCEPTION [x]); |
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280 | |
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281 | rob_state_t state = entry->state; |
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282 | Tcontext_t front_end_id = entry->front_end_id; |
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283 | Tcontext_t context_id = entry->context_id; |
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284 | |
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285 | // change state : test exception_use |
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286 | // * test if exception : exception and mask |
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287 | |
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288 | bool have_exception = false; |
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289 | bool have_miss_speculation = false; |
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290 | |
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291 | if (exception != EXCEPTION_NONE) |
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292 | { |
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293 | // Test if the instruction is a load and is a miss speculation (load is commit, but they have an dependence with a previous store) |
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294 | have_miss_speculation = (exception == EXCEPTION_MEMORY_MISS_SPECULATION); |
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295 | |
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296 | switch (entry->exception_use) |
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297 | { |
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298 | // Have overflow exception if bit overflow enable is set. |
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299 | case EXCEPTION_USE_RANGE : {have_exception = ((exception == EXCEPTION_RANGE) and PORT_READ(in_SPR_READ_SR_OVE[front_end_id][context_id])); break;} |
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300 | case EXCEPTION_USE_MEMORY_WITH_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or |
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301 | (exception == EXCEPTION_DATA_TLB ) or |
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302 | (exception == EXCEPTION_DATA_PAGE) or |
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303 | (exception == EXCEPTION_ALIGNMENT)); break;}; |
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304 | case EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or |
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305 | (exception == EXCEPTION_DATA_TLB ) or |
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306 | (exception == EXCEPTION_DATA_PAGE)); break;}; |
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307 | case EXCEPTION_USE_CUSTOM_0 : {have_exception = (exception == EXCEPTION_CUSTOM_0); break;}; |
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308 | case EXCEPTION_USE_CUSTOM_1 : {have_exception = (exception == EXCEPTION_CUSTOM_1); break;}; |
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309 | case EXCEPTION_USE_CUSTOM_2 : {have_exception = (exception == EXCEPTION_CUSTOM_2); break;}; |
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310 | case EXCEPTION_USE_CUSTOM_3 : {have_exception = (exception == EXCEPTION_CUSTOM_3); break;}; |
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311 | case EXCEPTION_USE_CUSTOM_4 : {have_exception = (exception == EXCEPTION_CUSTOM_4); break;}; |
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312 | case EXCEPTION_USE_CUSTOM_5 : {have_exception = (exception == EXCEPTION_CUSTOM_5); break;}; |
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313 | case EXCEPTION_USE_CUSTOM_6 : {have_exception = (exception == EXCEPTION_CUSTOM_6); break;}; |
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314 | // Case already manage (decod stage -> in insert in ROB) |
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315 | case EXCEPTION_USE_TRAP : {have_exception = false; exception = EXCEPTION_NONE; break;}; |
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316 | case EXCEPTION_USE_NONE : {have_exception = false; exception = EXCEPTION_NONE; break;}; |
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317 | case EXCEPTION_USE_ILLEGAL_INSTRUCTION : {have_exception = false; exception = EXCEPTION_NONE; break;}; |
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318 | case EXCEPTION_USE_SYSCALL : {have_exception = false; exception = EXCEPTION_NONE; break;}; |
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319 | default : |
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320 | { |
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321 | throw ERRORMORPHEO(FUNCTION,_("Commit : invalid exception_use.\n")); |
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322 | break; |
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323 | } |
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324 | } |
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325 | } |
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326 | |
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327 | switch (state) |
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328 | { |
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329 | // Branch ... |
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330 | case ROB_BRANCH_WAIT_END : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:ROB_BRANCH_COMPLETE; break;} |
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331 | // Store KO |
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332 | case ROB_EVENT_WAIT_END : {state = ROB_END_KO_SPECULATIVE; break;} |
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333 | // Store OK, Load and other instruction |
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334 | case ROB_OTHER_WAIT_END : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:((have_miss_speculation)?ROB_END_LOAD_MISS_SPECULATIVE:ROB_END_OK_SPECULATIVE); break;} |
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335 | default : |
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336 | { |
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337 | throw ERRORMORPHEO(FUNCTION,toString(_("Commit [%d] : Bank [%d][%d], invalid state value (%s).\n"),x,i,j,toString(state).c_str())); |
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338 | break; |
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339 | } |
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340 | } |
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341 | |
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342 | if ((have_exception or have_miss_speculation) and |
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343 | (reg_EVENT_FLUSH [entry->front_end_id][entry->context_id] == 0)) |
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344 | reg_EVENT_STOP [entry->front_end_id][entry->context_id] = true; |
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345 | |
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346 | // update Re Order Buffer |
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347 | entry->state = state; |
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348 | entry->exception = exception; |
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349 | entry->flags = PORT_READ(in_COMMIT_FLAGS [x]); |
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350 | entry->no_sequence = PORT_READ(in_COMMIT_NO_SEQUENCE [x]); |
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351 | // jalr, jr : address_dest is in register |
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352 | if ((entry->type == TYPE_BRANCH) and |
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353 | (entry->operation == OPERATION_BRANCH_L_JALR) and |
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354 | (entry->read_rb)) |
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355 | entry->address_next = PORT_READ(in_COMMIT_ADDRESS [x]); |
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356 | |
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357 | #ifdef DEBUG |
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358 | entry->cycle_commit = simulation_cycle(); |
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359 | #endif |
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360 | } |
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361 | } |
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362 | |
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363 | // =================================================================== |
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364 | // =====[ RETIRE ]==================================================== |
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365 | // =================================================================== |
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366 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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367 | { |
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368 | uint32_t num_bank = (internal_BANK_RETIRE_HEAD+i)%_param->_nb_bank; |
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369 | |
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370 | if (internal_BANK_RETIRE_VAL [num_bank]) |
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371 | { |
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372 | uint32_t x = internal_BANK_RETIRE_NUM_RENAME_UNIT [num_bank]; |
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373 | uint32_t y = internal_BANK_RETIRE_NUM_INST [num_bank]; |
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374 | |
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375 | log_printf(TRACE,Commit_unit,FUNCTION," * RETIRE [%d][%d]",x,y); |
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376 | log_printf(TRACE,Commit_unit,FUNCTION," * num_bank : %d",num_bank ); |
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377 | |
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378 | #ifdef DEBUG_TEST |
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379 | if (not PORT_READ(in_RETIRE_ACK [x][y])) |
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380 | throw ERRORMORPHEO(FUNCTION,_("Retire : retire_ack must be set.\n")); |
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381 | #endif |
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382 | |
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383 | entry_t * entry = _rob [num_bank].front(); |
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384 | rob_state_t state = entry->state; |
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385 | |
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386 | Tcontext_t front_end_id = entry->front_end_id; |
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387 | Tcontext_t context_id = entry->context_id ; |
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388 | uint32_t num_thread = _param->_translate_num_context_to_num_thread [front_end_id][context_id]; |
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389 | Ttype_t type = entry->type ; |
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390 | bool retire_ok = false; |
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391 | |
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392 | log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id ); |
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393 | log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id ); |
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394 | log_printf(TRACE,Commit_unit,FUNCTION," * rob_ptr : %d",((entry->ptr << _param->_shift_num_slot) | num_bank)); |
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395 | log_printf(TRACE,Commit_unit,FUNCTION," * num_thread : %d",num_thread ); |
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396 | log_printf(TRACE,Commit_unit,FUNCTION," * type : %s",toString(type).c_str()); |
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397 | log_printf(TRACE,Commit_unit,FUNCTION," * state : %s",toString(state).c_str()); |
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398 | |
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399 | if ((state == ROB_END_OK ) or |
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400 | // (state == ROB_END_KO ) or |
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401 | (state == ROB_END_BRANCH_MISS) or |
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402 | (state == ROB_END_LOAD_MISS )// or |
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403 | // (state == ROB_END_MISS ) or |
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404 | // (state == ROB_END_EXCEPTION ) |
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405 | ) |
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406 | { |
---|
407 | log_printf(TRACE,Commit_unit,FUNCTION," * retire_ok"); |
---|
408 | |
---|
409 | retire_ok = true; |
---|
410 | |
---|
411 | // reg_PC_PREVIOUS [front_end_id][context_id] = reg_PC_CURRENT [front_end_id][context_id]; |
---|
412 | reg_PC_CURRENT [front_end_id][context_id] = reg_PC_NEXT [front_end_id][context_id]; |
---|
413 | reg_PC_CURRENT_IS_DS [front_end_id][context_id] = entry->type == TYPE_BRANCH; |
---|
414 | reg_PC_CURRENT_IS_DS_TAKE [front_end_id][context_id] = entry->no_sequence; |
---|
415 | reg_PC_NEXT [front_end_id][context_id] = (entry->no_sequence)?(entry->address_next):(reg_PC_CURRENT [front_end_id][context_id]+1); |
---|
416 | |
---|
417 | // if (entry->address_next != reg_PC_NEXT [front_end_id][context_id]) |
---|
418 | // throw ERRORMORPHEO(FUNCTION,toString(_("Retire : Instruction's address_next (%.8x) is different of commit_unit's address_next (%.8x)"),entry->address_next,reg_PC_NEXT [front_end_id][context_id])); |
---|
419 | } |
---|
420 | |
---|
421 | if ((state == ROB_END_BRANCH_MISS) or |
---|
422 | (state == ROB_END_LOAD_MISS)) |
---|
423 | { |
---|
424 | reg_EVENT_STATE [front_end_id][context_id] = EVENT_STATE_EVENT; |
---|
425 | reg_EVENT_FLUSH [front_end_id][context_id] = true; |
---|
426 | reg_EVENT_STOP [front_end_id][context_id] = false; |
---|
427 | } |
---|
428 | |
---|
429 | #if defined(DEBUG) and defined(DEBUG_Commit_unit) and (DEBUG_Commit_unit == true) |
---|
430 | // log file |
---|
431 | instruction_log_file [num_thread] |
---|
432 | << "[" << simulation_cycle() << "] " |
---|
433 | << std::hex |
---|
434 | << (entry->address<<2) << " (" << (entry->address) << ") " |
---|
435 | << std::dec |
---|
436 | << "[" << entry->cycle_rob_in << ", " << entry->cycle_commit << "] " |
---|
437 | << "{" << ((retire_ok)?" OK ":"!KO!") << "} " |
---|
438 | << std::endl; |
---|
439 | #endif |
---|
440 | |
---|
441 | // Update nb_inst |
---|
442 | reg_NB_INST_COMMIT_ALL [front_end_id][context_id] --; |
---|
443 | if (type == TYPE_MEMORY) |
---|
444 | reg_NB_INST_COMMIT_MEM [front_end_id][context_id] --; |
---|
445 | |
---|
446 | reg_NUM_BANK_HEAD = (reg_NUM_BANK_HEAD+1)%_param->_nb_bank; |
---|
447 | |
---|
448 | delete entry; |
---|
449 | _rob [num_bank].pop_front(); |
---|
450 | |
---|
451 | // Transaction on retire interface : reset watch dog timer. |
---|
452 | _nb_cycle_idle [front_end_id][context_id] = 0; |
---|
453 | |
---|
454 | // Increase stop condition |
---|
455 | if (retire_ok) |
---|
456 | _simulation_nb_instruction_commited [num_thread] ++; |
---|
457 | |
---|
458 | #ifdef STATISTICS |
---|
459 | if (usage_is_set(_usage,USE_STATISTICS)) |
---|
460 | { |
---|
461 | (*_stat_nb_inst_retire [x]) ++; |
---|
462 | |
---|
463 | if (retire_ok) |
---|
464 | { |
---|
465 | (*_stat_nb_inst_retire_ok [num_thread]) ++; |
---|
466 | (*_stat_nb_inst_type [type] ) ++; |
---|
467 | } |
---|
468 | else |
---|
469 | (*_stat_nb_inst_retire_ko [num_thread]) ++; |
---|
470 | } |
---|
471 | #endif |
---|
472 | } |
---|
473 | } |
---|
474 | |
---|
475 | // =================================================================== |
---|
476 | // =====[ REEXECUTE ]================================================= |
---|
477 | // =================================================================== |
---|
478 | if (internal_REEXECUTE_VAL [0] and PORT_READ(in_REEXECUTE_ACK [0])) |
---|
479 | { |
---|
480 | log_printf(TRACE,Commit_unit,FUNCTION," * REEXECUTE [0]"); |
---|
481 | |
---|
482 | uint32_t num_bank = internal_REEXECUTE_NUM_BANK [0]; |
---|
483 | |
---|
484 | entry_t * entry = _rob [num_bank].front(); |
---|
485 | rob_state_t state = entry->state; |
---|
486 | |
---|
487 | switch (state) |
---|
488 | { |
---|
489 | case ROB_STORE_HEAD_OK : {state = ROB_OTHER_WAIT_END; break; } |
---|
490 | case ROB_STORE_HEAD_KO : {state = ROB_EVENT_WAIT_END; break; } |
---|
491 | default : {throw ERRORMORPHEO(FUNCTION,_("Reexecute : invalid state value.\n"));} |
---|
492 | } |
---|
493 | |
---|
494 | entry->state = state; |
---|
495 | } |
---|
496 | |
---|
497 | // =================================================================== |
---|
498 | // =====[ BRANCH_COMPLETE ]=========================================== |
---|
499 | // =================================================================== |
---|
500 | for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) |
---|
501 | if (internal_BRANCH_COMPLETE_VAL [i] and PORT_READ(in_BRANCH_COMPLETE_ACK [i])) |
---|
502 | { |
---|
503 | log_printf(TRACE,Commit_unit,FUNCTION," * BRANCH_COMPLETE [%d]",i); |
---|
504 | log_printf(TRACE,Commit_unit,FUNCTION," * miss_prediction : %d",PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i])); |
---|
505 | |
---|
506 | uint32_t num_bank = internal_BRANCH_COMPLETE_NUM_BANK [i]; |
---|
507 | |
---|
508 | entry_t * entry = _rob [num_bank].front(); |
---|
509 | |
---|
510 | #ifdef DEBUG_TEST |
---|
511 | rob_state_t state = entry->state; |
---|
512 | if (state != ROB_BRANCH_COMPLETE) |
---|
513 | throw ERRORMORPHEO(FUNCTION,_("Branch_complete : Invalid state value.\n")); |
---|
514 | #endif |
---|
515 | Tcontrol_t miss = PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]); |
---|
516 | |
---|
517 | entry->state = (miss)?ROB_END_BRANCH_MISS_SPECULATIVE:ROB_END_OK_SPECULATIVE; |
---|
518 | |
---|
519 | if (miss and (reg_EVENT_FLUSH [entry->front_end_id][entry->context_id] == 0)) |
---|
520 | reg_EVENT_STOP [entry->front_end_id][entry->context_id] = true; |
---|
521 | |
---|
522 | |
---|
523 | // entry->state = ROB_END_OK_SPECULATIVE; |
---|
524 | } |
---|
525 | |
---|
526 | // =================================================================== |
---|
527 | // =====[ UPDATE ]==================================================== |
---|
528 | // =================================================================== |
---|
529 | if (internal_UPDATE_VAL and PORT_READ(in_UPDATE_ACK)) |
---|
530 | { |
---|
531 | log_printf(TRACE,Commit_unit,FUNCTION," * UPDATE"); |
---|
532 | |
---|
533 | entry_t * entry = _rob [internal_UPDATE_NUM_BANK].front(); |
---|
534 | |
---|
535 | switch (entry->state) |
---|
536 | { |
---|
537 | // case ROB_END_EXCEPTION_UPDATE : |
---|
538 | // { |
---|
539 | // entry->state = ROB_END_KO; |
---|
540 | // throw ERRORMORPHEO(FUNCTION,_("Moore : exception is not yet supported (Coming Soon).\n")); |
---|
541 | // break; |
---|
542 | // } |
---|
543 | case ROB_END_LOAD_MISS_UPDATE : |
---|
544 | { |
---|
545 | log_printf(TRACE,Commit_unit,FUNCTION," * ROB_END_LOAD_MISS_UPDATE"); |
---|
546 | |
---|
547 | entry->state = ROB_END_LOAD_MISS; |
---|
548 | break; |
---|
549 | } |
---|
550 | default : |
---|
551 | { |
---|
552 | throw ERRORMORPHEO(FUNCTION,_("Update : invalid state.\n")); |
---|
553 | break; |
---|
554 | } |
---|
555 | } |
---|
556 | |
---|
557 | } |
---|
558 | |
---|
559 | // =================================================================== |
---|
560 | // =====[ EVENT ]===================================================== |
---|
561 | // =================================================================== |
---|
562 | // for (uint32_t i=0; i < _param->_nb_front_end; ++i) |
---|
563 | // for (uint32_t j=0; j < _param->_nb_context[i]; ++j) |
---|
564 | // if (PORT_READ(in_EVENT_VAL [i][j]) and internal_EVENT_ACK [i][j]) |
---|
565 | // { |
---|
566 | // log_printf(TRACE,Commit_unit,FUNCTION," * EVENT [%d][%d]",i,j); |
---|
567 | |
---|
568 | // reg_PC_CURRENT [i][j] = PORT_READ(in_EVENT_ADDRESS [i][j]); |
---|
569 | // reg_PC_CURRENT_IS_DS [i][j] = PORT_READ(in_EVENT_IS_DS_TAKE [i][j]); // ?? |
---|
570 | // reg_PC_CURRENT_IS_DS_TAKE [i][j] = PORT_READ(in_EVENT_IS_DS_TAKE [i][j]); |
---|
571 | // reg_PC_NEXT [i][j] = PORT_READ(in_EVENT_ADDRESS_NEXT [i][j]); |
---|
572 | // // PORT_READ(in_EVENT_ADDRESS_NEXT_VAL [i][j]); |
---|
573 | // } |
---|
574 | |
---|
575 | // =================================================================== |
---|
576 | // =====[ DEPTH - HEAD ]============================================== |
---|
577 | // =================================================================== |
---|
578 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
---|
579 | if (not _rob[i].empty()) |
---|
580 | { |
---|
581 | // Scan all instruction in windows and test if instruction is speculative |
---|
582 | entry_t * entry = _rob [i].front(); |
---|
583 | |
---|
584 | Tcontext_t front_end_id = entry->front_end_id; |
---|
585 | Tcontext_t context_id = entry->context_id ; |
---|
586 | rob_state_t state = entry->state; |
---|
587 | Tdepth_t depth = entry->depth; |
---|
588 | |
---|
589 | Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[front_end_id][context_id]):0; |
---|
590 | Tdepth_t depth_max = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[front_end_id][context_id]):0; |
---|
591 | Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL [front_end_id][context_id]); |
---|
592 | |
---|
593 | // is a valid instruction ? |
---|
594 | // If DEPTH_CURRENT : |
---|
595 | // equal at DEPTH_MIN -> not speculative |
---|
596 | // not include ]DEPTH_MIN:DEPTH_MAX] -> previous branch miss |
---|
597 | // include ]DEPTH_MIN:DEPTH_MAX] -> speculative |
---|
598 | |
---|
599 | // All case |
---|
600 | // ....... min ...X... max ....... OK |
---|
601 | // ....... min ....... max ...X... KO |
---|
602 | // ...X... min ....... max ....... KO |
---|
603 | // ....... max ....... min ...X... OK |
---|
604 | // ...X... max ....... min ....... OK |
---|
605 | // ....... max ...X... min ....... KO |
---|
606 | |
---|
607 | bool flush = reg_EVENT_FLUSH [front_end_id][context_id]; |
---|
608 | bool speculative = entry->speculative and not (depth == depth_min); |
---|
609 | Tcontrol_t is_valid = ((not speculative or |
---|
610 | (speculative and (depth_full or // all is valid |
---|
611 | ((depth_min <= depth_max)? // test if depth is overflow |
---|
612 | ((depth >= depth_min) and (depth <=depth_max)): |
---|
613 | ((depth >= depth_min) or (depth <=depth_max)))))) |
---|
614 | and not flush); |
---|
615 | |
---|
616 | // Tcontrol_t is_valid = ((depth == depth_min) and not flush); |
---|
617 | |
---|
618 | log_printf(TRACE,Commit_unit,FUNCTION," * HEAD [%d]",i); |
---|
619 | log_printf(TRACE,Commit_unit,FUNCTION," * is_valid : %d ((depth == depth_min) and not flush)",is_valid); |
---|
620 | log_printf(TRACE,Commit_unit,FUNCTION," * depth : %d",depth ); |
---|
621 | log_printf(TRACE,Commit_unit,FUNCTION," * depth_min : %d",depth_min); |
---|
622 | log_printf(TRACE,Commit_unit,FUNCTION," * depth_max : %d",depth_max); |
---|
623 | log_printf(TRACE,Commit_unit,FUNCTION," * depth_full : %d",depth_full); |
---|
624 | log_printf(TRACE,Commit_unit,FUNCTION," * flush : %d",flush); |
---|
625 | |
---|
626 | //------------------------------------------------------ |
---|
627 | // test if instruction is miss speculative |
---|
628 | //------------------------------------------------------ |
---|
629 | if (not is_valid) |
---|
630 | { |
---|
631 | switch (state) |
---|
632 | { |
---|
633 | case ROB_BRANCH_WAIT_END : {state = ROB_EVENT_WAIT_END; break;} |
---|
634 | case ROB_BRANCH_COMPLETE : {state = ROB_END_MISS ; break;} |
---|
635 | case ROB_END_BRANCH_MISS : |
---|
636 | case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;} |
---|
637 | case ROB_END_LOAD_MISS_UPDATE : |
---|
638 | case ROB_END_LOAD_MISS : |
---|
639 | case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;} |
---|
640 | case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_KO ; break;} |
---|
641 | //case ROB_STORE_WAIT_HEAD_KO : {state = ; break;} |
---|
642 | case ROB_OTHER_WAIT_END : {state = ROB_EVENT_WAIT_END; break;} |
---|
643 | case ROB_END_OK : |
---|
644 | case ROB_END_OK_SPECULATIVE : {state = ROB_END_MISS ; break;} |
---|
645 | case ROB_END_KO : |
---|
646 | case ROB_END_KO_SPECULATIVE : {state = ROB_END_MISS ; break;} |
---|
647 | case ROB_END_EXCEPTION_UPDATE : |
---|
648 | case ROB_END_EXCEPTION : |
---|
649 | case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_MISS ; break;} |
---|
650 | |
---|
651 | // don't change |
---|
652 | case ROB_STORE_HEAD_KO : {break;} |
---|
653 | case ROB_EVENT_WAIT_END : {break;} |
---|
654 | case ROB_END_MISS : {break;} |
---|
655 | |
---|
656 | // can't have miss speculation |
---|
657 | case ROB_STORE_HEAD_OK : |
---|
658 | default : |
---|
659 | { |
---|
660 | throw ERRORMORPHEO(FUNCTION,toString(_("Miss Speculation : Invalide state : %s.\n"),toString(state).c_str())); |
---|
661 | break; |
---|
662 | } |
---|
663 | } |
---|
664 | } |
---|
665 | |
---|
666 | //------------------------------------------------------ |
---|
667 | // test if instruction is not speculative |
---|
668 | //------------------------------------------------------ |
---|
669 | entry->speculative = speculative; |
---|
670 | // if (entry->depth == depth_min) |
---|
671 | if (not speculative) |
---|
672 | { |
---|
673 | switch (state) |
---|
674 | { |
---|
675 | case ROB_END_OK_SPECULATIVE : {state = ROB_END_OK ; break;} |
---|
676 | case ROB_END_KO_SPECULATIVE : {state = ROB_END_KO ; break;} |
---|
677 | case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_BRANCH_MISS ; break;} |
---|
678 | case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_LOAD_MISS_UPDATE ; break;} |
---|
679 | default : {break;} // else, no change |
---|
680 | } |
---|
681 | } |
---|
682 | |
---|
683 | //------------------------------------------------------ |
---|
684 | // test if instruction is store and head |
---|
685 | //------------------------------------------------------ |
---|
686 | if (i == reg_NUM_BANK_HEAD) |
---|
687 | { |
---|
688 | switch (state) |
---|
689 | { |
---|
690 | case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_OK; break;} |
---|
691 | case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_EXCEPTION_UPDATE; break;} |
---|
692 | default : {break;} // else, no change |
---|
693 | } |
---|
694 | } |
---|
695 | |
---|
696 | entry->state = state; |
---|
697 | } |
---|
698 | } |
---|
699 | |
---|
700 | // =================================================================== |
---|
701 | // =====[ OTHER ]===================================================== |
---|
702 | // =================================================================== |
---|
703 | |
---|
704 | #ifdef STATISTICS |
---|
705 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
---|
706 | if (usage_is_set(_usage,USE_STATISTICS)) |
---|
707 | *(_stat_bank_nb_inst [i]) += _rob[i].size(); |
---|
708 | #endif |
---|
709 | |
---|
710 | #if (DEBUG >= DEBUG_TRACE) and (DEBUG_Commit_unit == true) |
---|
711 | { |
---|
712 | log_printf(TRACE,Commit_unit,FUNCTION," * Dump ROB (Re-Order-Buffer)"); |
---|
713 | log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_head : %d",reg_NUM_BANK_HEAD); |
---|
714 | log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_tail : %d",reg_NUM_BANK_TAIL); |
---|
715 | |
---|
716 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
---|
717 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
---|
718 | { |
---|
719 | log_printf(TRACE,Commit_unit,FUNCTION," * [%d][%d] - %d",i,j,_param->_translate_num_context_to_num_thread [i][j]); |
---|
720 | log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_STATE : %s",toString(reg_EVENT_STATE [i][j]).c_str()); |
---|
721 | log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_FLUSH : %d",reg_EVENT_FLUSH [i][j]); |
---|
722 | log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_STOP : %d",reg_EVENT_STOP [i][j]); |
---|
723 | log_printf(TRACE,Commit_unit,FUNCTION," * NB_INST_ALL : %d",reg_NB_INST_COMMIT_ALL[i][j]); |
---|
724 | log_printf(TRACE,Commit_unit,FUNCTION," * NB_INST_MEM : %d",reg_NB_INST_COMMIT_MEM[i][j]); |
---|
725 | log_printf(TRACE,Commit_unit,FUNCTION," * PC_CURRENT : %.8x (%.8x) - %d %d",reg_PC_CURRENT [i][j],reg_PC_CURRENT [i][j]<<2, reg_PC_CURRENT_IS_DS [i][j], reg_PC_CURRENT_IS_DS_TAKE [i][j]); |
---|
726 | log_printf(TRACE,Commit_unit,FUNCTION," * PC_NEXT : %.8x (%.8x)",reg_PC_NEXT [i][j],reg_PC_NEXT [i][j]<<2); |
---|
727 | } |
---|
728 | |
---|
729 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
---|
730 | { |
---|
731 | uint32_t num_bank = (reg_NUM_BANK_HEAD+i)%_param->_nb_bank; |
---|
732 | |
---|
733 | log_printf(TRACE,Commit_unit,FUNCTION," * Bank [%d] size : %d, ptr : %d",num_bank,(int)_rob[num_bank].size(), reg_BANK_PTR [i]); |
---|
734 | |
---|
735 | for (std::list<entry_t*>::iterator it=_rob[num_bank].begin(); |
---|
736 | it!=_rob[num_bank].end(); |
---|
737 | it++) |
---|
738 | { |
---|
739 | log_printf(TRACE,Commit_unit,FUNCTION," [%.4d][%.4d] (%.4d) %.4d %.4d %.4d %.4d, %.3d %.3d, %.1d, %.1d %.4d, %.1d %.4d, %s", |
---|
740 | num_bank , |
---|
741 | (*it)->ptr , |
---|
742 | (((*it)->ptr << _param->_shift_num_slot) | num_bank), |
---|
743 | (*it)->front_end_id , |
---|
744 | (*it)->context_id , |
---|
745 | (*it)->rename_unit_id , |
---|
746 | (*it)->depth , |
---|
747 | (*it)->type , |
---|
748 | (*it)->operation , |
---|
749 | (*it)->is_delay_slot , |
---|
750 | (*it)->use_store_queue , |
---|
751 | (*it)->store_queue_ptr_write , |
---|
752 | (*it)->use_load_queue , |
---|
753 | (*it)->load_queue_ptr_write , |
---|
754 | toString((*it)->state).c_str() ); |
---|
755 | log_printf(TRACE,Commit_unit,FUNCTION," %.1d %.2d %.6d, %.1d %.2d %.6d, %.1d %.1d %.6d, %.1d %.2d %.6d %.6d, %.1d %.1d %.6d %.6d ", |
---|
756 | (*it)->read_ra , |
---|
757 | (*it)->num_reg_ra_log , |
---|
758 | (*it)->num_reg_ra_phy , |
---|
759 | (*it)->read_rb , |
---|
760 | (*it)->num_reg_rb_log , |
---|
761 | (*it)->num_reg_rb_phy , |
---|
762 | (*it)->read_rc , |
---|
763 | (*it)->num_reg_rc_log , |
---|
764 | (*it)->num_reg_rc_phy , |
---|
765 | (*it)->write_rd , |
---|
766 | (*it)->num_reg_rd_log , |
---|
767 | (*it)->num_reg_rd_phy_old , |
---|
768 | (*it)->num_reg_rd_phy_new , |
---|
769 | (*it)->write_re , |
---|
770 | (*it)->num_reg_re_log , |
---|
771 | (*it)->num_reg_re_phy_old , |
---|
772 | (*it)->num_reg_re_phy_new ); |
---|
773 | |
---|
774 | log_printf(TRACE,Commit_unit,FUNCTION," %.2d %.2d %.1d %.1d %.1d - %.8x (%.8x) %.8x (%.8x)", |
---|
775 | (*it)->exception_use , |
---|
776 | (*it)->exception , |
---|
777 | (*it)->flags , |
---|
778 | (*it)->no_sequence , |
---|
779 | (*it)->speculative , |
---|
780 | (*it)->address , |
---|
781 | (*it)->address<<2 , |
---|
782 | (*it)->address_next , |
---|
783 | (*it)->address_next<<2 |
---|
784 | ); |
---|
785 | } |
---|
786 | } |
---|
787 | } |
---|
788 | #endif |
---|
789 | |
---|
790 | #ifdef DEBUG_TEST |
---|
791 | { |
---|
792 | uint32_t x=reg_NUM_BANK_HEAD; |
---|
793 | if (not _rob[x].empty()) |
---|
794 | { |
---|
795 | entry_t * entry = _rob [x].front(); |
---|
796 | |
---|
797 | if (false |
---|
798 | // or (entry->state == ROB_EMPTY ) |
---|
799 | // or (entry->state == ROB_BRANCH_WAIT_END ) |
---|
800 | // or (entry->state == ROB_BRANCH_COMPLETE ) |
---|
801 | // or (entry->state == ROB_STORE_WAIT_HEAD_OK ) |
---|
802 | // //or (entry->state == ROB_STORE_WAIT_HEAD_KO ) |
---|
803 | // or (entry->state == ROB_STORE_HEAD_OK ) |
---|
804 | // or (entry->state == ROB_STORE_HEAD_KO ) |
---|
805 | // or (entry->state == ROB_OTHER_WAIT_END ) |
---|
806 | // or (entry->state == ROB_EVENT_WAIT_END ) |
---|
807 | // or (entry->state == ROB_END_OK_SPECULATIVE ) |
---|
808 | or (entry->state == ROB_END_OK ) |
---|
809 | // or (entry->state == ROB_END_KO_SPECULATIVE ) |
---|
810 | // or (entry->state == ROB_END_KO ) |
---|
811 | // or (entry->state == ROB_END_BRANCH_MISS_SPECULATIVE) |
---|
812 | or (entry->state == ROB_END_BRANCH_MISS ) |
---|
813 | // or (entry->state == ROB_END_LOAD_MISS_SPECULATIVE ) |
---|
814 | // or (entry->state == ROB_END_LOAD_MISS_UPDATE ) |
---|
815 | or (entry->state == ROB_END_LOAD_MISS ) |
---|
816 | // or (entry->state == ROB_END_MISS ) |
---|
817 | // or (entry->state == ROB_END_EXCEPTION_WAIT_HEAD ) |
---|
818 | // or (entry->state == ROB_END_EXCEPTION_UPDATE ) |
---|
819 | // or (entry->state == ROB_END_EXCEPTION ) |
---|
820 | ) |
---|
821 | if (entry->address != reg_PC_CURRENT[entry->front_end_id][entry->context_id]) |
---|
822 | throw ERRORMORPHEO(FUNCTION,toString(_("Rob top address (%x) is different of reg_PC_CURRENT[%d][%d] (%x).\n"), |
---|
823 | entry->address, |
---|
824 | entry->front_end_id, |
---|
825 | entry->context_id, |
---|
826 | reg_PC_CURRENT[entry->front_end_id][entry->context_id])); |
---|
827 | } |
---|
828 | } |
---|
829 | #endif |
---|
830 | |
---|
831 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
---|
832 | end_cycle (); |
---|
833 | #endif |
---|
834 | |
---|
835 | // Stop Condition |
---|
836 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
---|
837 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
---|
838 | if (_nb_cycle_idle [i][j] >= debug_idle_cycle) |
---|
839 | throw ERRORMORPHEO(FUNCTION,toString(_("Thread [%d] is idle since %.0f cycles.\n"),_param->_translate_num_context_to_num_thread[i][j],_nb_cycle_idle [i][j])); |
---|
840 | |
---|
841 | log_end(Commit_unit,FUNCTION); |
---|
842 | }; |
---|
843 | |
---|
844 | }; // end namespace commit_unit |
---|
845 | }; // end namespace ooo_engine |
---|
846 | }; // end namespace multi_ooo_engine |
---|
847 | }; // end namespace core |
---|
848 | |
---|
849 | }; // end namespace behavioural |
---|
850 | }; // end namespace morpheo |
---|
851 | #endif |
---|