1 | #ifdef SYSTEMC |
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2 | /* |
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3 | * $Id: Commit_unit_transition.cpp 88 2008-12-10 18:31:39Z rosiere $ |
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4 | * |
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5 | * [ Description ] |
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6 | * |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | namespace core { |
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14 | namespace multi_ooo_engine { |
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15 | namespace ooo_engine { |
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16 | namespace commit_unit { |
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17 | |
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18 | |
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19 | #undef FUNCTION |
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20 | #define FUNCTION "Commit_unit::transition" |
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21 | void Commit_unit::transition (void) |
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22 | { |
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23 | log_begin(Commit_unit,FUNCTION); |
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24 | log_function(Commit_unit,FUNCTION,_name.c_str()); |
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25 | |
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26 | if (PORT_READ(in_NRESET) == 0) |
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27 | { |
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28 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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29 | { |
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30 | _rob [i].clear(); |
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31 | reg_BANK_PTR [i] = 0; |
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32 | } |
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33 | |
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34 | reg_NUM_BANK_HEAD = 0; |
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35 | reg_NUM_BANK_TAIL = 0; |
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36 | |
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37 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
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38 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
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39 | { |
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40 | reg_NB_INST_COMMIT_ALL [i][j] = 0; |
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41 | reg_NB_INST_COMMIT_MEM [i][j] = 0; |
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42 | } |
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43 | |
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44 | _priority_insert->reset(); |
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45 | } |
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46 | else |
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47 | { |
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48 | // next priority |
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49 | _priority_insert->transition(); |
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50 | |
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51 | // =================================================================== |
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52 | // =====[ INSERT ]==================================================== |
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53 | // =================================================================== |
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54 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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55 | if (internal_BANK_INSERT_VAL [i]) |
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56 | { |
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57 | uint32_t x = internal_BANK_INSERT_NUM_RENAME_UNIT [i]; |
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58 | uint32_t y = internal_BANK_INSERT_NUM_INST [i]; |
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59 | |
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60 | if (PORT_READ(in_INSERT_VAL [x][y])) |
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61 | { |
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62 | log_printf(TRACE,Commit_unit,FUNCTION," * INSERT [%d][%d]",x,y); |
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63 | |
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64 | #ifdef STATISTICS |
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65 | if (usage_is_set(_usage,USE_STATISTICS)) |
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66 | (*_stat_nb_inst_insert [x]) ++; |
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67 | #endif |
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68 | |
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69 | Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_INSERT_FRONT_END_ID [x][y]):0; |
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70 | Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_INSERT_CONTEXT_ID [x][y]):0; |
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71 | Ttype_t type = PORT_READ(in_INSERT_TYPE [x][y]); |
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72 | Toperation_t operation = PORT_READ(in_INSERT_OPERATION [x][y]); |
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73 | Texception_t exception = PORT_READ(in_INSERT_EXCEPTION [x][y]); |
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74 | |
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75 | log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id); |
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76 | log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id); |
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77 | log_printf(TRACE,Commit_unit,FUNCTION," * type : %s",toString_type(type).c_str()); |
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78 | log_printf(TRACE,Commit_unit,FUNCTION," * operation : %d",operation ); |
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79 | log_printf(TRACE,Commit_unit,FUNCTION," * exception : %d",exception ); |
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80 | |
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81 | entry_t * entry = new entry_t; |
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82 | |
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83 | entry->ptr = reg_BANK_PTR [i]; |
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84 | entry->front_end_id = front_end_id; |
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85 | entry->context_id = context_id ; |
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86 | entry->rename_unit_id = x; |
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87 | entry->depth = (_param->_have_port_depth)?PORT_READ(in_INSERT_DEPTH [x][y]):0; |
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88 | entry->type = type; |
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89 | entry->operation = operation; |
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90 | entry->is_delay_slot = PORT_READ(in_INSERT_IS_DELAY_SLOT [x][y]); |
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91 | entry->address = PORT_READ(in_INSERT_ADDRESS [x][y]); |
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92 | entry->exception = exception; |
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93 | entry->exception_use = PORT_READ(in_INSERT_EXCEPTION_USE [x][y]); |
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94 | entry->use_store_queue = (type == TYPE_MEMORY) and ( is_operation_memory_store(operation)); |
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95 | entry->use_load_queue = (type == TYPE_MEMORY) and (not is_operation_memory_store(operation)); |
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96 | entry->store_queue_ptr_write = PORT_READ(in_INSERT_STORE_QUEUE_PTR_WRITE [x][y]); |
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97 | entry->load_queue_ptr_write = (_param->_have_port_load_queue_ptr)?PORT_READ(in_INSERT_LOAD_QUEUE_PTR_WRITE [x][y]):0; |
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98 | entry->read_ra = PORT_READ(in_INSERT_READ_RA [x][y]); |
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99 | entry->num_reg_ra_log = PORT_READ(in_INSERT_NUM_REG_RA_LOG [x][y]); |
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100 | entry->num_reg_ra_phy = PORT_READ(in_INSERT_NUM_REG_RA_PHY [x][y]); |
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101 | entry->read_rb = PORT_READ(in_INSERT_READ_RB [x][y]); |
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102 | entry->num_reg_rb_log = PORT_READ(in_INSERT_NUM_REG_RB_LOG [x][y]); |
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103 | entry->num_reg_rb_phy = PORT_READ(in_INSERT_NUM_REG_RB_PHY [x][y]); |
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104 | entry->read_rc = PORT_READ(in_INSERT_READ_RC [x][y]); |
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105 | entry->num_reg_rc_log = PORT_READ(in_INSERT_NUM_REG_RC_LOG [x][y]); |
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106 | entry->num_reg_rc_phy = PORT_READ(in_INSERT_NUM_REG_RC_PHY [x][y]); |
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107 | entry->write_rd = PORT_READ(in_INSERT_WRITE_RD [x][y]); |
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108 | entry->num_reg_rd_log = PORT_READ(in_INSERT_NUM_REG_RD_LOG [x][y]); |
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109 | entry->num_reg_rd_phy_old = PORT_READ(in_INSERT_NUM_REG_RD_PHY_OLD [x][y]); |
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110 | entry->num_reg_rd_phy_new = PORT_READ(in_INSERT_NUM_REG_RD_PHY_NEW [x][y]); |
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111 | entry->write_re = PORT_READ(in_INSERT_WRITE_RE [x][y]); |
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112 | entry->num_reg_re_log = PORT_READ(in_INSERT_NUM_REG_RE_LOG [x][y]); |
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113 | entry->num_reg_re_phy_old = PORT_READ(in_INSERT_NUM_REG_RE_PHY_OLD [x][y]); |
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114 | entry->num_reg_re_phy_new = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [x][y]); |
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115 | |
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116 | if (exception == EXCEPTION_NONE) |
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117 | { |
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118 | Tcontrol_t no_execute = PORT_READ(in_INSERT_NO_EXECUTE [x][y]); |
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119 | // no_execute : l.j, l.nop, l.rfe |
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120 | |
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121 | log_printf(TRACE,Commit_unit,FUNCTION," * no_execute : %d",no_execute); |
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122 | |
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123 | switch (type) |
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124 | { |
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125 | case TYPE_BRANCH : {entry->state=(no_execute==1)?ROB_BRANCH_COMPLETE:ROB_BRANCH_WAIT_END; break;} |
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126 | case TYPE_MEMORY : {entry->state=ROB_STORE_WAIT_HEAD_OK; break;} |
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127 | default : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:ROB_OTHER_WAIT_END; break;} |
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128 | } |
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129 | } |
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130 | else |
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131 | { |
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132 | // in_INSERT_NO_EXECUTE [x][y] : l.sys, l.trap |
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133 | |
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134 | entry->state = ROB_END_EXCEPTION_WAIT_HEAD; |
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135 | } |
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136 | |
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137 | _rob[i].push_back(entry); |
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138 | |
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139 | // Update nb_inst |
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140 | reg_NB_INST_COMMIT_ALL [front_end_id][context_id] ++; |
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141 | if (type == TYPE_MEMORY) |
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142 | reg_NB_INST_COMMIT_MEM [front_end_id][context_id] ++; |
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143 | |
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144 | reg_NUM_BANK_TAIL = (reg_NUM_BANK_TAIL+1)%_param->_nb_bank; |
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145 | reg_BANK_PTR [i] = (reg_BANK_PTR [i]+1)%_param->_size_bank; |
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146 | } |
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147 | } |
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148 | |
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149 | // =================================================================== |
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150 | // =====[ COMMIT ]==================================================== |
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151 | // =================================================================== |
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152 | |
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153 | #ifdef STATISTICS |
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154 | if (usage_is_set(_usage,USE_STATISTICS)) |
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155 | (*_stat_nb_inst_commit_conflit_access) += internal_BANK_COMMIT_CONFLIT_ACCESS; |
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156 | #endif |
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157 | |
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158 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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159 | for (uint32_t j=0; j<_param->_nb_bank_access_commit; j++) |
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160 | if (internal_BANK_COMMIT_VAL [i][j]) |
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161 | { |
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162 | uint32_t x = internal_BANK_COMMIT_NUM_INST [i][j]; |
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163 | |
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164 | if (PORT_READ(in_COMMIT_VAL [x]) and PORT_READ(in_COMMIT_WEN [x])) |
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165 | { |
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166 | log_printf(TRACE,Commit_unit,FUNCTION," * COMMIT [%d]",x); |
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167 | |
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168 | #ifdef STATISTICS |
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169 | if (usage_is_set(_usage,USE_STATISTICS)) |
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170 | (*_stat_nb_inst_commit) ++; |
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171 | #endif |
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172 | |
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173 | // Tpacket_t packet_id = (_param->_have_port_rob_ptr )?(PORT_READ(in_COMMIT_PACKET_ID [x])&_param->_mask_size_bank):0; |
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174 | |
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175 | log_printf(TRACE,Commit_unit,FUNCTION," * num_bank : %d",i); |
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176 | // log_printf(TRACE,Commit_unit,FUNCTION," * packet_id : %d",(_param->_have_port_rob_ptr )?(PORT_READ(in_COMMIT_PACKET_ID [x])):0); |
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177 | // log_printf(TRACE,Commit_unit,FUNCTION," * num_entry : %d",packet_id); |
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178 | |
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179 | // test pandex with ptr_write. |
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180 | // Tpacket_t index = (packet_id<reg_BANK_PTR [i])?(reg_BANK_PTR [i]-packet_id):(_param->_size_bank+reg_BANK_PTR [i]-packet_id); |
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181 | |
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182 | // find the good entry !!! |
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183 | entry_t * entry = internal_BANK_COMMIT_ENTRY [i][j]; |
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184 | |
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185 | //Toperation_t operation = PORT_READ(in_COMMIT_OPERATION [x]); |
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186 | //Ttype_t type = PORT_READ(in_COMMIT_TYPE [x]); |
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187 | Texception_t exception = PORT_READ(in_COMMIT_EXCEPTION [x]); |
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188 | |
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189 | rob_state_t state = entry->state; |
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190 | Tcontext_t front_end_id = entry->front_end_id; |
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191 | Tcontext_t context_id = entry->context_id; |
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192 | |
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193 | // change state |
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194 | // * test if exception : exception and mask |
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195 | |
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196 | bool have_exception = false; |
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197 | |
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198 | if (exception != EXCEPTION_NONE) |
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199 | switch (entry->exception_use) |
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200 | { |
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201 | case EXCEPTION_USE_RANGE : {have_exception = ((exception == EXCEPTION_RANGE) and PORT_READ(in_SPR_READ_SR_OVE[front_end_id][context_id])); break;} |
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202 | case EXCEPTION_USE_MEMORY_WITH_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or |
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203 | (exception == EXCEPTION_DATA_TLB ) or |
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204 | (exception == EXCEPTION_DATA_PAGE) or |
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205 | (exception == EXCEPTION_ALIGNMENT)); break;}; |
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206 | case EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or |
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207 | (exception == EXCEPTION_DATA_TLB ) or |
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208 | (exception == EXCEPTION_DATA_PAGE)); break;}; |
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209 | case EXCEPTION_USE_CUSTOM_0 : {have_exception = (exception == EXCEPTION_CUSTOM_0); break;}; |
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210 | case EXCEPTION_USE_CUSTOM_1 : {have_exception = (exception == EXCEPTION_CUSTOM_1); break;}; |
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211 | case EXCEPTION_USE_CUSTOM_2 : {have_exception = (exception == EXCEPTION_CUSTOM_2); break;}; |
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212 | case EXCEPTION_USE_CUSTOM_3 : {have_exception = (exception == EXCEPTION_CUSTOM_3); break;}; |
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213 | case EXCEPTION_USE_CUSTOM_4 : {have_exception = (exception == EXCEPTION_CUSTOM_4); break;}; |
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214 | case EXCEPTION_USE_CUSTOM_5 : {have_exception = (exception == EXCEPTION_CUSTOM_5); break;}; |
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215 | case EXCEPTION_USE_CUSTOM_6 : {have_exception = (exception == EXCEPTION_CUSTOM_6); break;}; |
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216 | case EXCEPTION_USE_TRAP : {have_exception = false; break;}; |
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217 | case EXCEPTION_USE_NONE : {have_exception = false; break;}; |
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218 | case EXCEPTION_USE_ILLEGAL_INSTRUCTION : {have_exception = false; break;}; |
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219 | case EXCEPTION_USE_SYSCALL : {have_exception = false; break;}; |
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220 | default : |
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221 | { |
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222 | throw ERRORMORPHEO(FUNCTION,_("Commit : invalid exception_use.\n")); |
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223 | break; |
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224 | } |
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225 | } |
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226 | |
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227 | if (not have_exception) |
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228 | { |
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229 | switch (state) |
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230 | { |
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231 | case ROB_OTHER_WAIT_END : {state = ROB_END_OK_SPECULATIVE; break;} |
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232 | case ROB_BRANCH_WAIT_END : {state = ROB_BRANCH_COMPLETE ; break;} |
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233 | case ROB_MISS_WAIT_END : {state = ROB_END_KO_SPECULATIVE; break;} |
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234 | default : |
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235 | { |
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236 | throw ERRORMORPHEO(FUNCTION,toString(_("Commit : invalid state value (%s).\n"),toString(state).c_str())); |
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237 | break; |
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238 | } |
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239 | } |
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240 | // can have an exception, but this instruction is not sensible a this exception |
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241 | exception = EXCEPTION_NONE; |
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242 | } |
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243 | else |
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244 | { |
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245 | #ifdef DEBUG_TEST |
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246 | if ((entry->type == TYPE_MEMORY) and (exception == EXCEPTION_MEMORY_LOAD_SPECULATIVE)) |
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247 | throw ERRORMORPHEO(FUNCTION,_("Commit : invalid exception.\n")); |
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248 | #endif |
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249 | |
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250 | switch (state) |
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251 | { |
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252 | case ROB_OTHER_WAIT_END : |
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253 | case ROB_BRANCH_WAIT_END : {state = ROB_END_EXCEPTION_WAIT_HEAD; break;} |
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254 | case ROB_MISS_WAIT_END : {state = ROB_END_KO_SPECULATIVE ; break;} |
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255 | default : |
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256 | { |
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257 | throw ERRORMORPHEO(FUNCTION,_("Commit : invalid state value.\n")); |
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258 | break; |
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259 | } |
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260 | } |
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261 | } |
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262 | |
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263 | // update Re Order Buffer |
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264 | entry->state = state; |
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265 | entry->exception = exception; |
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266 | entry->flags = PORT_READ(in_COMMIT_FLAGS [x]); |
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267 | entry->no_sequence = PORT_READ(in_COMMIT_NO_SEQUENCE [x]); |
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268 | entry->data_commit = PORT_READ(in_COMMIT_ADDRESS [x]); |
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269 | } |
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270 | } |
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271 | |
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272 | // =================================================================== |
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273 | // =====[ RETIRE ]==================================================== |
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274 | // =================================================================== |
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275 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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276 | if (internal_BANK_RETIRE_VAL [i]) |
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277 | { |
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278 | uint32_t x = internal_BANK_RETIRE_NUM_RENAME_UNIT [i]; |
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279 | uint32_t y = internal_BANK_RETIRE_NUM_INST [i]; |
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280 | |
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281 | log_printf(TRACE,Commit_unit,FUNCTION," * RETIRE [%d][%d]",x,y); |
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282 | |
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283 | #ifdef STATISTICS |
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284 | if (usage_is_set(_usage,USE_STATISTICS)) |
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285 | (*_stat_nb_inst_retire [x]) ++; |
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286 | #endif |
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287 | |
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288 | #ifdef DEBUG_TEST |
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289 | if (not PORT_READ(in_RETIRE_ACK [x][y])) |
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290 | throw ERRORMORPHEO(FUNCTION,_("Retire : retire_ack must be set.\n")); |
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291 | #endif |
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292 | |
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293 | |
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294 | entry_t * entry = _rob [i].front(); |
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295 | |
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296 | Tcontext_t front_end_id = entry->front_end_id; |
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297 | Tcontext_t context_id = entry->context_id ; |
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298 | Ttype_t type = entry->type ; |
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299 | |
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300 | // Update nb_inst |
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301 | reg_NB_INST_COMMIT_ALL [front_end_id][context_id] --; |
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302 | if (type == TYPE_MEMORY) |
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303 | reg_NB_INST_COMMIT_MEM [front_end_id][context_id] --; |
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304 | |
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305 | reg_NUM_BANK_HEAD = (reg_NUM_BANK_HEAD+1)%_param->_nb_bank; |
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306 | |
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307 | _rob [i].pop_front(); |
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308 | delete entry; |
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309 | } |
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310 | |
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311 | // =================================================================== |
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312 | // =====[ REEXECUTE ]================================================= |
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313 | // =================================================================== |
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314 | if (internal_REEXECUTE_VAL [0] and PORT_READ(in_REEXECUTE_ACK [0])) |
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315 | { |
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316 | uint32_t num_bank = internal_REEXECUTE_NUM_BANK [0]; |
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317 | |
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318 | entry_t * entry = _rob [num_bank].front(); |
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319 | rob_state_t state = entry->state; |
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320 | |
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321 | switch (state) |
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322 | { |
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323 | case ROB_STORE_HEAD_OK : {state = ROB_OTHER_WAIT_END; break; } |
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324 | case ROB_STORE_HEAD_KO : {state = ROB_MISS_WAIT_END ; break; } |
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325 | default : {throw ERRORMORPHEO(FUNCTION,_("Reexecute : invalid state value.\n"));} |
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326 | } |
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327 | |
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328 | entry->state = state; |
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329 | } |
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330 | |
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331 | // =================================================================== |
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332 | // =====[ BRANCH_COMPLETE ]=========================================== |
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333 | // =================================================================== |
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334 | for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) |
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335 | if (internal_BRANCH_COMPLETE_VAL [i] and PORT_READ(in_BRANCH_COMPLETE_ACK [i])) |
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336 | { |
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337 | uint32_t num_bank = internal_BRANCH_COMPLETE_NUM_BANK [i]; |
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338 | |
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339 | entry_t * entry = _rob [num_bank].front(); |
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340 | |
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341 | #ifdef DEBUG_TEST |
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342 | rob_state_t state = entry->state; |
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343 | if (state != ROB_BRANCH_COMPLETE) |
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344 | throw ERRORMORPHEO(FUNCTION,_("Branch_complete : Invalid state value.\n")); |
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345 | #endif |
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346 | |
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347 | entry->state = ROB_END_OK_SPECULATIVE; |
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348 | } |
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349 | |
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350 | // =================================================================== |
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351 | // =====[ EVENT ]===================================================== |
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352 | // =================================================================== |
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353 | |
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354 | // =================================================================== |
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355 | // =====[ DEPTH - HEAD ]============================================== |
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356 | // =================================================================== |
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357 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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358 | if (not _rob[i].empty()) |
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359 | { |
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360 | // Scan all instruction in windows and test if instruction is speculative |
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361 | entry_t * entry = _rob [i].front(); |
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362 | |
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363 | Tcontext_t front_end_id = entry->front_end_id; |
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364 | Tcontext_t context_id = entry->context_id ; |
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365 | rob_state_t state = entry->state; |
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366 | Tdepth_t depth = entry->depth; |
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367 | |
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368 | Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [front_end_id][context_id]):0; |
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369 | Tdepth_t depth_max = PORT_READ(in_DEPTH_MAX[front_end_id][context_id]); |
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370 | |
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371 | // is a valid instruction ? |
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372 | // If DEPTH_CURRENT : |
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373 | // equal at DEPTH_MIN -> not speculative |
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374 | // not include ]DEPTH_MIN:DEPTH_MAX[ -> previous branch miss |
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375 | // include ]DEPTH_MIN:DEPTH_MAX[ -> speculative |
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376 | |
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377 | // All case |
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378 | // ....... min ...X... max ....... OK |
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379 | // ....... min ....... max ...X... KO |
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380 | // ...X... min ....... max ....... KO |
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381 | // ....... max ....... min ...X... OK |
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382 | // ...X... max ....... min ....... OK |
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383 | // ....... max ...X... min ....... KO |
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384 | |
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385 | Tcontrol_t is_valid = ((depth == depth_min) or |
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386 | ((depth_min < depth_max)? |
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387 | (depth<depth_max): |
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388 | ((depth > depth_min) or (depth < depth_max)))); |
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389 | |
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390 | //------------------------------------------------------ |
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391 | // test if instruction is miss speculative |
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392 | //------------------------------------------------------ |
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393 | if (not is_valid) |
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394 | { |
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395 | switch (state) |
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396 | { |
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397 | case ROB_BRANCH_WAIT_END : {state = ROB_MISS_WAIT_END; break;} |
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398 | case ROB_BRANCH_COMPLETE : {state = ROB_END_MISS ; break;} |
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399 | case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_KO; break;} |
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400 | //case ROB_STORE_WAIT_HEAD_KO : {state = ; break;} |
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401 | case ROB_OTHER_WAIT_END : {state = ROB_MISS_WAIT_END; break;} |
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402 | case ROB_END_OK_SPECULATIVE : {state = ROB_END_MISS ; break;} |
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403 | case ROB_END_KO_SPECULATIVE : {state = ROB_END_MISS ; break;} |
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404 | case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_MISS ; break;} |
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405 | |
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406 | // don't change |
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407 | case ROB_STORE_HEAD_KO : {break;} |
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408 | case ROB_MISS_WAIT_END : {break;} |
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409 | case ROB_END_MISS : {break;} |
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410 | |
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411 | // can't have miss speculation |
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412 | case ROB_STORE_HEAD_OK : |
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413 | case ROB_END_OK : |
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414 | case ROB_END_KO : |
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415 | case ROB_END_EXCEPTION : |
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416 | default : |
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417 | { |
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418 | throw ERRORMORPHEO(FUNCTION,_("Miss Speculation : Invalide state.\n")); |
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419 | break; |
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420 | } |
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421 | } |
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422 | } |
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423 | |
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424 | //------------------------------------------------------ |
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425 | // test if instruction is not speculative |
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426 | //------------------------------------------------------ |
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427 | if (entry->depth == depth_min) |
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428 | { |
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429 | switch (state) |
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430 | { |
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431 | case ROB_END_OK_SPECULATIVE : {state = ROB_END_OK ; break;} |
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432 | case ROB_END_KO_SPECULATIVE : {state = ROB_END_KO ; break;} |
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433 | default : {break;} |
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434 | } |
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435 | } |
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436 | |
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437 | //------------------------------------------------------ |
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438 | // test if instruction is store and head |
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439 | //------------------------------------------------------ |
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440 | if (i == reg_NUM_BANK_HEAD) |
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441 | { |
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442 | switch (state) |
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443 | { |
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444 | case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_OK; break;} |
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445 | case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_EXCEPTION; break;} |
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446 | default : {break;} |
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447 | } |
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448 | } |
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449 | |
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450 | entry->state = state; |
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451 | } |
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452 | } |
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453 | |
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454 | // =================================================================== |
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455 | // =====[ OTHER ]===================================================== |
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456 | // =================================================================== |
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457 | |
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458 | log_printf(TRACE,Commit_unit,FUNCTION," * Dump ROB (Re-Order-Buffer)"); |
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459 | log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_head : %d",reg_NUM_BANK_HEAD); |
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460 | log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_tail : %d",reg_NUM_BANK_TAIL); |
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461 | |
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462 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
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463 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
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464 | log_printf(TRACE,Commit_unit,FUNCTION," * num_inst[%d][%d] all : %d, mem : %d",i,j,reg_NB_INST_COMMIT_ALL[i][j],reg_NB_INST_COMMIT_MEM[i][j]); |
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465 | |
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466 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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467 | { |
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468 | log_printf(TRACE,Commit_unit,FUNCTION," * Bank[%d] size : %d, ptr : %d",i,(int)_rob[i].size(), reg_BANK_PTR [i]); |
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469 | |
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470 | #ifdef STATISTICS |
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471 | if (usage_is_set(_usage,USE_STATISTICS)) |
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472 | *(_stat_bank_nb_inst [i]) += _rob[i].size(); |
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473 | #endif |
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474 | |
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475 | uint32_t x=0; |
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476 | for (std::list<entry_t*>::iterator it=_rob[i].begin(); |
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477 | it!=_rob[i].end(); |
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478 | it++) |
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479 | { |
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480 | log_printf(TRACE,Commit_unit,FUNCTION," [%d] %.8x (%.8x) %s - ptr : %d", |
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481 | x, |
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482 | (*it)->address, |
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483 | (*it)->address<<2, |
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484 | toString((*it)->state).c_str(), |
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485 | (*it)->ptr); |
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486 | x++; |
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487 | } |
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488 | } |
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489 | |
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490 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
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491 | end_cycle (); |
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492 | #endif |
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493 | |
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494 | log_end(Commit_unit,FUNCTION); |
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495 | }; |
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496 | |
---|
497 | }; // end namespace commit_unit |
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498 | }; // end namespace ooo_engine |
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499 | }; // end namespace multi_ooo_engine |
---|
500 | }; // end namespace core |
---|
501 | |
---|
502 | }; // end namespace behavioural |
---|
503 | }; // end namespace morpheo |
---|
504 | #endif |
---|