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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp @ 110

Last change on this file since 110 was 110, checked in by rosiere, 15 years ago
1) OOO_egine : add stat to depiste low perf source 2) Commit : add stat 3) LSU_Pointer : retire - always ack (else combinatory loop). insert - max nb_inst_memory 4) TopLevel? : add debug_idle_time to stop combinatory loop. 5) Issue_queue : add reexecute_queue, new implementation (routage after issue_queue) 6) Decod / Predictor : add "can_continue"
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File size: 39.7 KB

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1	#ifdef SYSTEMC
2	/*
3	* $Id: Commit_unit_transition.cpp 110 2009-02-19 16:31:47Z rosiere $
4	*
5	* [ Description ]
6	*
7	*/
8
9	#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h"
10	#include "Behavioural/include/Simulation.h"
11
12	namespace morpheo {
13	namespace behavioural {
14	namespace core {
15	namespace multi_ooo_engine {
16	namespace ooo_engine {
17	namespace commit_unit {
18
19
20	#undef FUNCTION
21	#define FUNCTION "Commit_unit::transition"
22	void Commit_unit::transition (void)
23	{
24	log_begin(Commit_unit,FUNCTION);
25	log_function(Commit_unit,FUNCTION,_name.c_str());
26
27	if (PORT_READ(in_NRESET) == 0)
28	{
29	// Clear all bank
30	for (uint32_t i=0; i<_param->_nb_bank; i++)
31	{
32	_rob [i].clear();
33	reg_BANK_PTR [i] = 0;
34	}
35
36	// Reset pointer
37	reg_NUM_BANK_HEAD = 0;
38	reg_NUM_BANK_TAIL = 0;
39
40	// Reset counter
41	for (uint32_t i=0; i<_param->_nb_front_end; i++)
42	for (uint32_t j=0; j<_param->_nb_context [i]; j++)
43	{
44	_nb_cycle_idle [i][j] = 0;
45
46	reg_NB_INST_COMMIT_ALL [i][j] = 0;
47	reg_NB_INST_COMMIT_MEM [i][j] = 0;
48
49	reg_EVENT_STATE [i][j] = EVENT_STATE_NO_EVENT;
50	reg_EVENT_FLUSH [i][j] = false;
51
52	// reg_PC_PREVIOUS [i][j] = (0x100-4)>>2;
53	reg_PC_CURRENT [i][j] = (0x100 )>>2;
54	reg_PC_CURRENT_IS_DS [i][j] = 0;
55	reg_PC_CURRENT_IS_DS_TAKE [i][j] = 0;
56	reg_PC_NEXT [i][j] = (0x100+4)>>2;
57	}
58
59	// Reset priority algorithm
60	_priority_insert->reset();
61	}
62	else
63	{
64	// Increase number idle cycle
65	for (uint32_t i=0; i<_param->_nb_front_end; i++)
66	for (uint32_t j=0; j<_param->_nb_context [i]; j++)
67	_nb_cycle_idle [i][j] ++;
68
69	// Compute next priority
70	_priority_insert->transition();
71
72	// ===================================================================
73	// =====[ GARBAGE COLLECTOR ]=========================================
74	// ===================================================================
75	for (uint32_t i=0; i<_param->_nb_front_end; i++)
76	for (uint32_t j=0; j<_param->_nb_context [i]; j++)
77	switch (reg_EVENT_STATE [i][j])
78	{
79	case EVENT_STATE_EVENT :
80	{
81	if (internal_RETIRE_EVENT_VAL [i][j] and in_RETIRE_EVENT_ACK [i][j])
82	reg_EVENT_STATE [i][j] = EVENT_STATE_WAITEND ;
83	break;
84	}
85	case EVENT_STATE_WAITEND :
86	{
87	Tcounter_t nb_inst_all = PORT_READ(in_NB_INST_DECOD_ALL [i][j]) + reg_NB_INST_COMMIT_ALL [i][j];
88	if (nb_inst_all == 0)
89	{
90	reg_EVENT_STATE [i][j] = EVENT_STATE_END;
91	reg_EVENT_FLUSH [i][j] = false;
92	}
93	break;
94	}
95	case EVENT_STATE_END :
96	{
97	reg_EVENT_STATE [i][j] = EVENT_STATE_NO_EVENT;
98	break;
99	}
100	// case EVENT_STATE_NO_EVENT :
101	default : break;
102	}
103
104	// ===================================================================
105	// =====[ INSERT ]====================================================
106	// ===================================================================
107	for (uint32_t i=0; i<_param->_nb_bank; i++)
108	if (internal_BANK_INSERT_VAL [i])
109	{
110	// get rename unit source and instruction.
111	uint32_t x = internal_BANK_INSERT_NUM_RENAME_UNIT [i];
112	uint32_t y = internal_BANK_INSERT_NUM_INST [i];
113
114	if (PORT_READ(in_INSERT_VAL [x][y]))
115	{
116	log_printf(TRACE,Commit_unit,FUNCTION," * INSERT [%d][%d]",x,y);
117
118	// get information
119	Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_INSERT_FRONT_END_ID [x][y]):0;
120	Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_INSERT_CONTEXT_ID [x][y]):0;
121	Ttype_t type = PORT_READ(in_INSERT_TYPE [x][y]);
122	Toperation_t operation = PORT_READ(in_INSERT_OPERATION [x][y]);
123	bool is_store = is_operation_memory_store(operation);
124
125	Texception_t exception = PORT_READ(in_INSERT_EXCEPTION [x][y]);
126
127	log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id);
128	log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id);
129	log_printf(TRACE,Commit_unit,FUNCTION," * type : %s",toString(type).c_str());
130	log_printf(TRACE,Commit_unit,FUNCTION," * operation : %d",operation );
131	log_printf(TRACE,Commit_unit,FUNCTION," * exception : %d",exception );
132
133	// Create new entry.
134	entry_t * entry = new entry_t;
135
136	entry->ptr = reg_BANK_PTR [i];
137	entry->front_end_id = front_end_id;
138	entry->context_id = context_id ;
139	entry->rename_unit_id = x;
140	entry->depth = (_param->_have_port_depth)?PORT_READ(in_INSERT_DEPTH [x][y]):0;
141	entry->type = type;
142	entry->operation = operation;
143	entry->is_delay_slot = PORT_READ(in_INSERT_IS_DELAY_SLOT [x][y]);
144	// entry->address = PORT_READ(in_INSERT_ADDRESS [x][y]);
145	entry->exception = exception;
146	entry->exception_use = PORT_READ(in_INSERT_EXCEPTION_USE [x][y]);
147	entry->use_store_queue = (type == TYPE_MEMORY) and ( is_store);
148	entry->use_load_queue = (type == TYPE_MEMORY) and (not is_store);
149	entry->store_queue_ptr_write = PORT_READ(in_INSERT_STORE_QUEUE_PTR_WRITE [x][y]);
150	entry->load_queue_ptr_write = (_param->_have_port_load_queue_ptr)?PORT_READ(in_INSERT_LOAD_QUEUE_PTR_WRITE [x][y]):0;
151	entry->read_ra = PORT_READ(in_INSERT_READ_RA [x][y]);
152	entry->num_reg_ra_log = PORT_READ(in_INSERT_NUM_REG_RA_LOG [x][y]);
153	entry->num_reg_ra_phy = PORT_READ(in_INSERT_NUM_REG_RA_PHY [x][y]);
154	entry->read_rb = PORT_READ(in_INSERT_READ_RB [x][y]);
155	entry->num_reg_rb_log = PORT_READ(in_INSERT_NUM_REG_RB_LOG [x][y]);
156	entry->num_reg_rb_phy = PORT_READ(in_INSERT_NUM_REG_RB_PHY [x][y]);
157	entry->read_rc = PORT_READ(in_INSERT_READ_RC [x][y]);
158	entry->num_reg_rc_log = PORT_READ(in_INSERT_NUM_REG_RC_LOG [x][y]);
159	entry->num_reg_rc_phy = PORT_READ(in_INSERT_NUM_REG_RC_PHY [x][y]);
160	entry->write_rd = PORT_READ(in_INSERT_WRITE_RD [x][y]);
161	entry->num_reg_rd_log = PORT_READ(in_INSERT_NUM_REG_RD_LOG [x][y]);
162	entry->num_reg_rd_phy_old = PORT_READ(in_INSERT_NUM_REG_RD_PHY_OLD [x][y]);
163	entry->num_reg_rd_phy_new = PORT_READ(in_INSERT_NUM_REG_RD_PHY_NEW [x][y]);
164	entry->write_re = PORT_READ(in_INSERT_WRITE_RE [x][y]);
165	entry->num_reg_re_log = PORT_READ(in_INSERT_NUM_REG_RE_LOG [x][y]);
166	entry->num_reg_re_phy_old = PORT_READ(in_INSERT_NUM_REG_RE_PHY_OLD [x][y]);
167	entry->num_reg_re_phy_new = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [x][y]);
168	entry->no_sequence = type == TYPE_BRANCH;
169	entry->speculative = true;
170	#ifdef DEBUG
171	entry->address = PORT_READ(in_INSERT_ADDRESS [x][y]);
172	#endif
173	entry->address_next = PORT_READ(in_INSERT_ADDRESS_NEXT [x][y]);
174
175	// Test if exception :
176	// * yes : no execute instruction, wait ROB Head
177	// * no : test type
178	// * BRANCH : l.j -> branch is ended
179	// other -> wait the execution end of branchment
180	// * MEMORY : store -> wait store is at head of ROB
181	// other -> wait end of instruction
182	// * OTHER
183
184	// bool flush = reg_EVENT_FLUSH [front_end_id][context_id];
185
186	// log_printf(TRACE,Commit_unit,FUNCTION," * flush : %d",flush);
187
188	// if (flush)
189	// {
190	// entry->state = ROB_END_MISS; // All type (branch, memory and others), because, is not execute
191	// }
192	// else
193	{
194	if (exception == EXCEPTION_NONE)
195	{
196	Tcontrol_t no_execute = PORT_READ(in_INSERT_NO_EXECUTE [x][y]);
197	// no_execute : l.j, l.nop, l.rfe
198
199	log_printf(TRACE,Commit_unit,FUNCTION," * no_execute : %d",no_execute);
200
201	switch (type)
202	{
203	case TYPE_BRANCH : {entry->state=(no_execute==1)?ROB_BRANCH_COMPLETE:ROB_BRANCH_WAIT_END ; break;}
204	case TYPE_MEMORY : {entry->state=(is_store ==1)?ROB_STORE_WAIT_HEAD_OK:ROB_OTHER_WAIT_END; break;}
205	default : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:ROB_OTHER_WAIT_END; break;}
206	}
207	}
208	else
209	{
210	// Have an exception : wait head of ROB
211
212	// in_INSERT_NO_EXECUTE [x][y] : l.sys, l.trap
213
214	entry->state = ROB_END_EXCEPTION_WAIT_HEAD;
215	}
216	}
217
218	#ifdef STATISTICS
219	if (usage_is_set(_usage,USE_STATISTICS))
220	(*_stat_nb_inst_insert [x]) ++;
221	#endif
222
223	// Push in rob
224	_rob[i].push_back(entry);
225
226	// Update counter and pointer
227	reg_NB_INST_COMMIT_ALL [front_end_id][context_id] ++;
228	if (type == TYPE_MEMORY)
229	reg_NB_INST_COMMIT_MEM [front_end_id][context_id] ++;
230
231	reg_NUM_BANK_TAIL = (reg_NUM_BANK_TAIL+1)%_param->_nb_bank;
232	reg_BANK_PTR [i] = (reg_BANK_PTR [i]+1)%_param->_size_bank;
233	}
234	}
235
236	// ===================================================================
237	// =====[ COMMIT ]====================================================
238	// ===================================================================
239
240	#ifdef STATISTICS
241	if (usage_is_set(_usage,USE_STATISTICS))
242	(*_stat_nb_inst_commit_conflit_access) += internal_BANK_COMMIT_CONFLIT_ACCESS;
243	#endif
244
245	for (uint32_t i=0; i<_param->_nb_bank; i++)
246	for (uint32_t j=0; j<_param->_nb_bank_access_commit; j++)
247	if (internal_BANK_COMMIT_VAL [i][j])
248	{
249	// An instruction is executed. Change state of this instruction
250
251	uint32_t x = internal_BANK_COMMIT_NUM_INST [i][j];
252
253	if (PORT_READ(in_COMMIT_VAL [x]) and PORT_READ(in_COMMIT_WEN [x]))
254	{
255	log_printf(TRACE,Commit_unit,FUNCTION," * COMMIT [%d]",x);
256
257	#ifdef STATISTICS
258	if (usage_is_set(_usage,USE_STATISTICS))
259	(*_stat_nb_inst_commit) ++;
260	#endif
261
262	log_printf(TRACE,Commit_unit,FUNCTION," * num_bank : %d",i);
263
264	// find the good entry !!!
265	entry_t * entry = internal_BANK_COMMIT_ENTRY [i][j];
266
267	//Toperation_t operation = PORT_READ(in_COMMIT_OPERATION [x]);
268	//Ttype_t type = PORT_READ(in_COMMIT_TYPE [x]);
269	Texception_t exception = PORT_READ(in_COMMIT_EXCEPTION [x]);
270
271	rob_state_t state = entry->state;
272	Tcontext_t front_end_id = entry->front_end_id;
273	Tcontext_t context_id = entry->context_id;
274
275	// change state : test exception_use
276	// * test if exception : exception and mask
277
278	bool have_exception = false;
279	bool have_miss_speculation = false;
280
281	if (exception != EXCEPTION_NONE)
282	{
283	// Test if the instruction is a load and is a miss speculation (load is commit, but they have an dependence with a previous store)
284	have_miss_speculation = (exception == EXCEPTION_MEMORY_MISS_SPECULATION);
285
286	switch (entry->exception_use)
287	{
288	// Have overflow exception if bit overflow enable is set.
289	case EXCEPTION_USE_RANGE : {have_exception = ((exception == EXCEPTION_RANGE) and PORT_READ(in_SPR_READ_SR_OVE[front_end_id][context_id])); break;}
290	case EXCEPTION_USE_MEMORY_WITH_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or
291	(exception == EXCEPTION_DATA_TLB ) or
292	(exception == EXCEPTION_DATA_PAGE) or
293	(exception == EXCEPTION_ALIGNMENT)); break;};
294	case EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or
295	(exception == EXCEPTION_DATA_TLB ) or
296	(exception == EXCEPTION_DATA_PAGE)); break;};
297	case EXCEPTION_USE_CUSTOM_0 : {have_exception = (exception == EXCEPTION_CUSTOM_0); break;};
298	case EXCEPTION_USE_CUSTOM_1 : {have_exception = (exception == EXCEPTION_CUSTOM_1); break;};
299	case EXCEPTION_USE_CUSTOM_2 : {have_exception = (exception == EXCEPTION_CUSTOM_2); break;};
300	case EXCEPTION_USE_CUSTOM_3 : {have_exception = (exception == EXCEPTION_CUSTOM_3); break;};
301	case EXCEPTION_USE_CUSTOM_4 : {have_exception = (exception == EXCEPTION_CUSTOM_4); break;};
302	case EXCEPTION_USE_CUSTOM_5 : {have_exception = (exception == EXCEPTION_CUSTOM_5); break;};
303	case EXCEPTION_USE_CUSTOM_6 : {have_exception = (exception == EXCEPTION_CUSTOM_6); break;};
304	// Case already manage (decod stage -> in insert in ROB)
305	case EXCEPTION_USE_TRAP : {have_exception = false; exception = EXCEPTION_NONE; break;};
306	case EXCEPTION_USE_NONE : {have_exception = false; exception = EXCEPTION_NONE; break;};
307	case EXCEPTION_USE_ILLEGAL_INSTRUCTION : {have_exception = false; exception = EXCEPTION_NONE; break;};
308	case EXCEPTION_USE_SYSCALL : {have_exception = false; exception = EXCEPTION_NONE; break;};
309	default :
310	{
311	throw ERRORMORPHEO(FUNCTION,_("Commit : invalid exception_use.\n"));
312	break;
313	}
314	}
315	}
316
317	switch (state)
318	{
319	// Branch ...
320	case ROB_BRANCH_WAIT_END : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:ROB_BRANCH_COMPLETE; break;}
321	// Store KO
322	case ROB_MISS_WAIT_END : {state = ROB_END_KO_SPECULATIVE; break;}
323	// Store OK, Load and other instruction
324	case ROB_OTHER_WAIT_END : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:((have_miss_speculation)?ROB_END_LOAD_MISS_SPECULATIVE:ROB_END_OK_SPECULATIVE); break;}
325	default :
326	{
327	throw ERRORMORPHEO(FUNCTION,toString(_("Commit : invalid state value (%s).\n"),toString(state).c_str()));
328	break;
329	}
330	}
331
332	// update Re Order Buffer
333	entry->state = state;
334	entry->exception = exception;
335	entry->flags = PORT_READ(in_COMMIT_FLAGS [x]);
336	entry->no_sequence = PORT_READ(in_COMMIT_NO_SEQUENCE [x]);
337	// jalr, jr : address_dest is in register
338	if ((entry->type == TYPE_BRANCH) and
339	(entry->operation == OPERATION_BRANCH_L_JALR) and
340	(entry->read_rb))
341	entry->address_next = PORT_READ(in_COMMIT_ADDRESS [x]);
342	}
343	}
344
345	// ===================================================================
346	// =====[ RETIRE ]====================================================
347	// ===================================================================
348	for (uint32_t i=0; i<_param->_nb_bank; i++)
349	{
350	uint32_t num_bank = (internal_BANK_RETIRE_HEAD+i)%_param->_nb_bank;
351
352	if (internal_BANK_RETIRE_VAL [num_bank])
353	{
354	uint32_t x = internal_BANK_RETIRE_NUM_RENAME_UNIT [num_bank];
355	uint32_t y = internal_BANK_RETIRE_NUM_INST [num_bank];
356
357	log_printf(TRACE,Commit_unit,FUNCTION," * RETIRE [%d][%d]",x,y);
358
359	#ifdef DEBUG_TEST
360	if (not PORT_READ(in_RETIRE_ACK [x][y]))
361	throw ERRORMORPHEO(FUNCTION,_("Retire : retire_ack must be set.\n"));
362	#endif
363
364	entry_t * entry = _rob [num_bank].front();
365	rob_state_t state = entry->state;
366
367	Tcontext_t front_end_id = entry->front_end_id;
368	Tcontext_t context_id = entry->context_id ;
369	uint32_t num_thread = _param->_translate_num_context_to_num_thread [front_end_id][context_id];
370	Ttype_t type = entry->type ;
371	bool retire_ok = false;
372
373	log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id );
374	log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id );
375	log_printf(TRACE,Commit_unit,FUNCTION," * num_thread : %d",num_thread );
376	log_printf(TRACE,Commit_unit,FUNCTION," * type : %s",toString(type).c_str());
377	log_printf(TRACE,Commit_unit,FUNCTION," * state : %s",toString(state).c_str());
378
379	if ((state == ROB_END_OK ) or
380	// (state == ROB_END_KO ) or
381	(state == ROB_END_BRANCH_MISS) or
382	(state == ROB_END_LOAD_MISS )// or
383	// (state == ROB_END_MISS ) or
384	// (state == ROB_END_EXCEPTION )
385	)
386	{
387	log_printf(TRACE,Commit_unit,FUNCTION," * retire_ok");
388
389	retire_ok = true;
390
391	// reg_PC_PREVIOUS [front_end_id][context_id] = reg_PC_CURRENT [front_end_id][context_id];
392	reg_PC_CURRENT [front_end_id][context_id] = reg_PC_NEXT [front_end_id][context_id];
393	reg_PC_CURRENT_IS_DS [front_end_id][context_id] = entry->type == TYPE_BRANCH;
394	reg_PC_CURRENT_IS_DS_TAKE [front_end_id][context_id] = entry->no_sequence;
395	reg_PC_NEXT [front_end_id][context_id] = (entry->no_sequence)?(entry->address_next):(reg_PC_CURRENT [front_end_id][context_id]+1);
396
397	// if (entry->address_next != reg_PC_NEXT [front_end_id][context_id])
398	// throw ERRORMORPHEO(FUNCTION,toString(_("Retire : Instruction's address_next (%.8x) is different of commit_unit's address_next (%.8x)"),entry->address_next,reg_PC_NEXT [front_end_id][context_id]));
399	}
400
401	if ((state == ROB_END_BRANCH_MISS) or
402	(state == ROB_END_LOAD_MISS))
403	{
404	reg_EVENT_STATE [front_end_id][context_id] = EVENT_STATE_EVENT;
405	reg_EVENT_FLUSH [front_end_id][context_id] = true;
406	}
407
408	// Update nb_inst
409	reg_NB_INST_COMMIT_ALL [front_end_id][context_id] --;
410	if (type == TYPE_MEMORY)
411	reg_NB_INST_COMMIT_MEM [front_end_id][context_id] --;
412
413	reg_NUM_BANK_HEAD = (reg_NUM_BANK_HEAD+1)%_param->_nb_bank;
414
415	_rob [num_bank].pop_front();
416	delete entry;
417
418	// Transaction on retire interface : reset watch dog timer.
419	_nb_cycle_idle [front_end_id][context_id] = 0;
420
421	// Increase stop condition
422	if (retire_ok)
423	_simulation_nb_instruction_commited [num_thread] ++;
424
425	#ifdef STATISTICS
426	if (usage_is_set(_usage,USE_STATISTICS))
427	{
428	(*_stat_nb_inst_retire [x]) ++;
429
430	if (retire_ok)
431	{
432	(*_stat_nb_inst_retire_ok [num_thread]) ++;
433	(*_stat_nb_inst_type [type] ) ++;
434	}
435	else
436	(*_stat_nb_inst_retire_ko [num_thread]) ++;
437	}
438	#endif
439	}
440	}
441
442	// ===================================================================
443	// =====[ REEXECUTE ]=================================================
444	// ===================================================================
445	if (internal_REEXECUTE_VAL [0] and PORT_READ(in_REEXECUTE_ACK [0]))
446	{
447	log_printf(TRACE,Commit_unit,FUNCTION," * REEXECUTE [0]");
448
449	uint32_t num_bank = internal_REEXECUTE_NUM_BANK [0];
450
451	entry_t * entry = _rob [num_bank].front();
452	rob_state_t state = entry->state;
453
454	switch (state)
455	{
456	case ROB_STORE_HEAD_OK : {state = ROB_OTHER_WAIT_END; break; }
457	case ROB_STORE_HEAD_KO : {state = ROB_MISS_WAIT_END ; break; }
458	default : {throw ERRORMORPHEO(FUNCTION,_("Reexecute : invalid state value.\n"));}
459	}
460
461	entry->state = state;
462	}
463
464	// ===================================================================
465	// =====[ BRANCH_COMPLETE ]===========================================
466	// ===================================================================
467	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
468	if (internal_BRANCH_COMPLETE_VAL [i] and PORT_READ(in_BRANCH_COMPLETE_ACK [i]))
469	{
470	log_printf(TRACE,Commit_unit,FUNCTION," * BRANCH_COMPLETE [%d]",i);
471	log_printf(TRACE,Commit_unit,FUNCTION," * miss_prediction : %d",PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]));
472
473	uint32_t num_bank = internal_BRANCH_COMPLETE_NUM_BANK [i];
474
475	entry_t * entry = _rob [num_bank].front();
476
477	#ifdef DEBUG_TEST
478	rob_state_t state = entry->state;
479	if (state != ROB_BRANCH_COMPLETE)
480	throw ERRORMORPHEO(FUNCTION,_("Branch_complete : Invalid state value.\n"));
481	#endif
482
483	entry->state = (PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]))?ROB_END_BRANCH_MISS_SPECULATIVE:ROB_END_OK_SPECULATIVE;
484	// entry->state = ROB_END_OK_SPECULATIVE;
485	}
486
487	// ===================================================================
488	// =====[ UPDATE ]====================================================
489	// ===================================================================
490	if (internal_UPDATE_VAL and PORT_READ(in_UPDATE_ACK))
491	{
492	log_printf(TRACE,Commit_unit,FUNCTION," * UPDATE");
493
494	entry_t * entry = _rob [internal_UPDATE_NUM_BANK].front();
495
496	switch (entry->state)
497	{
498	// case ROB_END_EXCEPTION_UPDATE :
499	// {
500	// entry->state = ROB_END_KO;
501	// throw ERRORMORPHEO(FUNCTION,_("Moore : exception is not yet supported (Coming Soon).\n"));
502	// break;
503	// }
504	case ROB_END_LOAD_MISS_UPDATE :
505	{
506	log_printf(TRACE,Commit_unit,FUNCTION," * ROB_END_LOAD_MISS_UPDATE");
507
508	entry->state = ROB_END_LOAD_MISS;
509	break;
510	}
511	default :
512	{
513	throw ERRORMORPHEO(FUNCTION,_("Update : invalid state.\n"));
514	break;
515	}
516	}
517
518	}
519
520	// ===================================================================
521	// =====[ EVENT ]=====================================================
522	// ===================================================================
523	// for (uint32_t i=0; i < _param->_nb_front_end; ++i)
524	// for (uint32_t j=0; j < _param->_nb_context[i]; ++j)
525	// if (PORT_READ(in_EVENT_VAL [i][j]) and internal_EVENT_ACK [i][j])
526	// {
527	// log_printf(TRACE,Commit_unit,FUNCTION," * EVENT [%d][%d]",i,j);
528
529	// reg_PC_CURRENT [i][j] = PORT_READ(in_EVENT_ADDRESS [i][j]);
530	// reg_PC_CURRENT_IS_DS [i][j] = PORT_READ(in_EVENT_IS_DS_TAKE [i][j]); // ??
531	// reg_PC_CURRENT_IS_DS_TAKE [i][j] = PORT_READ(in_EVENT_IS_DS_TAKE [i][j]);
532	// reg_PC_NEXT [i][j] = PORT_READ(in_EVENT_ADDRESS_NEXT [i][j]);
533	// // PORT_READ(in_EVENT_ADDRESS_NEXT_VAL [i][j]);
534	// }
535
536	// ===================================================================
537	// =====[ DEPTH - HEAD ]==============================================
538	// ===================================================================
539	for (uint32_t i=0; i<_param->_nb_bank; i++)
540	if (not _rob[i].empty())
541	{
542	// Scan all instruction in windows and test if instruction is speculative
543	entry_t * entry = _rob [i].front();
544
545	Tcontext_t front_end_id = entry->front_end_id;
546	Tcontext_t context_id = entry->context_id ;
547	rob_state_t state = entry->state;
548	Tdepth_t depth = entry->depth;
549
550	Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[front_end_id][context_id]):0;
551	Tdepth_t depth_max = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[front_end_id][context_id]):0;
552	Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL [front_end_id][context_id]);
553
554	// is a valid instruction ?
555	// If DEPTH_CURRENT :
556	// equal at DEPTH_MIN -> not speculative
557	// not include ]DEPTH_MIN:DEPTH_MAX] -> previous branch miss
558	// include ]DEPTH_MIN:DEPTH_MAX] -> speculative
559
560	// All case
561	// ....... min ...X... max ....... OK
562	// ....... min ....... max ...X... KO
563	// ...X... min ....... max ....... KO
564	// ....... max ....... min ...X... OK
565	// ...X... max ....... min ....... OK
566	// ....... max ...X... min ....... KO
567
568	bool flush = reg_EVENT_FLUSH [front_end_id][context_id];
569	bool speculative = entry->speculative and not (depth == depth_min);
570	Tcontrol_t is_valid = ((not speculative or
571	(speculative and (depth_full or // all is valid
572	((depth_min <= depth_max)? // test if depth is overflow
573	((depth >= depth_min) and (depth <=depth_max)):
574	((depth >= depth_min) or (depth <=depth_max))))))
575	and not flush);
576
577	// Tcontrol_t is_valid = ((depth == depth_min) and not flush);
578
579	log_printf(TRACE,Commit_unit,FUNCTION," * HEAD [%d]",i);
580	log_printf(TRACE,Commit_unit,FUNCTION," * is_valid : %d ((depth == depth_min) and not flush)",is_valid);
581	log_printf(TRACE,Commit_unit,FUNCTION," * depth : %d",depth );
582	log_printf(TRACE,Commit_unit,FUNCTION," * depth_min : %d",depth_min);
583	log_printf(TRACE,Commit_unit,FUNCTION," * depth_max : %d",depth_max);
584	log_printf(TRACE,Commit_unit,FUNCTION," * depth_full : %d",depth_full);
585	log_printf(TRACE,Commit_unit,FUNCTION," * flush : %d",flush);
586
587	//------------------------------------------------------
588	// test if instruction is miss speculative
589	//------------------------------------------------------
590	if (not is_valid)
591	{
592	switch (state)
593	{
594	case ROB_BRANCH_WAIT_END : {state = ROB_MISS_WAIT_END; break;}
595	case ROB_BRANCH_COMPLETE : {state = ROB_END_MISS ; break;}
596	case ROB_END_BRANCH_MISS :
597	case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;}
598	case ROB_END_LOAD_MISS_UPDATE :
599	case ROB_END_LOAD_MISS :
600	case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;}
601	case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_KO; break;}
602	//case ROB_STORE_WAIT_HEAD_KO : {state = ; break;}
603	case ROB_OTHER_WAIT_END : {state = ROB_MISS_WAIT_END; break;}
604	case ROB_END_OK :
605	case ROB_END_OK_SPECULATIVE : {state = ROB_END_MISS ; break;}
606	case ROB_END_KO :
607	case ROB_END_KO_SPECULATIVE : {state = ROB_END_MISS ; break;}
608	case ROB_END_EXCEPTION_UPDATE :
609	case ROB_END_EXCEPTION :
610	case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_MISS ; break;}
611
612	// don't change
613	case ROB_STORE_HEAD_KO : {break;}
614	case ROB_MISS_WAIT_END : {break;}
615	case ROB_END_MISS : {break;}
616
617	// can't have miss speculation
618	case ROB_STORE_HEAD_OK :
619	default :
620	{
621	throw ERRORMORPHEO(FUNCTION,toString(_("Miss Speculation : Invalide state : %s.\n"),toString(state).c_str()));
622	break;
623	}
624	}
625	}
626
627	//------------------------------------------------------
628	// test if instruction is not speculative
629	//------------------------------------------------------
630	entry->speculative = speculative;
631	// if (entry->depth == depth_min)
632	if (not speculative)
633	{
634	switch (state)
635	{
636	case ROB_END_OK_SPECULATIVE : {state = ROB_END_OK ; break;}
637	case ROB_END_KO_SPECULATIVE : {state = ROB_END_KO ; break;}
638	case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_BRANCH_MISS ; break;}
639	case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_LOAD_MISS_UPDATE ; break;}
640	default : {break;} // else, no change
641	}
642	}
643
644	//------------------------------------------------------
645	// test if instruction is store and head
646	//------------------------------------------------------
647	if (i == reg_NUM_BANK_HEAD)
648	{
649	switch (state)
650	{
651	case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_OK; break;}
652	case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_EXCEPTION_UPDATE; break;}
653	default : {break;} // else, no change
654	}
655	}
656
657	entry->state = state;
658	}
659	}
660
661	// ===================================================================
662	// =====[ OTHER ]=====================================================
663	// ===================================================================
664
665	#ifdef STATISTICS
666	for (uint32_t i=0; i<_param->_nb_bank; i++)
667	if (usage_is_set(_usage,USE_STATISTICS))
668	*(_stat_bank_nb_inst [i]) += _rob[i].size();
669	#endif
670
671	#if (DEBUG >= DEBUG_TRACE) and (DEBUG_Commit_unit == true)
672	{
673	log_printf(TRACE,Commit_unit,FUNCTION," * Dump ROB (Re-Order-Buffer)");
674	log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_head : %d",reg_NUM_BANK_HEAD);
675	log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_tail : %d",reg_NUM_BANK_TAIL);
676
677	for (uint32_t i=0; i<_param->_nb_front_end; i++)
678	for (uint32_t j=0; j<_param->_nb_context [i]; j++)
679	{
680	log_printf(TRACE,Commit_unit,FUNCTION," * [%d][%d] - %d",i,j,_param->_translate_num_context_to_num_thread [i][j]);
681	log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_STATE : %s",toString(reg_EVENT_STATE [i][j]).c_str());
682	log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_FLUSH : %d",reg_EVENT_FLUSH [i][j]);
683	log_printf(TRACE,Commit_unit,FUNCTION," * NB_INST_ALL : %d",reg_NB_INST_COMMIT_ALL[i][j]);
684	log_printf(TRACE,Commit_unit,FUNCTION," * NB_INST_MEM : %d",reg_NB_INST_COMMIT_MEM[i][j]);
685	log_printf(TRACE,Commit_unit,FUNCTION," * PC_CURRENT : %.8x (%.8x) - %d %d",reg_PC_CURRENT [i][j],reg_PC_CURRENT [i][j]<<2, reg_PC_CURRENT_IS_DS [i][j], reg_PC_CURRENT_IS_DS_TAKE [i][j]);
686	log_printf(TRACE,Commit_unit,FUNCTION," * PC_NEXT : %.8x (%.8x)",reg_PC_NEXT [i][j],reg_PC_NEXT [i][j]<<2);
687	}
688
689	for (uint32_t i=0; i<_param->_nb_bank; i++)
690	{
691	uint32_t num_bank = (reg_NUM_BANK_HEAD+i)%_param->_nb_bank;
692
693	log_printf(TRACE,Commit_unit,FUNCTION," * Bank [%d] size : %d, ptr : %d",num_bank,(int)_rob[num_bank].size(), reg_BANK_PTR [i]);
694
695	for (std::list<entry_t*>::iterator it=_rob[num_bank].begin();
696	it!=_rob[num_bank].end();
697	it++)
698	{
699	log_printf(TRACE,Commit_unit,FUNCTION," [%.4d][%.4d] (%.4d) %.4d %.4d %.4d %.4d, %.3d %.3d, %.1d, %.1d %.4d, %.1d %.4d, %s",
700	num_bank ,
701	(*it)->ptr ,
702	((num_bank << _param->_shift_num_bank) \| (*it)->ptr),
703	(*it)->front_end_id ,
704	(*it)->context_id ,
705	(*it)->rename_unit_id ,
706	(*it)->depth ,
707	(*it)->type ,
708	(*it)->operation ,
709	(*it)->is_delay_slot ,
710	(*it)->use_store_queue ,
711	(*it)->store_queue_ptr_write ,
712	(*it)->use_load_queue ,
713	(*it)->load_queue_ptr_write ,
714	toString((*it)->state).c_str() );
715	log_printf(TRACE,Commit_unit,FUNCTION," %.1d %.2d %.6d, %.1d %.2d %.6d, %.1d %.1d %.6d, %.1d %.2d %.6d %.6d, %.1d %.1d %.6d %.6d ",
716	(*it)->read_ra ,
717	(*it)->num_reg_ra_log ,
718	(*it)->num_reg_ra_phy ,
719	(*it)->read_rb ,
720	(*it)->num_reg_rb_log ,
721	(*it)->num_reg_rb_phy ,
722	(*it)->read_rc ,
723	(*it)->num_reg_rc_log ,
724	(*it)->num_reg_rc_phy ,
725	(*it)->write_rd ,
726	(*it)->num_reg_rd_log ,
727	(*it)->num_reg_rd_phy_old ,
728	(*it)->num_reg_rd_phy_new ,
729	(*it)->write_re ,
730	(*it)->num_reg_re_log ,
731	(*it)->num_reg_re_phy_old ,
732	(*it)->num_reg_re_phy_new );
733
734	log_printf(TRACE,Commit_unit,FUNCTION," %.2d %.2d %.1d %.1d %.1d - %.8x (%.8x) %.8x (%.8x)",
735	(*it)->exception_use ,
736	(*it)->exception ,
737	(*it)->flags ,
738	(*it)->no_sequence ,
739	(*it)->speculative ,
740	(*it)->address ,
741	(*it)->address<<2 ,
742	(*it)->address_next ,
743	(*it)->address_next<<2
744	);
745	}
746	}
747	}
748	#endif
749
750	#ifdef DEBUG_TEST
751	{
752	uint32_t x=reg_NUM_BANK_HEAD;
753	if (not _rob[x].empty())
754	{
755	entry_t * entry = _rob [x].front();
756
757	if (false
758	// or (entry->state == ROB_EMPTY )
759	// or (entry->state == ROB_BRANCH_WAIT_END )
760	// or (entry->state == ROB_BRANCH_COMPLETE )
761	// or (entry->state == ROB_STORE_WAIT_HEAD_OK )
762	// //or (entry->state == ROB_STORE_WAIT_HEAD_KO )
763	// or (entry->state == ROB_STORE_HEAD_OK )
764	// or (entry->state == ROB_STORE_HEAD_KO )
765	// or (entry->state == ROB_OTHER_WAIT_END )
766	// or (entry->state == ROB_MISS_WAIT_END )
767	// or (entry->state == ROB_END_OK_SPECULATIVE )
768	or (entry->state == ROB_END_OK )
769	// or (entry->state == ROB_END_KO_SPECULATIVE )
770	// or (entry->state == ROB_END_KO )
771	// or (entry->state == ROB_END_BRANCH_MISS_SPECULATIVE)
772	or (entry->state == ROB_END_BRANCH_MISS )
773	// or (entry->state == ROB_END_LOAD_MISS_SPECULATIVE )
774	// or (entry->state == ROB_END_LOAD_MISS_UPDATE )
775	or (entry->state == ROB_END_LOAD_MISS )
776	// or (entry->state == ROB_END_MISS )
777	// or (entry->state == ROB_END_EXCEPTION_WAIT_HEAD )
778	// or (entry->state == ROB_END_EXCEPTION_UPDATE )
779	// or (entry->state == ROB_END_EXCEPTION )
780	)
781	if (entry->address != reg_PC_CURRENT[entry->front_end_id][entry->context_id])
782	throw ERRORMORPHEO(FUNCTION,toString(_("Rob top address (%x) is different of reg_PC_CURRENT[%d][%d] (%x).\n"),
783	entry->address,
784	entry->front_end_id,
785	entry->context_id,
786	reg_PC_CURRENT[entry->front_end_id][entry->context_id]));
787	}
788	}
789	#endif
790
791	#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
792	end_cycle ();
793	#endif
794
795	// Stop Condition
796	for (uint32_t i=0; i<_param->_nb_front_end; i++)
797	for (uint32_t j=0; j<_param->_nb_context [i]; j++)
798	if (_nb_cycle_idle [i][j] >= debug_idle_cycle)
799	throw ERRORMORPHEO(FUNCTION,toString(_("Thread [%d] is idle since %.0f cycles.\n"),_param->_translate_num_context_to_num_thread[i][j],_nb_cycle_idle [i][j]));
800
801	log_end(Commit_unit,FUNCTION);
802	};
803
804	}; // end namespace commit_unit
805	}; // end namespace ooo_engine
806	}; // end namespace multi_ooo_engine
807	}; // end namespace core
808
809	}; // end namespace behavioural
810	}; // end namespace morpheo
811	#endif

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