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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp @ 141

Last change on this file since 141 was 141, checked in by rosiere, 14 years ago
Add statistics in stage IFETCH, DECODE and COMMIT (insert, retire and commit)
Property svn:keywords set to `Id`
File size: 79.6 KB

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1	#ifdef SYSTEMC
2	/*
3	* $Id: Commit_unit_transition.cpp 141 2010-08-02 18:56:05Z rosiere $
4	*
5	* [ Description ]
6	*
7	*/
8
9	#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h"
10	#include "Behavioural/include/Simulation.h"
11
12	namespace morpheo {
13	namespace behavioural {
14	namespace core {
15	namespace multi_ooo_engine {
16	namespace ooo_engine {
17	namespace commit_unit {
18
19	#undef FUNCTION
20	#define FUNCTION "Commit_unit::transition"
21	void Commit_unit::transition (void)
22	{
23	log_begin(Commit_unit,FUNCTION);
24	log_function(Commit_unit,FUNCTION,_name.c_str());
25
26	if (PORT_READ(in_NRESET) == 0)
27	{
28	// Clear all bank
29	for (uint32_t i=0; i<_param->_nb_bank; ++i)
30	{
31	while(not _rob[i].empty())
32	{
33	delete _rob[i].front();
34	_rob[i].pop_front();
35	}
36	reg_BANK_PTR [i] = 0;
37	}
38
39	// Reset pointer
40	reg_NUM_BANK_HEAD = 0;
41	reg_NUM_BANK_TAIL = 0;
42	reg_NUM_PTR_TAIL = 0;
43
44	// Reset counter
45	for (uint32_t i=0; i<_param->_nb_front_end; i++)
46	for (uint32_t j=0; j<_param->_nb_context [i]; j++)
47	{
48	_nb_cycle_idle [i][j] = 0;
49
50	reg_NB_INST_COMMIT_ALL [i][j] = 0;
51	reg_NB_INST_COMMIT_MEM [i][j] = 0;
52
53	reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_NO_EVENT;
54	// reg_EVENT_FLUSH [i][j] = false;
55	// reg_EVENT_STOP [i][j] = false;
56	// reg_EVENT_NUM_BANK [i][j] = 0; // not necessary
57	// reg_EVENT_NUM_PTR [i][j] = 0; // not necessary
58	// reg_EVENT_CAN_RESTART [i][j] = 0; // not necessary
59	reg_EVENT_PACKET [i][j] = 0; // not necessary
60	reg_EVENT_DEPTH [i][j] = 0; // not necessary
61	reg_EVENT_NB_INST [i][j] = 0;
62	reg_EVENT_LAST [i][j] = false;
63	reg_EVENT_LAST_NUM_BANK [i][j] = 0; // not necessary
64	reg_EVENT_LAST_NUM_PTR [i][j] = 0; // not necessary
65
66	reg_EVENT_NEXT_STOP [i][j] = false;
67	reg_EVENT_NEXT_PACKET [i][j] = 0; // not necessary
68
69	// reg_PC_PREVIOUS [i][j] = (0x100-4)>>2;
70	reg_PC_CURRENT [i][j] = (0x100 )>>2;
71	reg_PC_CURRENT_IS_DS [i][j] = 0;
72	reg_PC_CURRENT_IS_DS_TAKE [i][j] = 0;
73	reg_PC_NEXT [i][j] = (0x100+4)>>2;
74	}
75
76	// Resert RAT_UPDATE_TABLE
77	for (uint32_t i=0; i<_param->_nb_front_end; i++)
78	for (uint32_t j=0; j<_param->_nb_context[i]; j++)
79	{
80	for (uint32_t k=0; k<_param->_nb_general_register_logic; k++)
81	rat_gpr_update_table [i][j][k] = false; // not necessary
82	for (uint32_t k=0; k<_param->_nb_special_register_logic; k++)
83	rat_spr_update_table [i][j][k] = false; // not necessary
84	}
85
86	// Reset priority algorithm
87	_priority_insert->reset();
88	}
89	else
90	{
91	#ifdef STATISTICS
92	uint32_t stat_nb_inst_insert [_param->_nb_rename_unit];
93	uint32_t stat_nb_inst_retire [_param->_nb_rename_unit];
94	uint32_t stat_nb_inst_commit [_param->_nb_rename_unit];
95
96	if (usage_is_set(_usage,USE_STATISTICS))
97	for (uint32_t i=0; i<_param->_nb_rename_unit; ++i)
98	{
99	stat_nb_inst_insert [i] = 0;
100	stat_nb_inst_retire [i] = 0;
101	stat_nb_inst_commit [i] = 0;
102	}
103	#endif
104
105	// Increase number idle cycle
106	for (uint32_t i=0; i<_param->_nb_front_end; i++)
107	for (uint32_t j=0; j<_param->_nb_context [i]; j++)
108	_nb_cycle_idle [i][j] ++;
109
110	// Compute next priority
111	_priority_insert->transition();
112
113	// ===================================================================
114	// =====[ GARBAGE COLLECTOR ]=========================================
115	// ===================================================================
116	for (uint32_t i=0; i<_param->_nb_front_end; i++)
117	for (uint32_t j=0; j<_param->_nb_context [i]; j++)
118	{
119	// Test if can_restart : (can_restart is to signal at the state than the decod_queue is empty)
120	// * no previous can_restart (trap for one)
121	// * and decod_queue is empty
122	// * and have an event or have a futur event
123	// if (not reg_EVENT_CAN_RESTART [i][j] and
124	// (PORT_READ(in_NB_INST_DECOD_ALL [i][j]) == 0) and
125	// (reg_EVENT_STOP [i][j] or (reg_EVENT_STATE [i][j] != COMMIT_EVENT_STATE_NO_EVENT)))
126	// reg_EVENT_CAN_RESTART [i][j] = true;
127
128	// Test event state
129	switch (reg_EVENT_STATE [i][j])
130	{
131	case COMMIT_EVENT_STATE_EVENT :
132	{
133	// Have an event, test if all composant have ack
134	if (internal_RETIRE_EVENT_VAL [i][j] and in_RETIRE_EVENT_ACK [i][j])
135	{
136	// A minor optimisation : test if wait_decod is previously empty.
137	// if (not reg_EVENT_CAN_RESTART [i][j])
138	// reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_WAIT_DECOD;
139	// else
140	reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_WAIT_END;
141
142	// Reset update_table
143	for (uint32_t k=0; k<_param->_nb_general_register_logic; k++)
144	rat_gpr_update_table [i][j][k] = false;
145	for (uint32_t k=0; k<_param->_nb_special_register_logic; k++)
146	rat_spr_update_table [i][j][k] = false;
147	}
148
149	break;
150	}
151	// case COMMIT_EVENT_STATE_WAIT_DECOD :
152	// {
153	// // Wait flush of decod_queue.
154	// // Test if can restart now
155	// if (reg_EVENT_CAN_RESTART [i][j])
156	// {
157	// //reg_EVENT_FLUSH [i][j] = false;
158
159	// // A minor optimisation : test if the last element is already retire
160	// if (not reg_EVENT_LAST [i][j])
161	// reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_WAIT_END;
162	// else
163	// reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_END;
164	// }
165	// break;
166	// }
167
168	// case COMMIT_EVENT_STATE_WAIT_END :
169	// {
170	// // Wait the flush of Re Order Buffer.
171	// // Test if the last element is retire
172	// if (reg_EVENT_LAST [i][j])
173	// reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_END ;
174
175	// break;
176	// }
177	// case COMMIT_EVENT_STATE_END :
178	// {
179	// // Just one cycle
180
181	// // flush of re order buffer is finish
182	// reg_EVENT_LAST [i][j] = false;
183
184	// if (not reg_EVENT_NEXT_STOP [i][j])
185	// reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_NO_EVENT;
186	// else
187	// {
188	// reg_EVENT_NEXT_STOP [i][j] = false;
189	// reg_EVENT_PACKET [i][j] = reg_EVENT_NEXT_PACKET [i][j];
190	// reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_NOT_YET_EVENT;
191	// // reg_EVENT_STOP [i][j] = true;
192	// reg_EVENT_LAST_NUM_BANK [i][j] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1;
193	// reg_EVENT_LAST_NUM_PTR [i][j] = reg_NUM_PTR_TAIL;
194	// }
195
196	// break;
197	// }
198
199
200	case COMMIT_EVENT_STATE_WAIT_END :
201	{
202	// Wait the flush of Re Order Buffer.
203	// Test if the last element is retire
204	if (reg_EVENT_LAST [i][j])
205	{
206	// flush of re order buffer is finish
207	reg_EVENT_LAST [i][j] = false;
208
209	if (not reg_EVENT_NEXT_STOP [i][j])
210	reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_NO_EVENT;
211	else
212	{
213	uint32_t next_packet = reg_EVENT_NEXT_PACKET [i][j];
214
215	reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_NOT_YET_EVENT;
216
217	reg_EVENT_NEXT_STOP [i][j] = false;
218	reg_EVENT_PACKET [i][j] = next_packet;
219	// reg_EVENT_DEPTH [i][j] = _rob[next_packet].depth;
220	reg_EVENT_NB_INST [i][j] = reg_NB_INST_COMMIT_ALL [i][j];
221	//reg_EVENT_STOP [i][j] = true;
222	reg_EVENT_LAST_NUM_BANK [i][j] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1;
223	reg_EVENT_LAST_NUM_PTR [i][j] = reg_NUM_PTR_TAIL;
224	}
225	}
226	break;
227	}
228
229	//case COMMIT_EVENT_STATE_NO_EVENT :
230	//case COMMIT_EVENT_STATE_NOT_YET_EVENT :
231	default : break;
232	}
233	}
234
235	// ===================================================================
236	// =====[ INSERT ]====================================================
237	// ===================================================================
238	{
239	// for (uint32_t i=0; i<_param->_nb_rename_unit; i++)
240	// for (uint32_t j=0; j<_param->_nb_inst_insert[i]; j++)
241	// log_printf(TRACE,Commit_unit,FUNCTION," * INSERT_VAL [%d][%d] : %d",i,j,PORT_READ(in_INSERT_VAL [i][j]));
242
243	// variable to count instruction insert
244	uint32_t nb_insert = 0;
245
246	for (uint32_t i=0; i<_param->_nb_bank; i++)
247	{
248	// compute first bank number
249	uint32_t num_bank = (reg_NUM_BANK_TAIL+i)%_param->_nb_bank;
250
251	if (internal_BANK_INSERT_VAL [num_bank])
252	{
253	// get rename unit source and instruction.
254	uint32_t x = internal_BANK_INSERT_NUM_RENAME_UNIT [num_bank];
255	uint32_t y = internal_BANK_INSERT_NUM_INST [num_bank];
256
257	// Test if an instruction is valid
258	// (all in_order insert combinatory is in rename_unit )
259	if (PORT_READ(in_INSERT_VAL [x][y]))
260	{
261	log_printf(TRACE,Commit_unit,FUNCTION," * INSERT [%d][%d]",x,y);
262
263	// get information
264	Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_INSERT_FRONT_END_ID [x][y]):0;
265	Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_INSERT_CONTEXT_ID [x][y]):0;
266	Ttype_t type = PORT_READ(in_INSERT_TYPE [x][y]);
267	Toperation_t operation = PORT_READ(in_INSERT_OPERATION [x][y]);
268	bool is_store = is_operation_memory_store(operation);
269
270	Texception_t exception = PORT_READ(in_INSERT_EXCEPTION [x][y]);
271	Tcontrol_t no_execute = PORT_READ(in_INSERT_NO_EXECUTE [x][y]);
272
273	log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id);
274	log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id);
275	log_printf(TRACE,Commit_unit,FUNCTION," * type : %s",toString(type).c_str());
276	log_printf(TRACE,Commit_unit,FUNCTION," * operation : %d",operation );
277	log_printf(TRACE,Commit_unit,FUNCTION," * exception : %d",exception );
278
279	// Create new entry and write information
280	entry_t * entry = new entry_t;
281	uint32_t ptr = reg_BANK_PTR [num_bank];
282
283	entry->ptr = ptr;
284	entry->front_end_id = front_end_id;
285	entry->context_id = context_id ;
286	entry->rename_unit_id = x;
287	entry->depth = (_param->_have_port_depth)?PORT_READ(in_INSERT_DEPTH [x][y]):0;
288	#ifdef STATISTICS
289	entry->instruction = PORT_READ(in_INSERT_INSTRUCTION [x][y]);
290	#endif
291	entry->type = type;
292	entry->operation = operation;
293	entry->is_delay_slot = PORT_READ(in_INSERT_IS_DELAY_SLOT [x][y]);
294	// entry->address = PORT_READ(in_INSERT_ADDRESS [x][y]);
295	entry->exception = exception;
296	entry->exception_use = PORT_READ(in_INSERT_EXCEPTION_USE [x][y]);
297	entry->use_store_queue = (type == TYPE_MEMORY) and ( is_store) and (not no_execute);
298	entry->use_load_queue = (type == TYPE_MEMORY) and (not is_store) and (not no_execute);
299	entry->store_queue_ptr_write = PORT_READ(in_INSERT_STORE_QUEUE_PTR_WRITE [x][y]);
300	entry->load_queue_ptr_write = (_param->_have_port_load_queue_ptr)?PORT_READ(in_INSERT_LOAD_QUEUE_PTR_WRITE [x][y]):0;
301	#ifdef DEBUG
302	entry->read_ra = PORT_READ(in_INSERT_READ_RA [x][y]);
303	entry->num_reg_ra_log = PORT_READ(in_INSERT_NUM_REG_RA_LOG [x][y]);
304	entry->num_reg_ra_phy = PORT_READ(in_INSERT_NUM_REG_RA_PHY [x][y]);
305	#endif
306	entry->read_rb = PORT_READ(in_INSERT_READ_RB [x][y]);
307	#ifdef DEBUG
308	entry->num_reg_rb_log = PORT_READ(in_INSERT_NUM_REG_RB_LOG [x][y]);
309	entry->num_reg_rb_phy = PORT_READ(in_INSERT_NUM_REG_RB_PHY [x][y]);
310	entry->read_rc = PORT_READ(in_INSERT_READ_RC [x][y]);
311	entry->num_reg_rc_log = PORT_READ(in_INSERT_NUM_REG_RC_LOG [x][y]);
312	entry->num_reg_rc_phy = PORT_READ(in_INSERT_NUM_REG_RC_PHY [x][y]);
313	#endif
314	entry->write_rd = PORT_READ(in_INSERT_WRITE_RD [x][y]);
315	entry->num_reg_rd_log = PORT_READ(in_INSERT_NUM_REG_RD_LOG [x][y]);
316	entry->num_reg_rd_phy_old = PORT_READ(in_INSERT_NUM_REG_RD_PHY_OLD [x][y]);
317	entry->num_reg_rd_phy_new = PORT_READ(in_INSERT_NUM_REG_RD_PHY_NEW [x][y]);
318	entry->write_re = PORT_READ(in_INSERT_WRITE_RE [x][y]);
319	entry->num_reg_re_log = PORT_READ(in_INSERT_NUM_REG_RE_LOG [x][y]);
320	entry->num_reg_re_phy_old = PORT_READ(in_INSERT_NUM_REG_RE_PHY_OLD [x][y]);
321	entry->num_reg_re_phy_new = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [x][y]);
322
323	entry->flags = 0; // not necessary
324	entry->no_sequence = type == TYPE_BRANCH;
325	// entry->speculative = true;
326	#ifdef DEBUG
327	entry->address = PORT_READ(in_INSERT_ADDRESS [x][y]);
328	#endif
329	entry->address_next = PORT_READ(in_INSERT_ADDRESS_NEXT [x][y]);
330	#ifdef DEBUG
331	entry->cycle_rob_in = simulation_cycle();
332	entry->cycle_commit = simulation_cycle();
333	#endif
334
335	// Test if exception :
336	// * yes : no execute instruction, wait ROB Head
337	// * no : test if no_execute (== instruction is flushed)
338	// else test type
339	// * BRANCH : l.j -> branch is ended
340	// other -> wait the execution end of branchment
341	// * MEMORY : store -> wait store is at head of ROB
342	// other -> wait end of instruction
343	// * OTHER
344
345	{
346	if (exception == EXCEPTION_NONE)
347	{
348	// no_execute : l.j, l.nop, l.rfe
349
350	log_printf(TRACE,Commit_unit,FUNCTION," * no_execute : %d",no_execute);
351
352	switch (type)
353	{
354	case TYPE_BRANCH : {entry->state=(no_execute==1)?ROB_BRANCH_COMPLETE:ROB_BRANCH_WAIT_END ; break;}
355	case TYPE_MEMORY : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:(entry->state=(is_store ==1)?ROB_STORE_WAIT_END_OK:ROB_OTHER_WAIT_END); break;}
356	default : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:ROB_OTHER_WAIT_END; break;}
357	}
358	}
359	else
360	{
361	// Have an exception : wait head of ROB
362	// in_INSERT_NO_EXECUTE [x][y] : l.sys, l.trap
363
364	entry->state = ROB_END_EXCEPTION_WAIT_HEAD;
365	}
366	}
367
368	#ifdef STATISTICS
369	if (usage_is_set(_usage,USE_STATISTICS))
370	stat_nb_inst_insert [x] ++;
371	#endif
372
373	// Push entry in rob
374	_rob[num_bank].push_back(entry);
375
376	// Update counter and pointer
377	reg_NB_INST_COMMIT_ALL [front_end_id][context_id] ++;
378	if (type == TYPE_MEMORY)
379	reg_NB_INST_COMMIT_MEM [front_end_id][context_id] ++;
380
381
382	// flush = present event or future event.
383	// * present event = don't can restart
384
385	// bool flush = reg_EVENT_FLUSH [front_end_id][context_id];
386
387	// bool flush = (((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_EVENT) or
388	// (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_DECOD)) or
389	// (reg_EVENT_STOP [front_end_id][context_id]));
390
391	// New instruction from decod_queue. Flush if :
392	// * future event (instruction don't need execute because they are a previous event (miss load/branch or exception))
393	// * or present_event
394	// * and not can_restart (previous empty decod queue), because between the event_stop (branch_complete) and the state event (miss in head), many cycle is occured.
395	// bool flush = ((// present event
396	// ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_EVENT) or
397	// (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_DECOD)
398	// ) or
399	// futur event
400	// reg_EVENT_STOP [front_end_id][context_id])
401	// // can't restart
402	// and not reg_EVENT_CAN_RESTART[front_end_id][context_id]
403	// );
404
405	// if (flush)
406	// {
407	// // A new invalid instruction is push in rob -> new last instruction
408	// reg_EVENT_LAST [front_end_id][context_id] = false;
409	// reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] = num_bank;
410	// reg_EVENT_LAST_NUM_PTR [front_end_id][context_id] = ptr;
411	// }
412
413	// Update pointer
414	reg_NUM_PTR_TAIL = ptr;
415	reg_BANK_PTR [num_bank] = (reg_BANK_PTR [num_bank]+1)%_param->_size_bank;
416	nb_insert ++;
417	}
418	}
419	}
420	// Update pointer
421	reg_NUM_BANK_TAIL = (reg_NUM_BANK_TAIL+nb_insert)%_param->_nb_bank;
422	}
423
424	// ===================================================================
425	// =====[ COMMIT ]====================================================
426	// ===================================================================
427
428	#ifdef STATISTICS
429	if (usage_is_set(_usage,USE_STATISTICS))
430	(*_stat_nb_inst_commit_conflit_access) += internal_BANK_COMMIT_CONFLIT_ACCESS;
431	#endif
432
433	// For each commit instruction ...
434	for (uint32_t i=0; i<_param->_nb_bank; i++)
435	for (uint32_t j=0; j<_param->_nb_bank_access_commit; j++)
436	// ... test if an instruction have finish this execution
437	if (internal_BANK_COMMIT_VAL [i][j])
438	{
439	// An instruction is executed -> Change state of this instruction
440
441	// Get information
442	uint32_t x = internal_BANK_COMMIT_NUM_INST [i][j];
443
444	// Test if instruction is valid and is enable
445	// (can be disable if this instruction is reexecute)
446	if (PORT_READ(in_COMMIT_VAL [x]) and PORT_READ(in_COMMIT_WEN [x]))
447	{
448	log_printf(TRACE,Commit_unit,FUNCTION," * COMMIT [%d]",x);
449	log_printf(TRACE,Commit_unit,FUNCTION," * num_bank : %d",i);
450
451	// find the good entry !!!
452	entry_t * entry = internal_BANK_COMMIT_ENTRY [i][j];
453
454	#ifdef STATISTICS
455	if (usage_is_set(_usage,USE_STATISTICS))
456	stat_nb_inst_commit [entry->rename_unit_id] ++;
457	#endif
458
459	log_printf(TRACE,Commit_unit,FUNCTION," * ptr : %d",entry->ptr);
460
461	//Toperation_t operation = PORT_READ(in_COMMIT_OPERATION [x]);
462	Ttype_t type = entry->type;
463	Tcontrol_t no_sequence = PORT_READ(in_COMMIT_NO_SEQUENCE [x]);
464	// Tcontrol_t cancel = PORT_READ(in_COMMIT_CANCEL [x]);
465
466	#if 0
467	if ((type == TYPE_MEMORY) and no_sequence)
468	continue;
469	#endif
470
471	Texception_t exception = PORT_READ(in_COMMIT_EXCEPTION [x]);
472
473	rob_state_t state = entry->state;
474	Tcontext_t front_end_id = entry->front_end_id;
475	Tcontext_t context_id = entry->context_id;
476
477	// change state : test exception_use
478
479	bool have_exception = false;
480	bool have_miss_speculation = false;
481
482	// Test if have an exception ...
483	if (exception != EXCEPTION_NONE)
484	{
485	// Test if the instruction is a load and is a miss speculation
486	// (load is commit, but they have an dependence with a previous store -> need restart pipeline)
487
488	have_miss_speculation = (exception == EXCEPTION_MEMORY_MISS_SPECULATION);
489
490	// * Test if the exception generated can be trap by this exception
491	switch (entry->exception_use)
492	{
493	// Have overflow exception if bit overflow enable is set.
494	case EXCEPTION_USE_RANGE : {have_exception = ((exception == EXCEPTION_RANGE) and PORT_READ(in_SPR_READ_SR_OVE[front_end_id][context_id])); break;}
495	case EXCEPTION_USE_MEMORY_WITH_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or
496	(exception == EXCEPTION_DATA_TLB ) or
497	(exception == EXCEPTION_DATA_PAGE) or
498	(exception == EXCEPTION_ALIGNMENT)); break;};
499	case EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or
500	(exception == EXCEPTION_DATA_TLB ) or
501	(exception == EXCEPTION_DATA_PAGE)); break;};
502	case EXCEPTION_USE_CUSTOM_0 : {have_exception = (exception == EXCEPTION_CUSTOM_0); break;};
503	case EXCEPTION_USE_CUSTOM_1 : {have_exception = (exception == EXCEPTION_CUSTOM_1); break;};
504	case EXCEPTION_USE_CUSTOM_2 : {have_exception = (exception == EXCEPTION_CUSTOM_2); break;};
505	case EXCEPTION_USE_CUSTOM_3 : {have_exception = (exception == EXCEPTION_CUSTOM_3); break;};
506	case EXCEPTION_USE_CUSTOM_4 : {have_exception = (exception == EXCEPTION_CUSTOM_4); break;};
507	case EXCEPTION_USE_CUSTOM_5 : {have_exception = (exception == EXCEPTION_CUSTOM_5); break;};
508	case EXCEPTION_USE_CUSTOM_6 : {have_exception = (exception == EXCEPTION_CUSTOM_6); break;};
509	// Case already manage (decod stage -> in insert in ROB)
510	case EXCEPTION_USE_TRAP : {have_exception = false; exception = EXCEPTION_NONE; break;};
511	case EXCEPTION_USE_NONE : {have_exception = false; exception = EXCEPTION_NONE; break;};
512	case EXCEPTION_USE_ILLEGAL_INSTRUCTION : {have_exception = false; exception = EXCEPTION_NONE; break;};
513	case EXCEPTION_USE_SYSCALL : {have_exception = false; exception = EXCEPTION_NONE; break;};
514	default :
515	{
516	throw ERRORMORPHEO(FUNCTION,_("Commit : invalid exception_use.\n"));
517	break;
518	}
519	}
520	}
521
522	log_printf(TRACE,Commit_unit,FUNCTION," * have_exception : %d",have_exception );
523	log_printf(TRACE,Commit_unit,FUNCTION," * have_miss_speculation : %d",have_miss_speculation);
524
525
526	// Next state depends of previous state
527	switch (state)
528	{
529	// Branch : if no exception, the branchement can be completed
530	case ROB_BRANCH_WAIT_END :
531	{
532	if (not have_exception)
533	state = ROB_BRANCH_COMPLETE;
534	else
535	state = ROB_END_EXCEPTION_WAIT_HEAD;
536	break;
537	}
538	// Previous event -> set state as execute
539	case ROB_STORE_KO_WAIT_END :
540	case ROB_EVENT_WAIT_END :
541	{
542	state = ROB_END_KO_SPECULATIVE;
543	break;
544	}
545	// No previous event - Load and other instruction
546	case ROB_STORE_OK_WAIT_END :
547	case ROB_OTHER_WAIT_END :
548	{
549	if (not have_exception)
550	{
551	if (not have_miss_speculation)
552	state = ROB_END_OK_SPECULATIVE;
553	else
554	state = ROB_END_LOAD_MISS_SPECULATIVE;
555	}
556	else
557	state = ROB_END_EXCEPTION_WAIT_HEAD;
558	break;
559	}
560	case ROB_STORE_WAIT_END_OK :
561	{
562	if (not have_exception)
563	state = ROB_STORE_OK;
564	else
565	state = ROB_STORE_EVENT;
566	break;
567	}
568	case ROB_STORE_WAIT_END_KO :
569	{
570	// if (not have_exception)
571	state = ROB_STORE_KO;
572	// else
573	// state = ROB_END_EXCEPTION_WAIT_HEAD;
574	break;
575	}
576
577
578	default :
579	{
580	throw ERRORMORPHEO(FUNCTION,toString(_("Commit [%d] : Bank [%d][%d], invalid state value (%s).\n"),x,i,j,toString(state).c_str()));
581	break;
582	}
583	}
584
585	// Commit an instruction ...
586	// Test if have an event (miss_speculation or exception)
587
588	if (have_exception or have_miss_speculation)
589	{
590	// Two case :
591	// if no previous manage event -> generate an event
592	// if previous manage event -> next generate an event
593
594	// bool flush = reg_EVENT_FLUSH [front_end_id][context_id];
595	bool flush = ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_EVENT) or
596	// (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_DECOD) or
597	(reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_END)// or
598	// (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_END)
599	);
600
601	uint32_t packet = ((entry->ptr << _param->_shift_num_slot) \| i);
602	uint32_t _top = ((_rob[ reg_NUM_BANK_HEAD].front()->ptr << _param->_shift_num_slot) \| reg_NUM_BANK_HEAD);
603
604	log_printf(TRACE,Commit_unit,FUNCTION," * flush : %d",flush);
605	log_printf(TRACE,Commit_unit,FUNCTION," * packet : %d",packet);
606
607	if (not flush)
608	{
609	bool can = true;
610	// test have a previous event detected (event_stop = 1)
611	// if yes, test if the actual event if "before (in order)" that the previous event
612	if (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_NOT_YET_EVENT)
613	{
614	// Compare packet_id (by construction instruction is insert in order by increase packet_id)
615
616	uint32_t _old = reg_EVENT_PACKET [front_end_id][context_id];
617	uint32_t _new = packet;
618	if (_old < _top) _old = _old+_param->_size_queue;
619	if (_new < _top) _new = _new+_param->_size_queue;
620	if (_new < _old) reg_EVENT_PACKET [front_end_id][context_id] = packet;
621	else can = false;
622	}
623	else
624	reg_EVENT_PACKET [front_end_id][context_id] = packet;
625
626	if (can)
627	{
628	// have an error, stop issue instruction
629	reg_EVENT_STATE [front_end_id][context_id] = COMMIT_EVENT_STATE_NOT_YET_EVENT;
630
631	// reg_EVENT_DEPTH [front_end_id][context_id] = _rob[packet].depth;
632	reg_EVENT_NB_INST [front_end_id][context_id] = reg_NB_INST_COMMIT_ALL [front_end_id][context_id];
633
634	//reg_EVENT_STOP [front_end_id][context_id] = true;
635
636	reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1;
637	reg_EVENT_LAST_NUM_PTR [front_end_id][context_id] = reg_NUM_PTR_TAIL;
638	}
639	}
640	else
641	{
642	bool find = true;
643
644	log_printf(TRACE,Commit_unit,FUNCTION," * reg_EVENT_NEXT_STOP : %d",reg_EVENT_NEXT_STOP [front_end_id][context_id]);
645	log_printf(TRACE,Commit_unit,FUNCTION," * reg_EVENT_NEXT_PACKET : %d",reg_EVENT_NEXT_PACKET[front_end_id][context_id]);
646
647	// already manage an event.
648	if (reg_EVENT_NEXT_STOP [front_end_id][context_id])
649	{
650	// after last ?
651	uint32_t _old = reg_EVENT_NEXT_PACKET [front_end_id][context_id];
652	uint32_t _new = packet;
653
654	log_printf(TRACE,Commit_unit,FUNCTION," * _top : %d",_top );
655	log_printf(TRACE,Commit_unit,FUNCTION," * _old (before) : %d",_old );
656	log_printf(TRACE,Commit_unit,FUNCTION," * _new (before) : %d",_new );
657
658	if (_old < _top) _old = _old+_param->_size_queue;
659	if (_new < _top) _new = _new+_param->_size_queue;
660	if (_new > _old) reg_EVENT_NEXT_PACKET [front_end_id][context_id] = packet;
661	else find = false;
662
663	log_printf(TRACE,Commit_unit,FUNCTION," * _old (after) : %d",_old );
664	log_printf(TRACE,Commit_unit,FUNCTION," * _new (after) : %d",_new );
665	}
666	else
667	{
668	// after last ?
669	uint32_t _old = ((reg_EVENT_LAST_NUM_PTR [front_end_id][context_id] << _param->_shift_num_slot) \| reg_EVENT_LAST_NUM_BANK [front_end_id][context_id]);
670	uint32_t _new = packet;
671
672	log_printf(TRACE,Commit_unit,FUNCTION," * _top : %d",_top );
673	log_printf(TRACE,Commit_unit,FUNCTION," * _old (before) : %d",_old );
674	log_printf(TRACE,Commit_unit,FUNCTION," * _new (before) : %d",_new );
675
676	if (_old < _top) _old = _old+_param->_size_queue;
677	if (_new < _top) _new = _new+_param->_size_queue;
678	if (_new > _old) reg_EVENT_NEXT_PACKET [front_end_id][context_id] = packet;
679	else find = false;
680
681	log_printf(TRACE,Commit_unit,FUNCTION," * _old (after) : %d",_old );
682	log_printf(TRACE,Commit_unit,FUNCTION," * _new (after) : %d",_new );
683	}
684
685	log_printf(TRACE,Commit_unit,FUNCTION," * find : %d",find);
686
687	if (find)
688	reg_EVENT_NEXT_STOP [front_end_id][context_id] = true; // in all case : need stop
689	}
690	}
691
692	// Update Re Order Buffer
693	entry->state = state;
694	entry->exception = exception;
695	entry->flags = PORT_READ(in_COMMIT_FLAGS [x]);
696	entry->no_sequence = no_sequence;
697	// jalr, jr : address_dest is in register
698	if (( type == TYPE_BRANCH) and
699	(entry->operation == OPERATION_BRANCH_L_JALR) and
700	(entry->read_rb))
701	entry->address_next = PORT_READ(in_COMMIT_ADDRESS [x]);
702
703	#ifdef DEBUG
704	entry->load_data = PORT_READ(in_COMMIT_ADDRESS [x]);
705	entry->cycle_commit = simulation_cycle();
706	#endif
707	}
708	}
709
710	// ===================================================================
711	// =====[ RETIRE ]====================================================
712	// ===================================================================
713	for (uint32_t i=0; i<_param->_nb_bank; i++)
714	{
715	// Compute bank number
716	uint32_t num_bank = (internal_BANK_RETIRE_HEAD+i)%_param->_nb_bank;
717
718	// Test if have an request
719	if (internal_BANK_RETIRE_VAL [num_bank])
720	{
721	// Take num instruction
722	uint32_t x = internal_BANK_RETIRE_NUM_RENAME_UNIT [num_bank];
723	uint32_t y = internal_BANK_RETIRE_NUM_INST [num_bank];
724
725	log_printf(TRACE,Commit_unit,FUNCTION," * RETIRE [%d][%d]",x,y);
726	log_printf(TRACE,Commit_unit,FUNCTION," * num_bank : %d",num_bank );
727
728	#ifdef DEBUG_TEST
729	if (not PORT_READ(in_RETIRE_ACK [x][y]))
730	throw ERRORMORPHEO(FUNCTION,_("Retire : retire_ack must be set.\n"));
731	#endif
732
733	#ifdef STATISTICS
734	if (usage_is_set(_usage,USE_STATISTICS))
735	stat_nb_inst_retire [x] ++;
736	#endif
737
738	// Read information
739	entry_t * entry = _rob [num_bank].front();
740
741	entry->state_old = entry->state;
742	entry->state = ROB_END;
743
744
745	// Update RAT_UPDATE_TABLE
746	Tcontext_t front_end_id = entry->front_end_id;
747	Tcontext_t context_id = entry->context_id ;
748
749	if (entry->write_rd and internal_BANK_RETIRE_RESTORE_RD_PHY_OLD [num_bank])
750	rat_gpr_update_table [front_end_id][context_id][entry->num_reg_rd_log] = true;
751	if (entry->write_re and internal_BANK_RETIRE_RESTORE_RE_PHY_OLD [num_bank])
752	rat_spr_update_table [front_end_id][context_id][entry->num_reg_re_log] = true;
753	}
754	}
755
756	for (uint32_t i=0; i<_param->_nb_bank; i++)
757	{
758	// Compute bank number
759	bool can_continue = false;
760	uint32_t num_bank = reg_NUM_BANK_HEAD;
761
762	if (not _rob [num_bank].empty ())
763	{
764	entry_t * entry = _rob [num_bank].front();
765
766	if (entry->state == ROB_END)
767	{
768	log_printf(TRACE,Commit_unit,FUNCTION," * RETIRE_ROB [%d]",num_bank);
769
770	can_continue = true;
771
772	Tcontext_t front_end_id = entry->front_end_id;
773	Tcontext_t context_id = entry->context_id ;
774	uint32_t num_thread = _param->_translate_num_context_to_num_thread [front_end_id][context_id];
775	rob_state_t state = entry->state_old;
776	Ttype_t type = entry->type ;
777	bool retire_ok = false;
778	uint32_t packet_id = ((entry->ptr << _param->_shift_num_slot) \| num_bank);
779
780	log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id );
781	log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id );
782	log_printf(TRACE,Commit_unit,FUNCTION," * rob_ptr : %d",packet_id );
783	log_printf(TRACE,Commit_unit,FUNCTION," * num_thread : %d",num_thread );
784	log_printf(TRACE,Commit_unit,FUNCTION," * type : %s",toString(type).c_str());
785	log_printf(TRACE,Commit_unit,FUNCTION," * state : %s",toString(state).c_str());
786
787	// Test if the instruction is valid
788	// (BRANCH_MISS = instruction branch is valid, but have make an invalid prediction)
789	// (LOAD_MISS = instruction load is valid, but have make an invalid result)
790	if ((state == ROB_END_OK ) or
791	// (state == ROB_END_KO ) or
792	(state == ROB_END_BRANCH_MISS) or
793	(state == ROB_END_LOAD_MISS )// or
794	// (state == ROB_END_MISS ) or
795	// (state == ROB_END_EXCEPTION )
796	)
797	{
798	log_printf(TRACE,Commit_unit,FUNCTION," * retire_ok");
799
800	retire_ok = true;
801
802	// Update PC information
803	// reg_PC_PREVIOUS [front_end_id][context_id] = reg_PC_CURRENT [front_end_id][context_id];
804	reg_PC_CURRENT [front_end_id][context_id] = reg_PC_NEXT [front_end_id][context_id];
805	reg_PC_CURRENT_IS_DS [front_end_id][context_id] = type == TYPE_BRANCH;
806	reg_PC_CURRENT_IS_DS_TAKE [front_end_id][context_id] = entry->no_sequence;
807	reg_PC_NEXT [front_end_id][context_id] = (entry->no_sequence)?(entry->address_next):(reg_PC_CURRENT [front_end_id][context_id]+1);
808	}
809
810	// Test if have an event
811	if ((state == ROB_END_BRANCH_MISS) or
812	(state == ROB_END_LOAD_MISS))
813	{
814	reg_EVENT_STATE [front_end_id][context_id] = COMMIT_EVENT_STATE_EVENT;
815	reg_EVENT_TYPE [front_end_id][context_id] = rob_state_to_event_type(state);
816	// reg_EVENT_STOP [front_end_id][context_id] = false; // instruction flow can continue
817	reg_EVENT_LAST [front_end_id][context_id] = false;
818	// it the head !
819	reg_EVENT_PACKET [front_end_id][context_id] = packet_id;
820	reg_EVENT_DEPTH [front_end_id][context_id] = entry->depth;
821
822	// // If event is an load_miss, many instruction can be inserted.
823	// // -> new last instruction
824	// if (state == ROB_END_LOAD_MISS)
825	// {
826	// // reg_EVENT_CAN_RESTART [front_end_id][context_id] = false;
827
828	// reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1;
829	// reg_EVENT_LAST_NUM_PTR [front_end_id][context_id] = reg_NUM_PTR_TAIL;
830	// }
831	}
832
833	// Test if this instruction is the last instruction of an event
834	// * need event
835	// * packet id = last packet id
836	// for (uint32_t x=0; x<_param->_nb_front_end; x++)
837	// for (uint32_t y=0; y<_param->_nb_context [x]; y++)
838	// if (((reg_EVENT_STATE [x][y] != COMMIT_EVENT_STATE_NO_EVENT ) and
839	// (reg_EVENT_STATE [x][y] != COMMIT_EVENT_STATE_NOT_YET_EVENT)) and
840	// (reg_EVENT_LAST_NUM_BANK [x][y] == num_bank ) and
841	// (reg_EVENT_LAST_NUM_PTR [x][y] == entry->ptr ))
842	// reg_EVENT_LAST [x][y] = true;
843
844
845	if (reg_EVENT_NB_INST [front_end_id][context_id] > 0)
846	{
847	reg_EVENT_NB_INST [front_end_id][context_id] --;
848	if (reg_EVENT_NB_INST [front_end_id][context_id] == 0)
849	reg_EVENT_LAST [front_end_id][context_id] = true;
850	}
851
852	// Update nb_inst
853	reg_NB_INST_COMMIT_ALL [front_end_id][context_id] --;
854	if (type == TYPE_MEMORY)
855	reg_NB_INST_COMMIT_MEM [front_end_id][context_id] --;
856
857	// Update pointer
858	reg_NUM_BANK_HEAD = (num_bank+1)%_param->_nb_bank;
859
860	// Reset watch dog timer because have transaction on retire interface
861	_nb_cycle_idle [front_end_id][context_id] = 0;
862
863	// Increase stop condition
864	if (retire_ok)
865	_simulation_nb_instruction_commited [num_thread] ++;
866
867	#ifdef STATISTICS
868	if (usage_is_set(_usage,USE_STATISTICS))
869	{
870	if (retire_ok)
871	{
872	uint32_t instruction = entry->instruction;
873
874	(*_stat_nb_inst_retire_ok [num_thread] ) ++;
875	(*_stat_nb_inst_instruction [instruction]) ++;
876	(*_stat_nb_inst_type [type] ) ++;
877	}
878	else
879	(*_stat_nb_inst_retire_ko [num_thread]) ++;
880	}
881	#endif
882
883	#if defined(DEBUG) and defined(DEBUG_Commit_unit) and (DEBUG_Commit_unit == true)
884	if (log_file_generate)
885	{
886	// log file
887	instruction_log_file [num_thread]
888	<< "[" << simulation_cycle() << "] "
889	<< std::hex
890	<< (entry->address<<2) << " (" << (entry->address) << ") "
891	<< std::dec
892	<< "[" << entry->cycle_rob_in << ", " << entry->cycle_commit << "] "
893	<< "{" << ((retire_ok)?"OK":"KO") << "} ";
894
895	if ((type == TYPE_MEMORY) and is_operation_memory_load(entry->operation))
896	instruction_log_file [num_thread] << std::hex << entry->load_data << std::dec;
897
898	instruction_log_file [num_thread] << std::endl;
899	}
900	#endif
901
902	// Remove entry
903	delete entry;
904	_rob [num_bank].pop_front();
905	}
906	}
907
908	if (not can_continue)
909	break; // stop scan
910	}
911
912	// ===================================================================
913	// =====[ REEXECUTE ]=================================================
914	// ===================================================================
915	// Test if have an reexecute instruction (an store in head of rob)
916	for (uint32_t i=0; i<_param->_nb_inst_reexecute; ++i)
917	if (internal_REEXECUTE_VAL [i] and PORT_READ(in_REEXECUTE_ACK [i]))
918	{
919	log_printf(TRACE,Commit_unit,FUNCTION," * REEXECUTE [%d]",i);
920
921	uint32_t num_bank = internal_REEXECUTE_NUM_BANK [i];
922
923	entry_t * entry = _rob [num_bank].front();
924	rob_state_t state = entry->state;
925
926	// Change state
927	switch (state)
928	{
929	case ROB_STORE_OK : {state = ROB_STORE_OK_WAIT_END; break; }
930	case ROB_STORE_KO : {state = ROB_STORE_KO_WAIT_END; break; }
931	case ROB_STORE_EVENT : {state = ROB_EVENT_WAIT_END; break; }
932	default : {throw ERRORMORPHEO(FUNCTION,_("Reexecute : invalid state value.\n"));}
933	}
934
935	entry->state = state;
936	}
937
938	// ===================================================================
939	// =====[ BRANCH_COMPLETE ]===========================================
940	// ===================================================================
941	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
942	// Test if the prediction_unit have accept the branch complete transaction
943	if (internal_BRANCH_COMPLETE_VAL [i] and PORT_READ(in_BRANCH_COMPLETE_ACK [i]))
944	{
945	log_printf(TRACE,Commit_unit,FUNCTION," * BRANCH_COMPLETE [%d]",i);
946
947	// Read information
948	uint32_t num_bank = internal_BRANCH_COMPLETE_NUM_BANK [i];
949
950	entry_t * entry = _rob [num_bank].front();
951
952	#ifdef DEBUG_TEST
953	rob_state_t state = entry->state;
954	if (state != ROB_BRANCH_COMPLETE)
955	throw ERRORMORPHEO(FUNCTION,_("Branch_complete : Invalid state value.\n"));
956	#endif
957	Tcontrol_t miss = PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]);
958
959	log_printf(TRACE,Commit_unit,FUNCTION," * miss_prediction : %d",miss);
960
961	entry->state = (miss)?ROB_END_BRANCH_MISS_SPECULATIVE:ROB_END_OK_SPECULATIVE;
962
963	// bool flush = reg_EVENT_FLUSH [entry->front_end_id][entry->context_id];
964
965	// Branch_complete can be execute if
966	// * no present event
967	// * futur event and most not speculative that the event
968
969	// Also, test if in this cycle, they have not an most recently event !!!
970	if (miss)
971	{
972	bool can = true;
973	uint32_t packet = ((entry->ptr << _param->_shift_num_slot) \| num_bank);
974
975	// test if this packet is before previous event
976	if (reg_EVENT_STATE [entry->front_end_id][entry->context_id] == COMMIT_EVENT_STATE_NOT_YET_EVENT)
977	{
978	uint32_t _top = ((_rob[ reg_NUM_BANK_HEAD].front()->ptr << _param->_shift_num_slot) \| reg_NUM_BANK_HEAD);
979	uint32_t _old = reg_EVENT_PACKET [entry->front_end_id][entry->context_id];
980	uint32_t _new = packet;
981	if (_old < _top) _old = _old+_param->_size_queue;
982	if (_new < _top) _new = _new+_param->_size_queue;
983	if (_new < _old) reg_EVENT_PACKET [entry->front_end_id][entry->context_id] = packet;
984	else can = false;
985	}
986	else
987	reg_EVENT_PACKET [entry->front_end_id][entry->context_id] = packet;
988
989	if (can)
990	{
991	// In all case, stop instruction flow
992	reg_EVENT_STATE [entry->front_end_id][entry->context_id] = COMMIT_EVENT_STATE_NOT_YET_EVENT;
993	// reg_EVENT_DEPTH [entry->front_end_id][entry->context_id] = _rob[packet]._depth;
994	reg_EVENT_NB_INST [entry->front_end_id][entry->context_id] = reg_NB_INST_COMMIT_ALL [entry->front_end_id][entry->context_id];
995	// reg_EVENT_STOP [entry->front_end_id][entry->context_id] = true;
996
997	// reg_EVENT_CAN_RESTART [entry->front_end_id][entry->context_id] = false;
998
999	reg_EVENT_LAST_NUM_BANK [entry->front_end_id][entry->context_id] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1;
1000	reg_EVENT_LAST_NUM_PTR [entry->front_end_id][entry->context_id] = reg_NUM_PTR_TAIL;
1001	}
1002	}
1003	}
1004
1005	// ===================================================================
1006	// =====[ UPDATE ]====================================================
1007	// ===================================================================
1008	// Update when exception or load_miss
1009	if (internal_UPDATE_VAL and PORT_READ(in_UPDATE_ACK))
1010	{
1011	log_printf(TRACE,Commit_unit,FUNCTION," * UPDATE");
1012
1013	// Change state
1014	entry_t * entry = _rob [internal_UPDATE_NUM_BANK].front();
1015
1016	switch (entry->state)
1017	{
1018	// case ROB_END_EXCEPTION_UPDATE :
1019	// {
1020	// entry->state = ROB_END_KO;
1021	// throw ERRORMORPHEO(FUNCTION,_("Moore : exception is not yet supported (Coming Soon).\n"));
1022	// break;
1023	// }
1024	case ROB_END_LOAD_MISS_UPDATE :
1025	{
1026	log_printf(TRACE,Commit_unit,FUNCTION," * ROB_END_LOAD_MISS_UPDATE");
1027
1028	entry->state = ROB_END_LOAD_MISS;
1029	break;
1030	}
1031	default :
1032	{
1033	throw ERRORMORPHEO(FUNCTION,_("Update : invalid state.\n"));
1034	break;
1035	}
1036	}
1037	}
1038
1039	// ===================================================================
1040	// =====[ EVENT ]=====================================================
1041	// ===================================================================
1042	// for (uint32_t i=0; i < _param->_nb_front_end; ++i)
1043	// for (uint32_t j=0; j < _param->_nb_context[i]; ++j)
1044	// if (PORT_READ(in_EVENT_VAL [i][j]) and internal_EVENT_ACK [i][j])
1045	// {
1046	// log_printf(TRACE,Commit_unit,FUNCTION," * EVENT [%d][%d]",i,j);
1047
1048	// reg_PC_CURRENT [i][j] = PORT_READ(in_EVENT_ADDRESS [i][j]);
1049	// reg_PC_CURRENT_IS_DS [i][j] = PORT_READ(in_EVENT_IS_DS_TAKE [i][j]); // ??
1050	// reg_PC_CURRENT_IS_DS_TAKE [i][j] = PORT_READ(in_EVENT_IS_DS_TAKE [i][j]);
1051	// reg_PC_NEXT [i][j] = PORT_READ(in_EVENT_ADDRESS_NEXT [i][j]);
1052	// // PORT_READ(in_EVENT_ADDRESS_NEXT_VAL [i][j]);
1053	// }
1054
1055	// ===================================================================
1056	// =====[ DEPTH - HEAD ]==============================================
1057	// ===================================================================
1058
1059	{
1060	bool can_continue [_param->_nb_front_end][_param->_max_nb_context];
1061	uint32_t event_nb_inst [_param->_nb_front_end][_param->_max_nb_context];
1062	bool is_speculative [_param->_nb_front_end][_param->_max_nb_context];
1063	for (uint32_t i=0; i<_param->_nb_front_end; i++)
1064	for (uint32_t j=0; j<_param->_nb_context [i]; j++)
1065	{
1066	event_nb_inst [i][j] = 0;
1067	is_speculative[i][j] = false;
1068	can_continue [i][j] = (((reg_EVENT_NB_INST [i][j] == 0) or
1069	( event_nb_inst [i][j] < reg_EVENT_NB_INST [i][j])) and
1070	not reg_EVENT_LAST [i][j]);
1071	}
1072
1073	// Read all instruction of all top bank
1074	for (uint32_t i=0; i<_param->_nb_bank; i++)
1075	{
1076	uint32_t num_bank = (reg_NUM_BANK_HEAD+i)%_param->_nb_bank;
1077
1078	// Test if have an instruction
1079	if (not _rob[num_bank].empty())
1080	{
1081	// Scan all instruction in windows and test if instruction is speculative
1082	entry_t * entry = _rob [num_bank].front();
1083
1084	uint32_t num_packet = ((entry->ptr << _param->_shift_num_slot) \| num_bank);
1085	Tcontext_t front_end_id = entry->front_end_id;
1086	Tcontext_t context_id = entry->context_id ;
1087
1088	log_printf(TRACE,Commit_unit,FUNCTION," * HEAD [%d] - %d",num_bank,num_packet);
1089	log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id);
1090	log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id);
1091	log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_LAST : %d",reg_EVENT_LAST [front_end_id][context_id]);
1092	log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_NB_INST : %d",reg_EVENT_NB_INST [front_end_id][context_id]);
1093	log_printf(TRACE,Commit_unit,FUNCTION," * event_nb_inst : %d", event_nb_inst [front_end_id][context_id]);
1094
1095	// scan while last event instruction is not retire
1096	if (can_continue [front_end_id][context_id])
1097	{
1098	// Read information
1099	rob_state_t state = entry->state;
1100	// Tdepth_t depth = entry->depth;
1101
1102	// Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[front_end_id][context_id]):0;
1103	// Tdepth_t depth_max = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[front_end_id][context_id]):0;
1104	// Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL [front_end_id][context_id]);
1105
1106	// is a valid instruction ?
1107	// If DEPTH_CURRENT :
1108	// equal at DEPTH_MIN -> not speculative
1109	// not include ]DEPTH_MIN:DEPTH_MAX] -> previous branch miss
1110	// include ]DEPTH_MIN:DEPTH_MAX] -> speculative
1111
1112	// All case
1113	// ....... min ...X... max ....... OK
1114	// ....... min ....... max ...X... KO
1115	// ...X... min ....... max ....... KO
1116	// ....... max ....... min ...X... OK
1117	// ...X... max ....... min ....... OK
1118	// ....... max ...X... min ....... KO
1119
1120	bool flush = ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_EVENT) or
1121	// (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_DECOD) or
1122	(reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_END));
1123	bool speculative = is_speculative [front_end_id][context_id];
1124
1125	// bool speculative = entry->speculative and not (depth == depth_min);
1126	// Tcontrol_t is_valid = ((not speculative or
1127	// (speculative and (depth_full or // all is valid
1128	// ((depth_min <= depth_max)? // test if depth is overflow
1129	// ((depth >= depth_min) and (depth <=depth_max)):
1130	// ((depth >= depth_min) or (depth <=depth_max))))))
1131	// and not flush); // no event
1132
1133	Tcontrol_t is_valid = not flush;
1134
1135
1136	//Tcontrol_t is_valid = ((depth == depth_min) and not flush);
1137
1138
1139	log_printf(TRACE,Commit_unit,FUNCTION," * is_valid : %d ((depth == depth_min) and not flush)",is_valid);
1140	// log_printf(TRACE,Commit_unit,FUNCTION," * depth : %d",depth );
1141	// log_printf(TRACE,Commit_unit,FUNCTION," * depth_min : %d",depth_min);
1142	// log_printf(TRACE,Commit_unit,FUNCTION," * depth_max : %d",depth_max);
1143	// log_printf(TRACE,Commit_unit,FUNCTION," * depth_full : %d",depth_full);
1144	log_printf(TRACE,Commit_unit,FUNCTION," * speculative : %d",speculative);
1145	log_printf(TRACE,Commit_unit,FUNCTION," * flush : %d",flush);
1146	log_printf(TRACE,Commit_unit,FUNCTION," * state (before) : %s",toString(state).c_str());
1147
1148	// //------------------------------------------------------
1149	// // Event ?
1150	// //------------------------------------------------------
1151
1152	// if ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_NOT_YET_EVENT) and
1153	// (reg_EVENT_PACKET [front_end_id][context_id] == num_packet))
1154	// {
1155	// switch (state)
1156	// {
1157	// case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_BRANCH_MISS ; break;}
1158	// case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_LOAD_MISS_UPDATE ; break;}
1159	// case ROB_END_BRANCH_MISS :
1160	// case ROB_END_LOAD_MISS :
1161	// case ROB_END :
1162	// {break;}
1163	// default :
1164	// {
1165	// throw ERRORMORPHEO(FUNCTION,toString(_("Head [%d] : invalid state (%s)"),num_packet,toString(state).c_str()));
1166	// break;
1167	// }
1168	// }
1169	// }
1170
1171	//------------------------------------------------------
1172	// test if instruction is miss speculative
1173	//------------------------------------------------------
1174	if (not is_valid)
1175	{
1176	// Change state
1177	switch (state)
1178	{
1179	case ROB_BRANCH_WAIT_END : {state = ROB_EVENT_WAIT_END; break;}
1180	case ROB_BRANCH_COMPLETE : {state = ROB_END_MISS ; break;}
1181	case ROB_END_BRANCH_MISS :
1182	case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;}
1183	case ROB_END_LOAD_MISS :
1184	case ROB_END_LOAD_MISS_UPDATE :
1185	case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;}
1186	case ROB_STORE_OK : {state = ROB_STORE_KO ; break;}
1187	case ROB_STORE_WAIT_END_OK : {state = ROB_STORE_WAIT_END_KO; break;}
1188	case ROB_STORE_OK_WAIT_END : {state = ROB_STORE_KO_WAIT_END; break;}
1189	case ROB_OTHER_WAIT_END : {state = ROB_EVENT_WAIT_END; break;}
1190	case ROB_END_OK :
1191	case ROB_END_OK_SPECULATIVE : {state = ROB_END_MISS ; break;}
1192	case ROB_END_KO :
1193	case ROB_END_KO_SPECULATIVE : {state = ROB_END_MISS ; break;}
1194	case ROB_END_EXCEPTION_UPDATE :
1195	case ROB_END_EXCEPTION :
1196	case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_MISS ; break;}
1197
1198	// don't change state -> wait
1199	case ROB_STORE_WAIT_END_KO : {break;}
1200	case ROB_STORE_KO : {break;}
1201	case ROB_STORE_KO_WAIT_END : {break;}
1202	case ROB_STORE_EVENT : {break;}
1203	case ROB_EVENT_WAIT_END : {break;}
1204	case ROB_END_MISS : {break;}
1205	case ROB_END : {break;}
1206
1207	// can't have miss speculation -> invalid state
1208	default :
1209	{
1210	throw ERRORMORPHEO(FUNCTION,toString(_("Miss Speculation : Invalide state : %s.\n"),toString(state).c_str()));
1211	break;
1212	}
1213	}
1214	}
1215
1216	//------------------------------------------------------
1217	// test if instruction is branch not finish
1218	//------------------------------------------------------
1219	switch (state)
1220	{
1221	case ROB_BRANCH_WAIT_END :
1222	case ROB_BRANCH_COMPLETE :
1223	{
1224	is_speculative [front_end_id][context_id] = true;
1225	break;
1226	}
1227	default : break;
1228	}
1229
1230	//------------------------------------------------------
1231	// test if instruction is not speculative
1232	//------------------------------------------------------
1233	// entry->speculative = speculative;
1234	// if (entry->depth == depth_min)
1235	// test if instruction is speculative (depth != depth_min)
1236	if (not speculative)
1237	{
1238	switch (state)
1239	{
1240	case ROB_END_OK_SPECULATIVE : {state = ROB_END_OK ; break;}
1241	case ROB_END_KO_SPECULATIVE : {state = ROB_END_KO ; break;}
1242	case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_BRANCH_MISS ; break;}
1243	case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_LOAD_MISS_UPDATE ; break;}
1244	default : {break;} // else, no change
1245	}
1246	}
1247
1248	//------------------------------------------------------
1249	// test if instruction wait head and is the top of rob
1250	//------------------------------------------------------
1251	// TODO : retire OOO
1252	if (i == 0)
1253	{
1254	switch (state)
1255	{
1256	// case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_OK; break;}
1257	case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_EXCEPTION_UPDATE; break;}
1258	default : {break;} // else, no change
1259	}
1260	}
1261
1262	// Write new state
1263	entry->state = state;
1264
1265	log_printf(TRACE,Commit_unit,FUNCTION," * state (after ) : %s",toString(state).c_str());
1266
1267	// log_printf(TRACE,Commit_unit,FUNCTION," * Stop Scan !!!");
1268
1269	event_nb_inst [front_end_id][context_id] ++;
1270
1271	// stop if :
1272	// * begin event
1273	// * end event
1274	if (((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_NOT_YET_EVENT) and
1275	(reg_EVENT_PACKET[front_end_id][context_id] == num_packet)) or
1276	((reg_EVENT_NB_INST [front_end_id][context_id] > 0) and
1277	( event_nb_inst [front_end_id][context_id] >= reg_EVENT_NB_INST [front_end_id][context_id])))
1278	can_continue [front_end_id][context_id] = false;
1279	}
1280	}
1281	}
1282	}
1283
1284
1285
1286	#ifdef STATISTICS
1287	if (usage_is_set(_usage,USE_STATISTICS))
1288	{
1289	for (uint32_t i=0; i<_param->_nb_bank; i++)
1290	*(_stat_bank_nb_inst [i]) += _rob[i].size();
1291
1292	for (uint32_t i=0; i<_param->_nb_front_end; i++)
1293	for (uint32_t j=0; j<_param->_nb_context [i]; j++)
1294	{
1295	uint32_t num_thread = _param->_translate_num_context_to_num_thread [i][j];
1296
1297	switch (reg_EVENT_STATE [i][j])
1298	{
1299	case COMMIT_EVENT_STATE_NO_EVENT : (*_stat_nb_cycle_state_no_event [num_thread])++; break;
1300	case COMMIT_EVENT_STATE_NOT_YET_EVENT : (*_stat_nb_cycle_state_not_yet_event [num_thread])++; break;
1301	case COMMIT_EVENT_STATE_EVENT : (*_stat_nb_cycle_state_event [num_thread])++; break;
1302	case COMMIT_EVENT_STATE_WAIT_END : (*_stat_nb_cycle_state_wait_end [num_thread])++; break;
1303	}
1304	}
1305
1306	for (uint32_t i=0; i<_param->_nb_rename_unit; ++i)
1307	{
1308	(*_stat_nb_inst_insert [i]) += stat_nb_inst_insert [i];
1309	(*_stat_nb_inst_retire [i]) += stat_nb_inst_retire [i];
1310	(*_stat_nb_inst_commit [i]) += stat_nb_inst_commit [i];
1311	}
1312	}
1313	#endif
1314	}
1315
1316	// ===================================================================
1317	// =====[ OTHER ]=====================================================
1318	// ===================================================================
1319
1320	#if (DEBUG >= DEBUG_TRACE) and (DEBUG_Commit_unit == true)
1321	{
1322	log_printf(TRACE,Commit_unit,FUNCTION," * Dump ROB (Re-Order-Buffer)");
1323	log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_head : %d",reg_NUM_BANK_HEAD);
1324	log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_tail : %d",reg_NUM_BANK_TAIL);
1325	log_printf(TRACE,Commit_unit,FUNCTION," * num_ptr_tail : %d",reg_NUM_PTR_TAIL );
1326
1327	for (uint32_t i=0; i<_param->_nb_front_end; i++)
1328	for (uint32_t j=0; j<_param->_nb_context [i]; j++)
1329	{
1330	log_printf(TRACE,Commit_unit,FUNCTION," * [%d][%d] - %d",i,j,_param->_translate_num_context_to_num_thread [i][j]);
1331	log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_STATE : %s - %s",toString(reg_EVENT_STATE [i][j]).c_str(),toString(commit_event_state_to_event_state(reg_EVENT_STATE [i][j])).c_str());
1332	// log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_FLUSH : %d",reg_EVENT_FLUSH [i][j]);
1333	// log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_STOP : %d",reg_EVENT_STOP [i][j]);
1334	// log_printf(TRACE,Commit_unit,FUNCTION," * EVENT : %d (bank %d, ptr %d)",((reg_EVENT_NUM_PTR [i][j] << _param->_shift_num_slot) \| reg_EVENT_NUM_BANK [i][j]), reg_EVENT_NUM_BANK [i][j],reg_EVENT_NUM_PTR [i][j]);
1335	// log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_CAN_RESTART : %d",reg_EVENT_CAN_RESTART [i][j]);
1336	log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_DEPTH : %d - type %s",reg_EVENT_DEPTH [i][j],toString(reg_EVENT_TYPE [i][j]).c_str());
1337	log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_LAST : %d - packet %d - ptr %d (bank %d, ptr %d)",reg_EVENT_LAST [i][j],reg_EVENT_PACKET[i][j],((reg_EVENT_LAST_NUM_PTR [i][j] << _param->_shift_num_slot) \| reg_EVENT_LAST_NUM_BANK [i][j]), reg_EVENT_LAST_NUM_BANK [i][j],reg_EVENT_LAST_NUM_PTR [i][j]);
1338	log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_NEXT : stop : %d - packet : %d",reg_EVENT_NEXT_STOP [i][j],reg_EVENT_NEXT_PACKET[i][j]);
1339	log_printf(TRACE,Commit_unit,FUNCTION," * NB_INST_ALL : all : %d - mem : %d - event : %d",reg_NB_INST_COMMIT_ALL[i][j], reg_NB_INST_COMMIT_MEM[i][j],reg_EVENT_NB_INST[i][j]);
1340	log_printf(TRACE,Commit_unit,FUNCTION," * PC : %.8x (%.8x) - %d %d - %.8x (%.8x)",reg_PC_CURRENT [i][j],reg_PC_CURRENT [i][j]<<2, reg_PC_CURRENT_IS_DS [i][j], reg_PC_CURRENT_IS_DS_TAKE [i][j],reg_PC_NEXT [i][j],reg_PC_NEXT [i][j]<<2);
1341	}
1342
1343	std::list<entry_t*>::iterator iter [_param->_nb_bank];
1344	for (uint32_t i=0; i<_param->_nb_bank; i++)
1345	{
1346	uint32_t num_bank = (reg_NUM_BANK_HEAD+i)%_param->_nb_bank;
1347	// log_printf(TRACE,Commit_unit,FUNCTION," * Bank [%d] size : %d, ptr : %d",num_bank,(int)_rob[num_bank].size(), reg_BANK_PTR [i]);
1348
1349	iter [num_bank] = _rob[num_bank].begin();
1350	}
1351
1352	bool all_empty = false;
1353	uint32_t nb_write_rd = 0;
1354	uint32_t nb_write_re = 0;
1355
1356	while (not all_empty)
1357	{
1358	all_empty = true;
1359
1360	for (uint32_t i=0; i<_param->_nb_bank; i++)
1361	{
1362	uint32_t num_bank = (reg_NUM_BANK_HEAD+i)%_param->_nb_bank;
1363
1364	std::list<entry_t*>::iterator it = iter[num_bank];
1365	if (it != _rob[num_bank].end())
1366	{
1367	all_empty = false;
1368
1369	nb_write_rd += ((*it)->write_rd)?1:0;
1370	nb_write_re += ((*it)->write_re)?1:0;
1371
1372	log_printf(TRACE,Commit_unit,FUNCTION," [%.4d][%.4d] %.4d %.4d %.4d %.4d, %.3d %.3d, %.1d, %.1d %.4d, %.1d %.4d, %s",
1373	num_bank ,
1374	(*it)->ptr ,
1375	(*it)->front_end_id ,
1376	(*it)->context_id ,
1377	(*it)->rename_unit_id ,
1378	(*it)->depth ,
1379	(*it)->type ,
1380	(*it)->operation ,
1381	(*it)->is_delay_slot ,
1382	(*it)->use_store_queue ,
1383	(*it)->store_queue_ptr_write ,
1384	(*it)->use_load_queue ,
1385	(*it)->load_queue_ptr_write ,
1386	toString((*it)->state).c_str() );
1387	log_printf(TRACE,Commit_unit,FUNCTION," (%.4d) %.1d %.2d %.6d, %.1d %.2d %.6d, %.1d %.1d %.6d, %.1d %.2d %.6d %.6d, %.1d %.1d %.6d %.6d ",
1388	(((*it)->ptr << _param->_shift_num_slot) \| num_bank),
1389	(*it)->read_ra ,
1390	(*it)->num_reg_ra_log ,
1391	(*it)->num_reg_ra_phy ,
1392	(*it)->read_rb ,
1393	(*it)->num_reg_rb_log ,
1394	(*it)->num_reg_rb_phy ,
1395	(*it)->read_rc ,
1396	(*it)->num_reg_rc_log ,
1397	(*it)->num_reg_rc_phy ,
1398	(*it)->write_rd ,
1399	(*it)->num_reg_rd_log ,
1400	(*it)->num_reg_rd_phy_old ,
1401	(*it)->num_reg_rd_phy_new ,
1402	(*it)->write_re ,
1403	(*it)->num_reg_re_log ,
1404	(*it)->num_reg_re_phy_old ,
1405	(*it)->num_reg_re_phy_new );
1406
1407	log_printf(TRACE,Commit_unit,FUNCTION," %.2d %.2d %.1d %.1d - %.8x (%.8x) %.8x (%.8x)",
1408	(*it)->exception_use ,
1409	(*it)->exception ,
1410	(*it)->flags ,
1411	(*it)->no_sequence ,
1412	// (*it)->speculative ,
1413	(*it)->address ,
1414	(*it)->address<<2 ,
1415	(*it)->address_next ,
1416	(*it)->address_next<<2
1417	);
1418
1419	iter [num_bank] ++;
1420	}
1421	}
1422	}
1423
1424	log_printf(TRACE,Commit_unit,FUNCTION," * Dump RAT Update Table");
1425	for (uint32_t i=0; i<_param->_nb_front_end; ++i)
1426	for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
1427	{
1428	{
1429	std::string str = "";
1430	for (uint32_t k=0; k<_param->_nb_general_register_logic; k++)
1431	str+=toString("%.1d ",rat_gpr_update_table[i][j][k]);
1432
1433	log_printf(TRACE,Commit_unit,FUNCTION," * GPR [%d][%d] %s",i,j,str.c_str());
1434	}
1435
1436	{
1437	std::string str = "";
1438	for (uint32_t k=0; k<_param->_nb_special_register_logic; k++)
1439	str+=toString("%.1d ",rat_spr_update_table[i][j][k]);
1440
1441	log_printf(TRACE,Commit_unit,FUNCTION," * GPR [%d][%d] %s",i,j,str.c_str());
1442	}
1443	}
1444
1445	log_printf(TRACE,Commit_unit,FUNCTION," * nb_write_rd : %d",nb_write_rd);
1446	log_printf(TRACE,Commit_unit,FUNCTION," * nb_write_re : %d",nb_write_re);
1447	}
1448	#endif
1449
1450	#ifdef DEBUG_TEST
1451	{
1452	uint32_t x=reg_NUM_BANK_HEAD;
1453	if (not _rob[x].empty())
1454	{
1455	entry_t * entry = _rob [x].front();
1456
1457	if (false
1458	// or (entry->state == ROB_EMPTY )
1459	// or (entry->state == ROB_BRANCH_WAIT_END )
1460	// or (entry->state == ROB_BRANCH_COMPLETE )
1461	// or (entry->state == ROB_STORE_WAIT_HEAD_OK )
1462	// //or (entry->state == ROB_STORE_WAIT_HEAD_KO )
1463	// or (entry->state == ROB_STORE_HEAD_OK )
1464	// or (entry->state == ROB_STORE_HEAD_KO )
1465	// or (entry->state == ROB_OTHER_WAIT_END )
1466	// or (entry->state == ROB_EVENT_WAIT_END )
1467	// or (entry->state == ROB_END_OK_SPECULATIVE )
1468	or (entry->state == ROB_END_OK )
1469	// or (entry->state == ROB_END_KO_SPECULATIVE )
1470	// or (entry->state == ROB_END_KO )
1471	// or (entry->state == ROB_END_BRANCH_MISS_SPECULATIVE)
1472	or (entry->state == ROB_END_BRANCH_MISS )
1473	// or (entry->state == ROB_END_LOAD_MISS_SPECULATIVE )
1474	// or (entry->state == ROB_END_LOAD_MISS_UPDATE )
1475	or (entry->state == ROB_END_LOAD_MISS )
1476	// or (entry->state == ROB_END_MISS )
1477	// or (entry->state == ROB_END_EXCEPTION_WAIT_HEAD )
1478	// or (entry->state == ROB_END_EXCEPTION_UPDATE )
1479	// or (entry->state == ROB_END_EXCEPTION )
1480	)
1481	if (entry->address != reg_PC_CURRENT[entry->front_end_id][entry->context_id])
1482	throw ERRORMORPHEO(FUNCTION,toString(_("Rob top address (0x%x) is different of reg_PC_CURRENT[%d][%d] (0x%x).\n"),
1483	entry->address,
1484	entry->front_end_id,
1485	entry->context_id,
1486	reg_PC_CURRENT[entry->front_end_id][entry->context_id]));
1487	}
1488	}
1489	{
1490	uint32_t NB_INST [_param->_nb_front_end][_param->_max_nb_context];
1491	for (uint32_t i=0; i<_param->_nb_front_end; i++)
1492	for (uint32_t j=0; j<_param->_nb_context [i]; j++)
1493	NB_INST [i][j] = 0; //reg_EVENT_NB_INST [i][j];
1494
1495	for (uint32_t i=0; i<_param->_nb_bank; ++i)
1496	for (std::list<entry_t*>::iterator it=_rob[i].begin();
1497	it!=_rob [i].end();
1498	++it)
1499	NB_INST [(it)->front_end_id][(it)->context_id] ++;
1500
1501	for (uint32_t i=0; i<_param->_nb_front_end; i++)
1502	for (uint32_t j=0; j<_param->_nb_context [i]; j++)
1503	if (NB_INST [i][j] != reg_NB_INST_COMMIT_ALL [i][j])
1504	throw ERRORMORPHEO(FUNCTION,toString(_("Context [%d][%d] have not the good nb_inst (%d in rob, %d in register).\n"),i,j,NB_INST[i][j], reg_NB_INST_COMMIT_ALL [i][j]));
1505	}
1506	#endif
1507
1508	#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
1509	end_cycle ();
1510	#endif
1511
1512	// Stop Condition
1513	for (uint32_t i=0; i<_param->_nb_front_end; i++)
1514	for (uint32_t j=0; j<_param->_nb_context [i]; j++)
1515	if (_nb_cycle_idle [i][j] >= debug_idle_cycle)
1516	throw ERRORMORPHEO(FUNCTION,toString(_("Thread [%d] is idle since %.0f cycles.\n"),_param->_translate_num_context_to_num_thread[i][j],_nb_cycle_idle [i][j]));
1517
1518	log_end(Commit_unit,FUNCTION);
1519	};
1520
1521	}; // end namespace commit_unit
1522	}; // end namespace ooo_engine
1523	}; // end namespace multi_ooo_engine
1524	}; // end namespace core
1525
1526	}; // end namespace behavioural
1527	}; // end namespace morpheo
1528	#endif

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