[111] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id: Issue_queue_function_in_order_genMealy_issue_out.cpp 136 2009-10-20 18:52:15Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Issue_queue.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_ooo_engine { |
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| 15 | namespace ooo_engine { |
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| 16 | namespace issue_queue { |
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| 17 | |
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| 18 | |
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| 19 | #undef FUNCTION |
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| 20 | #define FUNCTION "Issue_queue::function_in_order_genMealy_issue_out" |
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| 21 | void Issue_queue::function_in_order_genMealy_issue_out (void) |
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| 22 | { |
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| 23 | log_begin(Issue_queue,FUNCTION); |
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| 24 | log_function(Issue_queue,FUNCTION,_name.c_str()); |
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| 25 | |
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[123] | 26 | if (PORT_READ(in_NRESET)) |
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[111] | 27 | // =================================================================== |
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| 28 | // =====[ ISSUE_OUT ]================================================= |
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| 29 | // =================================================================== |
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[123] | 30 | { |
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[111] | 31 | Tcontrol_t val [_param->_nb_inst_issue]; |
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| 32 | |
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[117] | 33 | uint32_t index=0; |
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[111] | 34 | for (uint32_t i=0; i<_param->_nb_inst_issue; i++) |
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| 35 | val [i] = 0; |
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| 36 | |
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[117] | 37 | //-------------------------------------- |
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[111] | 38 | // From Reexecute_queue |
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[117] | 39 | //-------------------------------------- |
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[111] | 40 | |
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[117] | 41 | // scan all reexecute_queue slot ... |
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[111] | 42 | // uint32_t num_reexecute_entry = 0; |
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| 43 | for (std::list<entry_t*>::iterator it=_reexecute_queue.begin(); |
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| 44 | it!=_reexecute_queue.end(); |
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| 45 | ++it) |
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| 46 | { |
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| 47 | entry_t* entry = (*it); |
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| 48 | |
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[117] | 49 | val [index] = 1; |
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| 50 | |
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| 51 | if (_param->_have_port_context_id) |
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| 52 | PORT_WRITE(out_ISSUE_OUT_CONTEXT_ID [index], entry->_context_id ); |
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| 53 | if (_param->_have_port_front_end_id) |
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| 54 | PORT_WRITE(out_ISSUE_OUT_FRONT_END_ID [index], entry->_front_end_id ); |
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| 55 | if (_param->_have_port_rob_ptr ) |
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| 56 | PORT_WRITE(out_ISSUE_OUT_PACKET_ID [index], entry->_packet_id ); |
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| 57 | PORT_WRITE(out_ISSUE_OUT_OPERATION [index], entry->_operation ); |
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| 58 | PORT_WRITE(out_ISSUE_OUT_TYPE [index], entry->_type ); |
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[136] | 59 | PORT_WRITE(out_ISSUE_OUT_CANCEL [index], 0 ); |
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[117] | 60 | PORT_WRITE(out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE [index], entry->_store_queue_ptr_write); |
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[122] | 61 | PORT_WRITE(out_ISSUE_OUT_STORE_QUEUE_PTR_READ [index], entry->_store_queue_ptr_read ); |
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| 62 | PORT_WRITE(out_ISSUE_OUT_STORE_QUEUE_EMPTY [index], entry->_store_queue_empty ); |
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[117] | 63 | if (_param->_have_port_load_queue_ptr) |
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| 64 | PORT_WRITE(out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE [index], entry->_load_queue_ptr_write ); |
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| 65 | PORT_WRITE(out_ISSUE_OUT_HAS_IMMEDIAT [index], entry->_has_immediat ); |
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| 66 | PORT_WRITE(out_ISSUE_OUT_IMMEDIAT [index], entry->_immediat ); |
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| 67 | PORT_WRITE(out_ISSUE_OUT_READ_RA [index], entry->_read_ra ); |
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| 68 | PORT_WRITE(out_ISSUE_OUT_NUM_REG_RA [index], entry->_num_reg_ra ); |
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| 69 | PORT_WRITE(out_ISSUE_OUT_READ_RB [index], entry->_read_rb ); |
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| 70 | PORT_WRITE(out_ISSUE_OUT_NUM_REG_RB [index], entry->_num_reg_rb ); |
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| 71 | PORT_WRITE(out_ISSUE_OUT_READ_RC [index], entry->_read_rc ); |
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| 72 | PORT_WRITE(out_ISSUE_OUT_NUM_REG_RC [index], entry->_num_reg_rc ); |
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| 73 | PORT_WRITE(out_ISSUE_OUT_WRITE_RD [index], entry->_write_rd ); |
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| 74 | PORT_WRITE(out_ISSUE_OUT_NUM_REG_RD [index], entry->_num_reg_rd ); |
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| 75 | PORT_WRITE(out_ISSUE_OUT_WRITE_RE [index], entry->_write_re ); |
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| 76 | PORT_WRITE(out_ISSUE_OUT_NUM_REG_RE [index], entry->_num_reg_re ); |
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[111] | 77 | |
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[117] | 78 | internal_ISSUE_OUT_FROM_REEXECUTE [index] = true; |
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| 79 | // internal_ISSUE_OUT_NUM_BANK [index] = num_reexecute_entry; |
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| 80 | internal_ISSUE_OUT_ENTRY [index] = entry; |
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[111] | 81 | |
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[117] | 82 | index ++; // next slot |
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[111] | 83 | } |
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[117] | 84 | |
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| 85 | //-------------------------------------- |
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| 86 | // From Issue_queue |
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| 87 | //-------------------------------------- |
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| 88 | index = _param->_nb_inst_reexecute; |
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[111] | 89 | |
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[117] | 90 | log_printf(TRACE,Issue_queue,FUNCTION," * From Issue_queue"); |
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| 91 | |
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| 92 | // for all instruction in issue_queue head ... |
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[111] | 93 | for (uint32_t i=0; i<_param->_nb_bank; ++i) |
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| 94 | { |
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| 95 | uint32_t num_bank=(reg_NUM_BANK_HEAD+i)%_param->_nb_bank; |
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| 96 | |
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| 97 | log_printf(TRACE,Issue_queue,FUNCTION," * Bank [%d]",num_bank); |
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| 98 | |
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[117] | 99 | // bool find = false; |
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[111] | 100 | |
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[117] | 101 | // ... test if have an instruction |
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[111] | 102 | if (not _issue_queue [num_bank].empty()) |
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| 103 | { |
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| 104 | log_printf(TRACE,Issue_queue,FUNCTION," * Not Empty !!!"); |
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| 105 | |
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[117] | 106 | // read instruction |
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[111] | 107 | entry_t* entry = _issue_queue [num_bank].front(); |
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| 108 | |
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[117] | 109 | // Tcontrol_t issue_ack = PORT_READ(in_ISSUE_OUT_ACK [index]); |
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| 110 | |
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| 111 | log_printf(TRACE,Issue_queue,FUNCTION," * Issue [%d]",index); |
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| 112 | // log_printf(TRACE,Issue_queue,FUNCTION," * issue_ack : %d",issue_ack); |
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| 113 | // log_printf(TRACE,Issue_queue,FUNCTION," * previous transaction : %d",val[index]); |
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| 114 | // log_printf(TRACE,Issue_queue,FUNCTION," * can issue type : %d",_param->_table_issue_type [index][entry->_type]); |
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[111] | 115 | |
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[117] | 116 | // in_order : test if find a valid read_unit |
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| 117 | // if (issue_ack) |
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| 118 | // { |
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| 119 | // log_printf(TRACE,Issue_queue,FUNCTION," * find !!!"); |
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| 120 | |
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| 121 | // find = true; |
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| 122 | // } |
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[115] | 123 | |
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[117] | 124 | // find a issue port |
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| 125 | val [index] = true; // instruction is valid |
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| 126 | |
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| 127 | if (_param->_have_port_context_id) |
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| 128 | PORT_WRITE(out_ISSUE_OUT_CONTEXT_ID [index], entry->_context_id ); |
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| 129 | if (_param->_have_port_front_end_id) |
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| 130 | PORT_WRITE(out_ISSUE_OUT_FRONT_END_ID [index], entry->_front_end_id ); |
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| 131 | if (_param->_have_port_rob_ptr ) |
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| 132 | PORT_WRITE(out_ISSUE_OUT_PACKET_ID [index], entry->_packet_id ); |
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| 133 | PORT_WRITE(out_ISSUE_OUT_OPERATION [index], entry->_operation ); |
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| 134 | PORT_WRITE(out_ISSUE_OUT_TYPE [index], entry->_type ); |
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[136] | 135 | PORT_WRITE(out_ISSUE_OUT_CANCEL [index], 0 ); |
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[117] | 136 | PORT_WRITE(out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE [index], entry->_store_queue_ptr_write); |
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[122] | 137 | PORT_WRITE(out_ISSUE_OUT_STORE_QUEUE_PTR_READ [index], entry->_store_queue_ptr_read ); |
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| 138 | PORT_WRITE(out_ISSUE_OUT_STORE_QUEUE_EMPTY [index], entry->_store_queue_empty ); |
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[117] | 139 | if (_param->_have_port_load_queue_ptr) |
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| 140 | PORT_WRITE(out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE [index], entry->_load_queue_ptr_write ); |
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| 141 | PORT_WRITE(out_ISSUE_OUT_HAS_IMMEDIAT [index], entry->_has_immediat ); |
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| 142 | PORT_WRITE(out_ISSUE_OUT_IMMEDIAT [index], entry->_immediat ); |
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| 143 | PORT_WRITE(out_ISSUE_OUT_READ_RA [index], entry->_read_ra ); |
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| 144 | PORT_WRITE(out_ISSUE_OUT_NUM_REG_RA [index], entry->_num_reg_ra ); |
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| 145 | PORT_WRITE(out_ISSUE_OUT_READ_RB [index], entry->_read_rb ); |
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| 146 | PORT_WRITE(out_ISSUE_OUT_NUM_REG_RB [index], entry->_num_reg_rb ); |
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| 147 | PORT_WRITE(out_ISSUE_OUT_READ_RC [index], entry->_read_rc ); |
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| 148 | PORT_WRITE(out_ISSUE_OUT_NUM_REG_RC [index], entry->_num_reg_rc ); |
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| 149 | PORT_WRITE(out_ISSUE_OUT_WRITE_RD [index], entry->_write_rd ); |
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| 150 | PORT_WRITE(out_ISSUE_OUT_NUM_REG_RD [index], entry->_num_reg_rd ); |
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| 151 | PORT_WRITE(out_ISSUE_OUT_WRITE_RE [index], entry->_write_re ); |
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| 152 | PORT_WRITE(out_ISSUE_OUT_NUM_REG_RE [index], entry->_num_reg_re ); |
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| 153 | |
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| 154 | internal_ISSUE_OUT_FROM_REEXECUTE [index] = false; |
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| 155 | internal_ISSUE_OUT_NUM_BANK [index] = num_bank; |
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| 156 | internal_ISSUE_OUT_ENTRY [index] = entry; |
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| 157 | |
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| 158 | index ++; // next slot |
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[111] | 159 | } |
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| 160 | |
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[117] | 161 | // if (not find) |
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| 162 | // { |
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| 163 | // log_printf(TRACE,Issue_queue,FUNCTION," * Not find. Stop Scan (in order)"); |
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| 164 | |
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| 165 | // break; // stop scan (in order) |
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| 166 | // } |
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[111] | 167 | } |
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[117] | 168 | |
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| 169 | // Output |
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[111] | 170 | for (uint32_t i=0; i<_param->_nb_inst_issue; i++) |
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| 171 | { |
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| 172 | internal_ISSUE_OUT_VAL [i] = val [i]; |
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| 173 | PORT_WRITE(out_ISSUE_OUT_VAL [i], internal_ISSUE_OUT_VAL [i]); |
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[117] | 174 | |
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| 175 | // // Type invalid to the Core_Glue network |
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| 176 | // if (not val [i]) // == empty |
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| 177 | // PORT_WRITE(out_ISSUE_OUT_TYPE [i], TYPE_INVALID); |
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[111] | 178 | } |
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| 179 | } |
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[123] | 180 | else |
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| 181 | { |
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| 182 | for (uint32_t i=0; i<_param->_nb_inst_issue; i++) |
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| 183 | internal_ISSUE_OUT_VAL [i] = 0; |
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| 184 | } |
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[111] | 185 | |
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[123] | 186 | for (uint32_t i=0; i<_param->_nb_inst_issue; i++) |
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| 187 | PORT_WRITE(out_ISSUE_OUT_VAL [i], internal_ISSUE_OUT_VAL [i]); |
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| 188 | |
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[111] | 189 | log_end(Issue_queue,FUNCTION); |
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| 190 | }; |
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| 191 | |
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| 192 | }; // end namespace issue_queue |
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| 193 | }; // end namespace ooo_engine |
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| 194 | }; // end namespace multi_ooo_engine |
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| 195 | }; // end namespace core |
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| 196 | |
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| 197 | }; // end namespace behavioural |
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| 198 | }; // end namespace morpheo |
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| 199 | #endif |
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