[111] | 1 | #ifdef SYSTEMC |
---|
| 2 | /* |
---|
| 3 | * $Id: Issue_queue_function_in_order_genMealy_issue_out.cpp 123 2009-06-08 20:43:30Z rosiere $ |
---|
| 4 | * |
---|
| 5 | * [ Description ] |
---|
| 6 | * |
---|
| 7 | */ |
---|
| 8 | |
---|
| 9 | #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Issue_queue.h" |
---|
| 10 | |
---|
| 11 | namespace morpheo { |
---|
| 12 | namespace behavioural { |
---|
| 13 | namespace core { |
---|
| 14 | namespace multi_ooo_engine { |
---|
| 15 | namespace ooo_engine { |
---|
| 16 | namespace issue_queue { |
---|
| 17 | |
---|
| 18 | |
---|
| 19 | #undef FUNCTION |
---|
| 20 | #define FUNCTION "Issue_queue::function_in_order_genMealy_issue_out" |
---|
| 21 | void Issue_queue::function_in_order_genMealy_issue_out (void) |
---|
| 22 | { |
---|
| 23 | log_begin(Issue_queue,FUNCTION); |
---|
| 24 | log_function(Issue_queue,FUNCTION,_name.c_str()); |
---|
| 25 | |
---|
[123] | 26 | if (PORT_READ(in_NRESET)) |
---|
[111] | 27 | // =================================================================== |
---|
| 28 | // =====[ ISSUE_OUT ]================================================= |
---|
| 29 | // =================================================================== |
---|
[123] | 30 | { |
---|
[111] | 31 | Tcontrol_t val [_param->_nb_inst_issue]; |
---|
| 32 | |
---|
[117] | 33 | uint32_t index=0; |
---|
[111] | 34 | for (uint32_t i=0; i<_param->_nb_inst_issue; i++) |
---|
| 35 | val [i] = 0; |
---|
| 36 | |
---|
[117] | 37 | //-------------------------------------- |
---|
[111] | 38 | // From Reexecute_queue |
---|
[117] | 39 | //-------------------------------------- |
---|
[111] | 40 | |
---|
[117] | 41 | // scan all reexecute_queue slot ... |
---|
[111] | 42 | // uint32_t num_reexecute_entry = 0; |
---|
| 43 | for (std::list<entry_t*>::iterator it=_reexecute_queue.begin(); |
---|
| 44 | it!=_reexecute_queue.end(); |
---|
| 45 | ++it) |
---|
| 46 | { |
---|
| 47 | entry_t* entry = (*it); |
---|
| 48 | |
---|
[117] | 49 | val [index] = 1; |
---|
| 50 | |
---|
| 51 | if (_param->_have_port_context_id) |
---|
| 52 | PORT_WRITE(out_ISSUE_OUT_CONTEXT_ID [index], entry->_context_id ); |
---|
| 53 | if (_param->_have_port_front_end_id) |
---|
| 54 | PORT_WRITE(out_ISSUE_OUT_FRONT_END_ID [index], entry->_front_end_id ); |
---|
| 55 | if (_param->_have_port_rob_ptr ) |
---|
| 56 | PORT_WRITE(out_ISSUE_OUT_PACKET_ID [index], entry->_packet_id ); |
---|
| 57 | PORT_WRITE(out_ISSUE_OUT_OPERATION [index], entry->_operation ); |
---|
| 58 | PORT_WRITE(out_ISSUE_OUT_TYPE [index], entry->_type ); |
---|
| 59 | PORT_WRITE(out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE [index], entry->_store_queue_ptr_write); |
---|
[122] | 60 | PORT_WRITE(out_ISSUE_OUT_STORE_QUEUE_PTR_READ [index], entry->_store_queue_ptr_read ); |
---|
| 61 | PORT_WRITE(out_ISSUE_OUT_STORE_QUEUE_EMPTY [index], entry->_store_queue_empty ); |
---|
[117] | 62 | if (_param->_have_port_load_queue_ptr) |
---|
| 63 | PORT_WRITE(out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE [index], entry->_load_queue_ptr_write ); |
---|
| 64 | PORT_WRITE(out_ISSUE_OUT_HAS_IMMEDIAT [index], entry->_has_immediat ); |
---|
| 65 | PORT_WRITE(out_ISSUE_OUT_IMMEDIAT [index], entry->_immediat ); |
---|
| 66 | PORT_WRITE(out_ISSUE_OUT_READ_RA [index], entry->_read_ra ); |
---|
| 67 | PORT_WRITE(out_ISSUE_OUT_NUM_REG_RA [index], entry->_num_reg_ra ); |
---|
| 68 | PORT_WRITE(out_ISSUE_OUT_READ_RB [index], entry->_read_rb ); |
---|
| 69 | PORT_WRITE(out_ISSUE_OUT_NUM_REG_RB [index], entry->_num_reg_rb ); |
---|
| 70 | PORT_WRITE(out_ISSUE_OUT_READ_RC [index], entry->_read_rc ); |
---|
| 71 | PORT_WRITE(out_ISSUE_OUT_NUM_REG_RC [index], entry->_num_reg_rc ); |
---|
| 72 | PORT_WRITE(out_ISSUE_OUT_WRITE_RD [index], entry->_write_rd ); |
---|
| 73 | PORT_WRITE(out_ISSUE_OUT_NUM_REG_RD [index], entry->_num_reg_rd ); |
---|
| 74 | PORT_WRITE(out_ISSUE_OUT_WRITE_RE [index], entry->_write_re ); |
---|
| 75 | PORT_WRITE(out_ISSUE_OUT_NUM_REG_RE [index], entry->_num_reg_re ); |
---|
[111] | 76 | |
---|
[117] | 77 | internal_ISSUE_OUT_FROM_REEXECUTE [index] = true; |
---|
| 78 | // internal_ISSUE_OUT_NUM_BANK [index] = num_reexecute_entry; |
---|
| 79 | internal_ISSUE_OUT_ENTRY [index] = entry; |
---|
[111] | 80 | |
---|
[117] | 81 | index ++; // next slot |
---|
[111] | 82 | } |
---|
[117] | 83 | |
---|
| 84 | //-------------------------------------- |
---|
| 85 | // From Issue_queue |
---|
| 86 | //-------------------------------------- |
---|
| 87 | index = _param->_nb_inst_reexecute; |
---|
[111] | 88 | |
---|
[117] | 89 | log_printf(TRACE,Issue_queue,FUNCTION," * From Issue_queue"); |
---|
| 90 | |
---|
| 91 | // for all instruction in issue_queue head ... |
---|
[111] | 92 | for (uint32_t i=0; i<_param->_nb_bank; ++i) |
---|
| 93 | { |
---|
| 94 | uint32_t num_bank=(reg_NUM_BANK_HEAD+i)%_param->_nb_bank; |
---|
| 95 | |
---|
| 96 | log_printf(TRACE,Issue_queue,FUNCTION," * Bank [%d]",num_bank); |
---|
| 97 | |
---|
[117] | 98 | // bool find = false; |
---|
[111] | 99 | |
---|
[117] | 100 | // ... test if have an instruction |
---|
[111] | 101 | if (not _issue_queue [num_bank].empty()) |
---|
| 102 | { |
---|
| 103 | log_printf(TRACE,Issue_queue,FUNCTION," * Not Empty !!!"); |
---|
| 104 | |
---|
[117] | 105 | // read instruction |
---|
[111] | 106 | entry_t* entry = _issue_queue [num_bank].front(); |
---|
| 107 | |
---|
[117] | 108 | // Tcontrol_t issue_ack = PORT_READ(in_ISSUE_OUT_ACK [index]); |
---|
| 109 | |
---|
| 110 | log_printf(TRACE,Issue_queue,FUNCTION," * Issue [%d]",index); |
---|
| 111 | // log_printf(TRACE,Issue_queue,FUNCTION," * issue_ack : %d",issue_ack); |
---|
| 112 | // log_printf(TRACE,Issue_queue,FUNCTION," * previous transaction : %d",val[index]); |
---|
| 113 | // log_printf(TRACE,Issue_queue,FUNCTION," * can issue type : %d",_param->_table_issue_type [index][entry->_type]); |
---|
[111] | 114 | |
---|
[117] | 115 | // in_order : test if find a valid read_unit |
---|
| 116 | // if (issue_ack) |
---|
| 117 | // { |
---|
| 118 | // log_printf(TRACE,Issue_queue,FUNCTION," * find !!!"); |
---|
| 119 | |
---|
| 120 | // find = true; |
---|
| 121 | // } |
---|
[115] | 122 | |
---|
[117] | 123 | // find a issue port |
---|
| 124 | val [index] = true; // instruction is valid |
---|
| 125 | |
---|
| 126 | if (_param->_have_port_context_id) |
---|
| 127 | PORT_WRITE(out_ISSUE_OUT_CONTEXT_ID [index], entry->_context_id ); |
---|
| 128 | if (_param->_have_port_front_end_id) |
---|
| 129 | PORT_WRITE(out_ISSUE_OUT_FRONT_END_ID [index], entry->_front_end_id ); |
---|
| 130 | if (_param->_have_port_rob_ptr ) |
---|
| 131 | PORT_WRITE(out_ISSUE_OUT_PACKET_ID [index], entry->_packet_id ); |
---|
| 132 | PORT_WRITE(out_ISSUE_OUT_OPERATION [index], entry->_operation ); |
---|
| 133 | PORT_WRITE(out_ISSUE_OUT_TYPE [index], entry->_type ); |
---|
| 134 | PORT_WRITE(out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE [index], entry->_store_queue_ptr_write); |
---|
[122] | 135 | PORT_WRITE(out_ISSUE_OUT_STORE_QUEUE_PTR_READ [index], entry->_store_queue_ptr_read ); |
---|
| 136 | PORT_WRITE(out_ISSUE_OUT_STORE_QUEUE_EMPTY [index], entry->_store_queue_empty ); |
---|
[117] | 137 | if (_param->_have_port_load_queue_ptr) |
---|
| 138 | PORT_WRITE(out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE [index], entry->_load_queue_ptr_write ); |
---|
| 139 | PORT_WRITE(out_ISSUE_OUT_HAS_IMMEDIAT [index], entry->_has_immediat ); |
---|
| 140 | PORT_WRITE(out_ISSUE_OUT_IMMEDIAT [index], entry->_immediat ); |
---|
| 141 | PORT_WRITE(out_ISSUE_OUT_READ_RA [index], entry->_read_ra ); |
---|
| 142 | PORT_WRITE(out_ISSUE_OUT_NUM_REG_RA [index], entry->_num_reg_ra ); |
---|
| 143 | PORT_WRITE(out_ISSUE_OUT_READ_RB [index], entry->_read_rb ); |
---|
| 144 | PORT_WRITE(out_ISSUE_OUT_NUM_REG_RB [index], entry->_num_reg_rb ); |
---|
| 145 | PORT_WRITE(out_ISSUE_OUT_READ_RC [index], entry->_read_rc ); |
---|
| 146 | PORT_WRITE(out_ISSUE_OUT_NUM_REG_RC [index], entry->_num_reg_rc ); |
---|
| 147 | PORT_WRITE(out_ISSUE_OUT_WRITE_RD [index], entry->_write_rd ); |
---|
| 148 | PORT_WRITE(out_ISSUE_OUT_NUM_REG_RD [index], entry->_num_reg_rd ); |
---|
| 149 | PORT_WRITE(out_ISSUE_OUT_WRITE_RE [index], entry->_write_re ); |
---|
| 150 | PORT_WRITE(out_ISSUE_OUT_NUM_REG_RE [index], entry->_num_reg_re ); |
---|
| 151 | |
---|
| 152 | internal_ISSUE_OUT_FROM_REEXECUTE [index] = false; |
---|
| 153 | internal_ISSUE_OUT_NUM_BANK [index] = num_bank; |
---|
| 154 | internal_ISSUE_OUT_ENTRY [index] = entry; |
---|
| 155 | |
---|
| 156 | index ++; // next slot |
---|
[111] | 157 | } |
---|
| 158 | |
---|
[117] | 159 | // if (not find) |
---|
| 160 | // { |
---|
| 161 | // log_printf(TRACE,Issue_queue,FUNCTION," * Not find. Stop Scan (in order)"); |
---|
| 162 | |
---|
| 163 | // break; // stop scan (in order) |
---|
| 164 | // } |
---|
[111] | 165 | } |
---|
[117] | 166 | |
---|
| 167 | // Output |
---|
[111] | 168 | for (uint32_t i=0; i<_param->_nb_inst_issue; i++) |
---|
| 169 | { |
---|
| 170 | internal_ISSUE_OUT_VAL [i] = val [i]; |
---|
| 171 | PORT_WRITE(out_ISSUE_OUT_VAL [i], internal_ISSUE_OUT_VAL [i]); |
---|
[117] | 172 | |
---|
| 173 | // // Type invalid to the Core_Glue network |
---|
| 174 | // if (not val [i]) // == empty |
---|
| 175 | // PORT_WRITE(out_ISSUE_OUT_TYPE [i], TYPE_INVALID); |
---|
[111] | 176 | } |
---|
| 177 | } |
---|
[123] | 178 | else |
---|
| 179 | { |
---|
| 180 | for (uint32_t i=0; i<_param->_nb_inst_issue; i++) |
---|
| 181 | internal_ISSUE_OUT_VAL [i] = 0; |
---|
| 182 | } |
---|
[111] | 183 | |
---|
[123] | 184 | for (uint32_t i=0; i<_param->_nb_inst_issue; i++) |
---|
| 185 | PORT_WRITE(out_ISSUE_OUT_VAL [i], internal_ISSUE_OUT_VAL [i]); |
---|
| 186 | |
---|
[111] | 187 | log_end(Issue_queue,FUNCTION); |
---|
| 188 | }; |
---|
| 189 | |
---|
| 190 | }; // end namespace issue_queue |
---|
| 191 | }; // end namespace ooo_engine |
---|
| 192 | }; // end namespace multi_ooo_engine |
---|
| 193 | }; // end namespace core |
---|
| 194 | |
---|
| 195 | }; // end namespace behavioural |
---|
| 196 | }; // end namespace morpheo |
---|
| 197 | #endif |
---|