[88] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id: Issue_queue_transition.cpp 117 2009-05-16 14:42:39Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Issue_queue.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_ooo_engine { |
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| 15 | namespace ooo_engine { |
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| 16 | namespace issue_queue { |
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| 17 | |
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| 18 | |
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| 19 | #undef FUNCTION |
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| 20 | #define FUNCTION "Issue_queue::transition" |
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| 21 | void Issue_queue::transition (void) |
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| 22 | { |
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| 23 | log_begin(Issue_queue,FUNCTION); |
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| 24 | log_function(Issue_queue,FUNCTION,_name.c_str()); |
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| 25 | |
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| 26 | if (PORT_READ(in_NRESET) == 0) |
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| 27 | { |
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| 28 | _priority_in ->reset(); |
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[110] | 29 | _reexecute_queue.clear(); |
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[88] | 30 | } |
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| 31 | else |
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| 32 | { |
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| 33 | _priority_in ->transition(); |
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| 34 | |
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| 35 | // =================================================================== |
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[110] | 36 | // =====[ REEXECUTE_UNIT ]============================================ |
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| 37 | // =================================================================== |
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| 38 | |
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| 39 | for (uint32_t i=0; i<_param->_nb_inst_reexecute; ++i) |
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| 40 | if (PORT_READ(in_REEXECUTE_VAL [i]) and internal_REEXECUTE_ACK [i]) |
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| 41 | { |
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| 42 | log_printf(TRACE,Issue_queue,FUNCTION," * REEXECUTE [%d]",i); |
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[88] | 43 | #ifdef STATISTICS |
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[110] | 44 | if (usage_is_set(_usage,USE_STATISTICS)) |
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| 45 | (*_stat_nb_inst_reexecute) ++; |
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[88] | 46 | #endif |
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[110] | 47 | entry_t * entry = new entry_t |
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| 48 | ( |
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| 49 | (_param->_have_port_context_id )?PORT_READ(in_REEXECUTE_CONTEXT_ID [i]):0, |
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| 50 | (_param->_have_port_front_end_id )?PORT_READ(in_REEXECUTE_FRONT_END_ID [i]):0, |
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| 51 | (_param->_have_port_rob_ptr )?PORT_READ(in_REEXECUTE_PACKET_ID [i]):0, |
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| 52 | PORT_READ(in_REEXECUTE_OPERATION [i]), |
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| 53 | PORT_READ(in_REEXECUTE_TYPE [i]), |
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| 54 | PORT_READ(in_REEXECUTE_STORE_QUEUE_PTR_WRITE [i]), |
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| 55 | (_param->_have_port_load_queue_ptr)?PORT_READ(in_REEXECUTE_LOAD_QUEUE_PTR_WRITE [i]):0, |
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| 56 | PORT_READ(in_REEXECUTE_HAS_IMMEDIAT [i]), |
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| 57 | PORT_READ(in_REEXECUTE_IMMEDIAT [i]), |
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| 58 | PORT_READ(in_REEXECUTE_READ_RA [i]), |
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| 59 | PORT_READ(in_REEXECUTE_NUM_REG_RA [i]), |
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| 60 | PORT_READ(in_REEXECUTE_READ_RB [i]), |
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| 61 | PORT_READ(in_REEXECUTE_NUM_REG_RB [i]), |
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| 62 | PORT_READ(in_REEXECUTE_READ_RC [i]), |
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| 63 | PORT_READ(in_REEXECUTE_NUM_REG_RC [i]), |
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| 64 | PORT_READ(in_REEXECUTE_WRITE_RD [i]), |
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| 65 | PORT_READ(in_REEXECUTE_NUM_REG_RD [i]), |
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| 66 | PORT_READ(in_REEXECUTE_WRITE_RE [i]), |
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| 67 | PORT_READ(in_REEXECUTE_NUM_REG_RE [i]) |
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| 68 | ); |
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[88] | 69 | |
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[110] | 70 | _reexecute_queue.push_back(entry); |
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| 71 | } |
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[88] | 72 | |
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| 73 | // =================================================================== |
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| 74 | // =====[ ISSUE_OUT ]================================================= |
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| 75 | // =================================================================== |
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| 76 | |
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[110] | 77 | for (uint32_t i=0; i<_param->_nb_inst_issue; ++i) |
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| 78 | if (internal_ISSUE_OUT_VAL [i] and PORT_READ(in_ISSUE_OUT_ACK [i])) |
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| 79 | { |
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[111] | 80 | #ifdef STATISTICS |
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| 81 | if (usage_is_set(_usage,USE_STATISTICS)) |
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| 82 | (*_stat_nb_inst_issue_out ) ++; |
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| 83 | #endif |
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[110] | 84 | if (internal_ISSUE_OUT_FROM_REEXECUTE [i]) |
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| 85 | { |
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[111] | 86 | entry_t * entry = internal_ISSUE_OUT_ENTRY [i]; |
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| 87 | |
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[110] | 88 | log_printf(TRACE,Issue_queue,FUNCTION," * ISSUE_OUT [%d] - From Reexecute_queue",i); |
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| 89 | |
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| 90 | _reexecute_queue.remove(entry); |
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[111] | 91 | |
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| 92 | delete entry; |
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[110] | 93 | } |
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[111] | 94 | // else ... in function specific |
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| 95 | } |
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| 96 | } |
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[109] | 97 | |
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[111] | 98 | // specific implementation |
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| 99 | (this->*function_transition) (); |
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[109] | 100 | |
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[111] | 101 | // =================================================================== |
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| 102 | // =====[ PRINT ]==================================================== |
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| 103 | // =================================================================== |
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[110] | 104 | |
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[111] | 105 | #if defined(DEBUG) and DEBUG_Issue_queue and (DEBUG >= DEBUG_TRACE) |
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[109] | 106 | log_printf(TRACE,Issue_queue,FUNCTION," * Dump Issue_queue"); |
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[110] | 107 | |
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[117] | 108 | if (_param->_queue_scheme == ISSUE_QUEUE_SCHEME_IN_ORDER) |
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| 109 | { |
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| 110 | log_printf(TRACE,Issue_queue,FUNCTION," * reg_NUM_BANK_HEAD : %d",reg_NUM_BANK_HEAD); |
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| 111 | log_printf(TRACE,Issue_queue,FUNCTION," * reg_NUM_BANK_TAIL : %d",reg_NUM_BANK_TAIL); |
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| 112 | } |
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| 113 | |
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[88] | 114 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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| 115 | { |
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[109] | 116 | log_printf(TRACE,Issue_queue,FUNCTION," * Bank [%d] size : %d",i,(int)_issue_queue[i].size()); |
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| 117 | |
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| 118 | uint32_t j = 0; |
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| 119 | for (std::list<entry_t*>::iterator it=_issue_queue[i].begin();it!=_issue_queue[i].end(); ++it) |
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| 120 | { |
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| 121 | log_printf(TRACE,Issue_queue,FUNCTION," [%.4d] %.2d %.2d %.4d, %.2d %.3d, %.2d %.2d, %.1d %.8x, %.1d %.4d, %.1d %.4d, %.1d %.4d, %.1d %.4d, %.1d %.4d", |
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| 122 | j, |
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| 123 | |
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| 124 | (*it)->_context_id , |
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| 125 | (*it)->_front_end_id , |
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| 126 | (*it)->_packet_id , |
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| 127 | |
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| 128 | (*it)->_type , |
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| 129 | (*it)->_operation , |
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| 130 | |
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| 131 | (*it)->_store_queue_ptr_write, |
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| 132 | (*it)->_load_queue_ptr_write , |
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| 133 | |
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| 134 | (*it)->_has_immediat , |
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| 135 | (*it)->_immediat , |
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| 136 | |
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| 137 | (*it)->_read_ra , |
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| 138 | (*it)->_num_reg_ra , |
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| 139 | |
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| 140 | (*it)->_read_rb , |
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| 141 | (*it)->_num_reg_rb , |
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| 142 | |
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| 143 | (*it)->_read_rc , |
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| 144 | (*it)->_num_reg_rc , |
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| 145 | |
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| 146 | (*it)->_write_rd , |
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| 147 | (*it)->_num_reg_rd , |
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| 148 | |
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| 149 | (*it)->_write_re , |
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| 150 | (*it)->_num_reg_re ); |
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| 151 | |
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| 152 | ++j; |
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| 153 | } |
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[88] | 154 | } |
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| 155 | |
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[110] | 156 | { |
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| 157 | log_printf(TRACE,Issue_queue,FUNCTION," * Reexecute_queue - size : %d",(int)_reexecute_queue.size()); |
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| 158 | |
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| 159 | uint32_t i = 0; |
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| 160 | |
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| 161 | for (std::list<entry_t*>::iterator it=_reexecute_queue.begin();it!=_reexecute_queue.end(); ++it) |
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| 162 | { |
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| 163 | log_printf(TRACE,Issue_queue,FUNCTION," [%.4d] %.2d %.2d %.4d, %.2d %.3d, %.2d %.2d, %.1d %.8x, %.1d %.4d, %.1d %.4d, %.1d %.4d, %.1d %.4d, %.1d %.4d", |
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| 164 | i, |
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| 165 | |
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| 166 | (*it)->_context_id , |
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| 167 | (*it)->_front_end_id , |
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| 168 | (*it)->_packet_id , |
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| 169 | |
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| 170 | (*it)->_type , |
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| 171 | (*it)->_operation , |
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| 172 | |
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| 173 | (*it)->_store_queue_ptr_write, |
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| 174 | (*it)->_load_queue_ptr_write , |
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| 175 | |
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| 176 | (*it)->_has_immediat , |
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| 177 | (*it)->_immediat , |
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| 178 | |
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| 179 | (*it)->_read_ra , |
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| 180 | (*it)->_num_reg_ra , |
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| 181 | |
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| 182 | (*it)->_read_rb , |
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| 183 | (*it)->_num_reg_rb , |
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| 184 | |
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| 185 | (*it)->_read_rc , |
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| 186 | (*it)->_num_reg_rc , |
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| 187 | |
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| 188 | (*it)->_write_rd , |
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| 189 | (*it)->_num_reg_rd , |
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| 190 | |
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| 191 | (*it)->_write_re , |
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| 192 | (*it)->_num_reg_re ); |
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| 193 | ++i; |
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| 194 | } |
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| 195 | } |
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| 196 | #endif |
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| 197 | |
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| 198 | #ifdef STATISTICS |
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| 199 | if (usage_is_set(_usage,USE_STATISTICS)) |
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| 200 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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| 201 | *(_stat_bank_nb_inst [i]) += _issue_queue[i].size(); |
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| 202 | #endif |
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| 203 | |
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[111] | 204 | |
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| 205 | |
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[88] | 206 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
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| 207 | end_cycle (); |
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| 208 | #endif |
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| 209 | |
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| 210 | log_end(Issue_queue,FUNCTION); |
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| 211 | }; |
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| 212 | |
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| 213 | }; // end namespace issue_queue |
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| 214 | }; // end namespace ooo_engine |
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| 215 | }; // end namespace multi_ooo_engine |
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| 216 | }; // end namespace core |
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| 217 | |
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| 218 | }; // end namespace behavioural |
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| 219 | }; // end namespace morpheo |
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| 220 | #endif |
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