[88] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id: Reexecute_unit_transition.cpp 88 2008-12-10 18:31:39Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Reexecute_unit.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_ooo_engine { |
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| 15 | namespace ooo_engine { |
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| 16 | namespace reexecute_unit { |
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| 17 | |
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| 18 | |
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| 19 | #undef FUNCTION |
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| 20 | #define FUNCTION "Reexecute_unit::transition" |
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| 21 | void Reexecute_unit::transition (void) |
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| 22 | { |
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| 23 | log_begin(Reexecute_unit,FUNCTION); |
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| 24 | |
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| 25 | if (PORT_READ(in_NRESET) == 0) |
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| 26 | { |
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| 27 | _priority_execute_loop->reset(); |
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| 28 | _priority_queue_in ->reset(); |
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| 29 | |
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| 30 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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| 31 | _reexecute_queue [i].clear(); |
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| 32 | } |
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| 33 | else |
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| 34 | { |
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| 35 | _priority_execute_loop->transition(); |
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| 36 | _priority_queue_in ->transition(); |
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| 37 | |
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| 38 | // =================================================================== |
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| 39 | // =====[ EXECUTE_LOOP / COMMIT ]===================================== |
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| 40 | // =================================================================== |
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| 41 | for (uint32_t i=0; i<_param->_nb_bank; ++i) |
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| 42 | if (internal_QUEUE_PUSH [i]) |
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| 43 | { |
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| 44 | entry_t * entry = new entry_t; |
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| 45 | _reexecute_queue [i].push_back(entry); |
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| 46 | |
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| 47 | uint32_t x = internal_QUEUE_NUM_EXECUTE_LOOP [i]; |
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| 48 | uint32_t y = internal_QUEUE_NUM_INST_EXECUTE [i]; |
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| 49 | uint32_t z = internal_QUEUE_NUM_INST_COMMIT [i]; |
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| 50 | |
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| 51 | entry->state = STATE_SPR_ACCESS; |
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| 52 | entry->context_id = (_param->_have_port_context_id )?PORT_READ(in_EXECUTE_LOOP_CONTEXT_ID [x][y]):0; |
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| 53 | entry->front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_EXECUTE_LOOP_FRONT_END_ID [x][y]):0; |
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| 54 | entry->packet_id = (_param->_have_port_rob_ptr )?PORT_READ(in_EXECUTE_LOOP_PACKET_ID [x][y]):0; |
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| 55 | entry->address = PORT_READ(in_EXECUTE_LOOP_ADDRESS [x][y]); |
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| 56 | entry->data = PORT_READ(in_EXECUTE_LOOP_DATA [x][y]); |
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| 57 | entry->num_reg_rd = PORT_READ(in_COMMIT_NUM_REG_RD [z]); |
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| 58 | entry->spr_wen = internal_QUEUE_INFO [i].spr_wen ; |
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| 59 | entry->reexecute = internal_QUEUE_INFO [i].reexecute; |
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| 60 | entry->type = internal_QUEUE_INFO [i].type ; |
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| 61 | entry->operation = internal_QUEUE_INFO [i].operation; |
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| 62 | entry->write_rd = internal_QUEUE_INFO [i].write_rd ; |
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| 63 | } |
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| 64 | |
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| 65 | #ifdef STATISTICS |
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| 66 | if (usage_is_set(_usage,USE_STATISTICS)) |
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| 67 | for (uint32_t i=0; i<_param->_nb_inst_commit; i++) |
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| 68 | if (internal_COMMIT_VAL [i] and PORT_READ(in_COMMIT_ACK[i])) |
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| 69 | (*_stat_nb_inst_commit) ++; |
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| 70 | #endif |
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| 71 | |
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| 72 | // =================================================================== |
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| 73 | // =====[ SPR ]======================================================= |
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| 74 | // =================================================================== |
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| 75 | for (uint32_t i=0; i<_param->_nb_inst_reexecute; i++) |
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| 76 | if (internal_SPR_VAL [i] and PORT_READ(in_SPR_ACK [i])) |
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| 77 | { |
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| 78 | #ifdef STATISTICS |
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| 79 | if (usage_is_set(_usage,USE_STATISTICS)) |
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| 80 | (*_stat_nb_spr_access) ++; |
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| 81 | #endif |
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| 82 | entry_t * entry = _reexecute_queue [i].front(); |
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| 83 | |
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| 84 | if (not entry->spr_wen) |
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| 85 | { |
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| 86 | entry->data = PORT_READ(in_SPR_RDATA [i]); |
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| 87 | entry->write_rd = not PORT_READ(in_SPR_INVALID [i]); |
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| 88 | } |
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| 89 | |
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| 90 | if (entry->reexecute) |
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| 91 | entry->state = STATE_REEXECUTE; |
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| 92 | else |
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| 93 | entry->state = STATE_EMPTY; |
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| 94 | } |
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| 95 | |
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| 96 | // =================================================================== |
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| 97 | // =====[ REEXECUTE ]================================================= |
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| 98 | // =================================================================== |
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| 99 | for (uint32_t i=0; i<_param->_nb_inst_reexecute; i++) |
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| 100 | if (internal_REEXECUTE_VAL [i] and PORT_READ(in_REEXECUTE_ACK [i])) |
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| 101 | // test source |
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| 102 | if (not internal_REEXECUTE_ROB_ACK [i]) |
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| 103 | { |
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| 104 | #ifdef STATISTICS |
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| 105 | if (usage_is_set(_usage,USE_STATISTICS)) |
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| 106 | (*_stat_nb_inst_reexecute) ++; |
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| 107 | #endif |
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| 108 | |
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| 109 | // invalid entry |
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| 110 | _reexecute_queue [i].front()->state = STATE_EMPTY; |
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| 111 | } |
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| 112 | #ifdef DEBUG_TEST |
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| 113 | else |
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| 114 | { |
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| 115 | if (not PORT_READ(in_REEXECUTE_ROB_VAL [i])) |
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| 116 | throw ERRORMORPHEO(FUNCTION,toString(_("in_REEXECUTE_ROB_VAL [%d] must be = 1.\n"),i)); |
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| 117 | } |
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| 118 | #endif |
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| 119 | |
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| 120 | // =================================================================== |
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| 121 | // =====[ End cycle ]================================================= |
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| 122 | // =================================================================== |
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| 123 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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| 124 | if (not _reexecute_queue [i].empty() and (_reexecute_queue [i].front()->state == STATE_EMPTY)) |
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| 125 | { |
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| 126 | entry_t * entry = _reexecute_queue [i].front(); |
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| 127 | _reexecute_queue [i].pop_front(); |
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| 128 | delete entry; |
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| 129 | |
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| 130 | #ifdef STATISTICS |
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| 131 | if (usage_is_set(_usage,USE_STATISTICS)) |
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| 132 | (*(_stat_bank_nb_inst [i])) += _reexecute_queue [i].size(); |
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| 133 | #endif |
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| 134 | } |
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| 135 | } |
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| 136 | |
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| 137 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
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| 138 | end_cycle (); |
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| 139 | #endif |
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| 140 | |
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| 141 | log_end(Reexecute_unit,FUNCTION); |
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| 142 | }; |
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| 143 | |
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| 144 | }; // end namespace reexecute_unit |
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| 145 | }; // end namespace ooo_engine |
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| 146 | }; // end namespace multi_ooo_engine |
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| 147 | }; // end namespace core |
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| 148 | |
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| 149 | }; // end namespace behavioural |
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| 150 | }; // end namespace morpheo |
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| 151 | #endif |
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