1 | #ifdef SYSTEMC |
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2 | /* |
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3 | * $Id: Reexecute_unit_transition.cpp 101 2009-01-15 17:19:08Z rosiere $ |
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4 | * |
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5 | * [ Description ] |
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6 | * |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Reexecute_unit.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | namespace core { |
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14 | namespace multi_ooo_engine { |
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15 | namespace ooo_engine { |
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16 | namespace reexecute_unit { |
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17 | |
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18 | |
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19 | #undef FUNCTION |
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20 | #define FUNCTION "Reexecute_unit::transition" |
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21 | void Reexecute_unit::transition (void) |
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22 | { |
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23 | log_begin(Reexecute_unit,FUNCTION); |
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24 | log_function(Reexecute_unit,FUNCTION,_name.c_str()); |
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25 | |
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26 | if (PORT_READ(in_NRESET) == 0) |
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27 | { |
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28 | _priority_execute_loop->reset(); |
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29 | _priority_queue_in ->reset(); |
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30 | |
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31 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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32 | _reexecute_queue [i].clear(); |
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33 | } |
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34 | else |
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35 | { |
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36 | _priority_execute_loop->transition(); |
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37 | _priority_queue_in ->transition(); |
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38 | |
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39 | // =================================================================== |
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40 | // =====[ EXECUTE_LOOP / COMMIT ]===================================== |
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41 | // =================================================================== |
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42 | for (uint32_t i=0; i<_param->_nb_bank; ++i) |
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43 | if (internal_QUEUE_PUSH [i]) |
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44 | { |
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45 | entry_t * entry = new entry_t; |
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46 | _reexecute_queue [i].push_back(entry); |
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47 | |
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48 | uint32_t x = internal_QUEUE_NUM_EXECUTE_LOOP [i]; |
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49 | uint32_t y = internal_QUEUE_NUM_INST_EXECUTE [i]; |
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50 | uint32_t z = internal_QUEUE_NUM_INST_COMMIT [i]; |
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51 | |
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52 | entry->state = STATE_SPR_ACCESS; |
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53 | entry->context_id = (_param->_have_port_context_id )?PORT_READ(in_EXECUTE_LOOP_CONTEXT_ID [x][y]):0; |
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54 | entry->front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_EXECUTE_LOOP_FRONT_END_ID [x][y]):0; |
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55 | entry->packet_id = (_param->_have_port_rob_ptr )?PORT_READ(in_EXECUTE_LOOP_PACKET_ID [x][y]):0; |
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56 | entry->address = PORT_READ(in_EXECUTE_LOOP_ADDRESS [x][y]); |
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57 | entry->data = PORT_READ(in_EXECUTE_LOOP_DATA [x][y]); |
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58 | entry->num_reg_rd = PORT_READ(in_COMMIT_NUM_REG_RD [z]); |
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59 | entry->spr_wen = internal_QUEUE_INFO [i].spr_wen ; |
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60 | entry->reexecute = internal_QUEUE_INFO [i].reexecute; |
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61 | entry->type = internal_QUEUE_INFO [i].type ; |
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62 | entry->operation = internal_QUEUE_INFO [i].operation; |
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63 | entry->write_rd = internal_QUEUE_INFO [i].write_rd ; |
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64 | } |
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65 | |
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66 | #ifdef STATISTICS |
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67 | if (usage_is_set(_usage,USE_STATISTICS)) |
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68 | for (uint32_t i=0; i<_param->_nb_inst_commit; i++) |
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69 | if (internal_COMMIT_VAL [i] and PORT_READ(in_COMMIT_ACK[i])) |
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70 | (*_stat_nb_inst_commit) ++; |
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71 | #endif |
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72 | |
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73 | // =================================================================== |
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74 | // =====[ SPR ]======================================================= |
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75 | // =================================================================== |
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76 | for (uint32_t i=0; i<_param->_nb_inst_reexecute; i++) |
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77 | if (internal_SPR_VAL [i] and PORT_READ(in_SPR_ACK [i])) |
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78 | { |
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79 | #ifdef STATISTICS |
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80 | if (usage_is_set(_usage,USE_STATISTICS)) |
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81 | (*_stat_nb_spr_access) ++; |
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82 | #endif |
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83 | entry_t * entry = _reexecute_queue [i].front(); |
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84 | |
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85 | if (not entry->spr_wen) |
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86 | { |
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87 | entry->data = PORT_READ(in_SPR_RDATA [i]); |
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88 | // entry->write_rd = not PORT_READ(in_SPR_INVALID [i]); // in all case write value |
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89 | } |
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90 | |
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91 | if (entry->reexecute) |
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92 | entry->state = STATE_REEXECUTE; |
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93 | else |
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94 | entry->state = STATE_EMPTY; |
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95 | } |
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96 | |
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97 | // =================================================================== |
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98 | // =====[ REEXECUTE ]================================================= |
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99 | // =================================================================== |
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100 | for (uint32_t i=0; i<_param->_nb_inst_reexecute; i++) |
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101 | if (internal_REEXECUTE_VAL [i] and PORT_READ(in_REEXECUTE_ACK [i])) |
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102 | // test source |
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103 | if (not internal_REEXECUTE_ROB_ACK [i]) |
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104 | { |
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105 | #ifdef STATISTICS |
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106 | if (usage_is_set(_usage,USE_STATISTICS)) |
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107 | (*_stat_nb_inst_reexecute) ++; |
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108 | #endif |
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109 | |
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110 | // invalid entry |
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111 | _reexecute_queue [i].front()->state = STATE_EMPTY; |
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112 | } |
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113 | #ifdef DEBUG_TEST |
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114 | else |
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115 | { |
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116 | if (not PORT_READ(in_REEXECUTE_ROB_VAL [i])) |
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117 | throw ERRORMORPHEO(FUNCTION,toString(_("in_REEXECUTE_ROB_VAL [%d] must be = 1.\n"),i)); |
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118 | } |
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119 | #endif |
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120 | |
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121 | // =================================================================== |
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122 | // =====[ End cycle ]================================================= |
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123 | // =================================================================== |
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124 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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125 | if (not _reexecute_queue [i].empty() and (_reexecute_queue [i].front()->state == STATE_EMPTY)) |
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126 | { |
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127 | entry_t * entry = _reexecute_queue [i].front(); |
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128 | _reexecute_queue [i].pop_front(); |
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129 | delete entry; |
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130 | |
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131 | #ifdef STATISTICS |
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132 | if (usage_is_set(_usage,USE_STATISTICS)) |
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133 | (*(_stat_bank_nb_inst [i])) += _reexecute_queue [i].size(); |
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134 | #endif |
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135 | } |
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136 | } |
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137 | |
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138 | #if ((DEBUG >= DEBUG_TRACE) and DEBUG_Reexecute_unit) |
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139 | log_printf(TRACE,Reexecute_unit,FUNCTION," * Dump Reexecute_queue"); |
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140 | |
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141 | for (uint32_t i=0; i<_param->_nb_bank; ++i) |
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142 | { |
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143 | uint32_t j=0; |
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144 | for (std::list<entry_t *>::iterator it=_reexecute_queue[i].begin(); |
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145 | it!=_reexecute_queue[i].end(); |
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146 | ++it) |
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147 | { |
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148 | log_printf(TRACE,Reexecute_unit,FUNCTION," [%.4d][%.4d] %.4d %.4d %.4d, %.1d %.1d, %.4d %.4d, %.8x (%.2d %.4d) %.8x, %.1d %.5d, %s", |
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149 | i, |
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150 | j, |
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151 | (*it)->context_id , |
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152 | (*it)->front_end_id , |
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153 | (*it)->packet_id , |
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154 | (*it)->spr_wen , |
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155 | (*it)->reexecute , |
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156 | (*it)->type , |
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157 | (*it)->operation , |
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158 | (*it)->address , |
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159 | ((*it)->address >> _param->_shift_spr_num_group) & _param->_mask_spr_num_group, |
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160 | ((*it)->address ) & _param->_mask_spr_num_reg , |
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161 | (*it)->data , |
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162 | (*it)->write_rd , |
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163 | (*it)->num_reg_rd , |
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164 | toString((*it)->state).c_str()); |
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165 | |
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166 | ++j; |
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167 | } |
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168 | } |
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169 | // // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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170 | // private : std::list<entry_t *> * _reexecute_queue ;//[nb_bank] |
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171 | typedef struct |
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172 | { |
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173 | } entry_t; |
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174 | |
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175 | #endif |
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176 | |
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177 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
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178 | end_cycle (); |
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179 | #endif |
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180 | |
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181 | log_end(Reexecute_unit,FUNCTION); |
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182 | }; |
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183 | |
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184 | }; // end namespace reexecute_unit |
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185 | }; // end namespace ooo_engine |
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186 | }; // end namespace multi_ooo_engine |
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187 | }; // end namespace core |
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188 | |
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189 | }; // end namespace behavioural |
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190 | }; // end namespace morpheo |
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191 | #endif |
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