[78] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id: Dependency_checking_unit_genMealy.cpp 137 2010-02-16 12:35:48Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/include/Dependency_checking_unit.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_ooo_engine { |
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| 15 | namespace ooo_engine { |
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| 16 | namespace rename_unit { |
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| 17 | namespace register_translation_unit { |
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| 18 | namespace dependency_checking_unit { |
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| 19 | |
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| 20 | |
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| 21 | #undef FUNCTION |
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| 22 | #define FUNCTION "Dependency_checking_unit::genMealy" |
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| 23 | void Dependency_checking_unit::genMealy (void) |
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| 24 | { |
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[88] | 25 | log_begin(Dependency_checking_unit,FUNCTION); |
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| 26 | log_function(Dependency_checking_unit,FUNCTION,_name.c_str()); |
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[78] | 27 | |
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[123] | 28 | if (PORT_READ(in_NRESET)) |
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| 29 | { |
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[78] | 30 | // Tcontrol_t val [_param->_nb_inst_insert]; |
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| 31 | // Tcontrol_t ack [_param->_nb_inst_insert]; |
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| 32 | Tcontext_t front_end_id [_param->_nb_inst_insert]; |
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| 33 | Tcontext_t context_id [_param->_nb_inst_insert]; |
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| 34 | Tcontrol_t read_ra [_param->_nb_inst_insert]; |
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| 35 | Tgeneral_address_t num_reg_ra_log [_param->_nb_inst_insert]; |
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| 36 | Tgeneral_address_t num_reg_ra_phy [_param->_nb_inst_insert]; |
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| 37 | Tcontrol_t read_rb [_param->_nb_inst_insert]; |
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| 38 | Tgeneral_address_t num_reg_rb_log [_param->_nb_inst_insert]; |
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| 39 | Tgeneral_address_t num_reg_rb_phy [_param->_nb_inst_insert]; |
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| 40 | Tcontrol_t read_rc [_param->_nb_inst_insert]; |
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| 41 | Tspecial_address_t num_reg_rc_log [_param->_nb_inst_insert]; |
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| 42 | Tspecial_address_t num_reg_rc_phy [_param->_nb_inst_insert]; |
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| 43 | Tcontrol_t write_rd [_param->_nb_inst_insert]; |
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| 44 | Tgeneral_address_t num_reg_rd_log [_param->_nb_inst_insert]; |
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| 45 | Tgeneral_address_t num_reg_rd_phy_old [_param->_nb_inst_insert]; |
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| 46 | Tgeneral_address_t num_reg_rd_phy_new [_param->_nb_inst_insert]; |
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| 47 | Tcontrol_t write_re [_param->_nb_inst_insert]; |
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| 48 | Tspecial_address_t num_reg_re_log [_param->_nb_inst_insert]; |
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| 49 | Tspecial_address_t num_reg_re_phy_old [_param->_nb_inst_insert]; |
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| 50 | Tspecial_address_t num_reg_re_phy_new [_param->_nb_inst_insert]; |
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| 51 | |
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| 52 | // 4 dependency : |
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| 53 | // * Read after Read : it's a false dependency |
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| 54 | // * Write after Read : it's inhibt by rename process |
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| 55 | // * Write after Write : for the num_reg_old |
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| 56 | // * Read after Write : dependency |
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| 57 | for (uint32_t i=0; i<_param->_nb_inst_insert; i++) |
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| 58 | { |
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| 59 | // =====[ Input ]================================================== |
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| 60 | // val [i] = PORT_READ(in_RENAME_IN_VAL [i]); |
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| 61 | // ack [i] = PORT_READ(in_RENAME_OUT_ACK [i]); |
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| 62 | front_end_id [i] = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_IN_FRONT_END_ID [i]):0; |
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| 63 | context_id [i] = (_param->_have_port_context_id )?PORT_READ(in_RENAME_IN_CONTEXT_ID [i]):0; |
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| 64 | read_ra [i] = PORT_READ(in_RENAME_IN_READ_RA [i]); |
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| 65 | num_reg_ra_log [i] = PORT_READ(in_RENAME_IN_NUM_REG_RA_LOG [i]); |
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| 66 | num_reg_ra_phy [i] = PORT_READ(in_RENAME_IN_NUM_REG_RA_PHY [i]); |
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| 67 | read_rb [i] = PORT_READ(in_RENAME_IN_READ_RB [i]); |
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| 68 | num_reg_rb_log [i] = PORT_READ(in_RENAME_IN_NUM_REG_RB_LOG [i]); |
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| 69 | num_reg_rb_phy [i] = PORT_READ(in_RENAME_IN_NUM_REG_RB_PHY [i]); |
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| 70 | read_rc [i] = PORT_READ(in_RENAME_IN_READ_RC [i]); |
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| 71 | num_reg_rc_log [i] = PORT_READ(in_RENAME_IN_NUM_REG_RC_LOG [i]); |
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| 72 | num_reg_rc_phy [i] = PORT_READ(in_RENAME_IN_NUM_REG_RC_PHY [i]); |
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| 73 | write_rd [i] = PORT_READ(in_RENAME_IN_WRITE_RD [i]); |
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| 74 | num_reg_rd_log [i] = PORT_READ(in_RENAME_IN_NUM_REG_RD_LOG [i]); |
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| 75 | num_reg_rd_phy_old [i] = PORT_READ(in_RENAME_IN_NUM_REG_RD_PHY_OLD [i]); |
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| 76 | num_reg_rd_phy_new [i] = PORT_READ(in_RENAME_IN_NUM_REG_RD_PHY_NEW [i]); |
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| 77 | write_re [i] = PORT_READ(in_RENAME_IN_WRITE_RE [i]); |
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| 78 | num_reg_re_log [i] = PORT_READ(in_RENAME_IN_NUM_REG_RE_LOG [i]); |
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| 79 | num_reg_re_phy_old [i] = PORT_READ(in_RENAME_IN_NUM_REG_RE_PHY_OLD [i]); |
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| 80 | num_reg_re_phy_new [i] = PORT_READ(in_RENAME_IN_NUM_REG_RE_PHY_NEW [i]); |
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| 81 | |
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[88] | 82 | log_printf(TRACE,Dependency_checking_unit,FUNCTION," * (before) [%d] %.2d %.2d, %.1d %.2d %.5d, %.1d %.2d %.5d, %.1d %.2d %.5d, %.1d %.2d %.5d -> %.5d, %.1d %.2d %.5d -> %.5d", |
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| 83 | i, |
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| 84 | front_end_id [i], |
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| 85 | context_id [i], |
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| 86 | read_ra [i], |
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| 87 | num_reg_ra_log [i], |
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| 88 | num_reg_ra_phy [i], |
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| 89 | read_rb [i], |
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| 90 | num_reg_rb_log [i], |
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| 91 | num_reg_rb_phy [i], |
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| 92 | read_rc [i], |
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| 93 | num_reg_rc_log [i], |
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| 94 | num_reg_rc_phy [i], |
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| 95 | write_rd [i], |
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| 96 | num_reg_rd_log [i], |
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| 97 | num_reg_rd_phy_old [i], |
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| 98 | num_reg_rd_phy_new [i], |
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| 99 | write_re [i], |
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| 100 | num_reg_re_log [i], |
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| 101 | num_reg_re_phy_old [i], |
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| 102 | num_reg_re_phy_new [i]); |
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| 103 | |
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[78] | 104 | // ================================================================ |
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| 105 | // =====[ Write after Write ]====================================== |
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| 106 | // ================================================================ |
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| 107 | if (write_rd [i]) |
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| 108 | // Inverse scan : with x < y, instruction x is before in the sequential order program that the instruction y |
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| 109 | for (int32_t j=i-1; j>=0; j--) |
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| 110 | if ((write_rd [j] == 1 ) and |
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| 111 | (num_reg_rd_log [j] == num_reg_rd_log [i]) and |
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| 112 | (front_end_id [j] == front_end_id [i]) and |
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| 113 | (context_id [j] == context_id [i]) ) |
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| 114 | { |
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[88] | 115 | log_printf(TRACE,Dependency_checking_unit,FUNCTION," * RD : WAW dependency with inst[%d].RD",j); |
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[78] | 116 | num_reg_rd_phy_old [i] = num_reg_rd_phy_new [j]; |
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| 117 | break; // find the most recently dependency |
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| 118 | } |
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| 119 | |
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| 120 | if (write_re [i]) |
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| 121 | // Inverse scan : with x < y, instruction x is before in the sequential order program that the instruction y |
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| 122 | for (int32_t j=i-1; j>=0; j--) |
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| 123 | if ((write_re [j] == 1 ) and |
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| 124 | (num_reg_re_log [j] == num_reg_re_log [i]) and |
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| 125 | (front_end_id [j] == front_end_id [i]) and |
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| 126 | (context_id [j] == context_id [i]) ) |
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| 127 | { |
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[88] | 128 | log_printf(TRACE,Dependency_checking_unit,FUNCTION," * RE : WAW dependency with inst[%d].RE",j); |
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[78] | 129 | num_reg_re_phy_old [i] = num_reg_re_phy_new [j]; |
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| 130 | break; // find the most recently dependency |
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| 131 | } |
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| 132 | // ================================================================ |
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| 133 | // =====[ Read after Write ]====================================== |
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| 134 | // ================================================================ |
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| 135 | if (read_ra [i]) |
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| 136 | // Inverse scan : with x < y, instruction x is before in the sequential order program that the instruction y |
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| 137 | for (int32_t j=i-1; j>=0; j--) |
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| 138 | if ((write_rd [j] == 1 ) and |
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| 139 | (num_reg_rd_log [j] == num_reg_ra_log [i]) and |
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| 140 | (front_end_id [j] == front_end_id [i]) and |
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| 141 | (context_id [j] == context_id [i]) ) |
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| 142 | { |
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[88] | 143 | log_printf(TRACE,Dependency_checking_unit,FUNCTION," * RA : RAW dependency with inst[%d].RD",j); |
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[78] | 144 | num_reg_ra_phy [i] = num_reg_rd_phy_new [j]; |
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| 145 | break; // find the most recently dependency |
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| 146 | } |
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| 147 | |
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| 148 | if (read_rb [i]) |
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| 149 | // Inverse scan : with x < y, instruction x is before in the sequential order program that the instruction y |
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| 150 | for (int32_t j=i-1; j>=0; j--) |
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| 151 | if ((write_rd [j] == 1 ) and |
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| 152 | (num_reg_rd_log [j] == num_reg_rb_log [i]) and |
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| 153 | (front_end_id [j] == front_end_id [i]) and |
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| 154 | (context_id [j] == context_id [i]) ) |
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| 155 | { |
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[88] | 156 | log_printf(TRACE,Dependency_checking_unit,FUNCTION," * RB : RAW dependency with inst[%d].RD",j); |
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[78] | 157 | num_reg_rb_phy [i] = num_reg_rd_phy_new [j]; |
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| 158 | break; // find the most recently dependency |
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| 159 | } |
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| 160 | |
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| 161 | if (read_rc [i]) |
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| 162 | // Inverse scan : with x < y, instruction x is before in the sequential order program that the instruction y |
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| 163 | for (int32_t j=i-1; j>=0; j--) |
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| 164 | if ((write_re [j] == 1 ) and |
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| 165 | (num_reg_re_log [j] == num_reg_rc_log [i]) and |
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| 166 | (front_end_id [j] == front_end_id [i]) and |
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| 167 | (context_id [j] == context_id [i]) ) |
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| 168 | { |
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[88] | 169 | log_printf(TRACE,Dependency_checking_unit,FUNCTION," * RC : RAW dependency with inst[%d].RE",j); |
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[78] | 170 | num_reg_rc_phy [i] = num_reg_re_phy_new [j]; |
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| 171 | break; // find the most recently dependency |
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| 172 | } |
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| 173 | |
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[88] | 174 | log_printf(TRACE,Dependency_checking_unit,FUNCTION," * (after ) [%d] %.2d %.2d, %.1d %.2d %.5d, %.1d %.2d %.5d, %.1d %.2d %.5d, %.1d %.2d %.5d -> %.5d, %.1d %.2d %.5d -> %.5d", |
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| 175 | i, |
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| 176 | front_end_id [i], |
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| 177 | context_id [i], |
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| 178 | read_ra [i], |
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| 179 | num_reg_ra_log [i], |
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| 180 | num_reg_ra_phy [i], |
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| 181 | read_rb [i], |
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| 182 | num_reg_rb_log [i], |
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| 183 | num_reg_rb_phy [i], |
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| 184 | read_rc [i], |
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| 185 | num_reg_rc_log [i], |
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| 186 | num_reg_rc_phy [i], |
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| 187 | write_rd [i], |
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| 188 | num_reg_rd_log [i], |
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| 189 | num_reg_rd_phy_old [i], |
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| 190 | num_reg_rd_phy_new [i], |
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| 191 | write_re [i], |
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| 192 | num_reg_re_log [i], |
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| 193 | num_reg_re_phy_old [i], |
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| 194 | num_reg_re_phy_new [i]); |
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| 195 | |
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[78] | 196 | // =====[ Output ]================================================= |
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| 197 | // PORT_WRITE(out_RENAME_OUT_VAL [i], val [i]); |
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| 198 | // PORT_WRITE(out_RENAME_IN_ACK [i], ack [i]); |
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[137] | 199 | // if (_param->_have_port_front_end_id) |
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| 200 | // PORT_WRITE(out_RENAME_OUT_FRONT_END_ID [i], front_end_id [i]); |
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| 201 | // if (_param->_have_port_context_id) |
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| 202 | // PORT_WRITE(out_RENAME_OUT_CONTEXT_ID [i], context_id [i]); |
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[78] | 203 | PORT_WRITE(out_RENAME_OUT_READ_RA [i], read_ra [i]); |
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[121] | 204 | #ifdef DEBUG |
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[78] | 205 | PORT_WRITE(out_RENAME_OUT_NUM_REG_RA_LOG [i], num_reg_ra_log [i]); |
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[121] | 206 | #endif |
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[78] | 207 | PORT_WRITE(out_RENAME_OUT_NUM_REG_RA_PHY [i], num_reg_ra_phy [i]); |
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| 208 | PORT_WRITE(out_RENAME_OUT_READ_RB [i], read_rb [i]); |
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[121] | 209 | #ifdef DEBUG |
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[78] | 210 | PORT_WRITE(out_RENAME_OUT_NUM_REG_RB_LOG [i], num_reg_rb_log [i]); |
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[121] | 211 | #endif |
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[78] | 212 | PORT_WRITE(out_RENAME_OUT_NUM_REG_RB_PHY [i], num_reg_rb_phy [i]); |
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| 213 | PORT_WRITE(out_RENAME_OUT_READ_RC [i], read_rc [i]); |
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[121] | 214 | #ifdef DEBUG |
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[78] | 215 | PORT_WRITE(out_RENAME_OUT_NUM_REG_RC_LOG [i], num_reg_rc_log [i]); |
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[121] | 216 | #endif |
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[78] | 217 | PORT_WRITE(out_RENAME_OUT_NUM_REG_RC_PHY [i], num_reg_rc_phy [i]); |
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| 218 | PORT_WRITE(out_RENAME_OUT_WRITE_RD [i], write_rd [i]); |
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| 219 | PORT_WRITE(out_RENAME_OUT_NUM_REG_RD_LOG [i], num_reg_rd_log [i]); |
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| 220 | PORT_WRITE(out_RENAME_OUT_NUM_REG_RD_PHY_OLD [i], num_reg_rd_phy_old [i]); |
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| 221 | PORT_WRITE(out_RENAME_OUT_NUM_REG_RD_PHY_NEW [i], num_reg_rd_phy_new [i]); |
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| 222 | PORT_WRITE(out_RENAME_OUT_WRITE_RE [i], write_re [i]); |
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| 223 | PORT_WRITE(out_RENAME_OUT_NUM_REG_RE_LOG [i], num_reg_re_log [i]); |
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| 224 | PORT_WRITE(out_RENAME_OUT_NUM_REG_RE_PHY_OLD [i], num_reg_re_phy_old [i]); |
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| 225 | PORT_WRITE(out_RENAME_OUT_NUM_REG_RE_PHY_NEW [i], num_reg_re_phy_new [i]); |
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| 226 | } |
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[123] | 227 | } |
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[78] | 228 | |
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[88] | 229 | log_end(Dependency_checking_unit,FUNCTION); |
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[78] | 230 | }; |
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| 231 | |
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| 232 | }; // end namespace dependency_checking_unit |
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| 233 | }; // end namespace register_translation_unit |
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| 234 | }; // end namespace rename_unit |
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| 235 | }; // end namespace ooo_engine |
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| 236 | }; // end namespace multi_ooo_engine |
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| 237 | }; // end namespace core |
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| 238 | }; // end namespace behavioural |
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| 239 | }; // end namespace morpheo |
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| 240 | #endif |
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