1 | #ifdef SYSTEMC |
---|
2 | /* |
---|
3 | * $Id$ |
---|
4 | * |
---|
5 | * [ Description ] |
---|
6 | * |
---|
7 | */ |
---|
8 | |
---|
9 | #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/include/Dependency_checking_unit.h" |
---|
10 | |
---|
11 | namespace morpheo { |
---|
12 | namespace behavioural { |
---|
13 | namespace core { |
---|
14 | namespace multi_ooo_engine { |
---|
15 | namespace ooo_engine { |
---|
16 | namespace rename_unit { |
---|
17 | namespace register_translation_unit { |
---|
18 | namespace dependency_checking_unit { |
---|
19 | |
---|
20 | |
---|
21 | #undef FUNCTION |
---|
22 | #define FUNCTION "Dependency_checking_unit::genMealy" |
---|
23 | void Dependency_checking_unit::genMealy (void) |
---|
24 | { |
---|
25 | log_printf(FUNC,Dependency_checking_unit,FUNCTION,"Begin"); |
---|
26 | |
---|
27 | // Tcontrol_t val [_param->_nb_inst_insert]; |
---|
28 | // Tcontrol_t ack [_param->_nb_inst_insert]; |
---|
29 | Tcontext_t front_end_id [_param->_nb_inst_insert]; |
---|
30 | Tcontext_t context_id [_param->_nb_inst_insert]; |
---|
31 | Tcontrol_t read_ra [_param->_nb_inst_insert]; |
---|
32 | Tgeneral_address_t num_reg_ra_log [_param->_nb_inst_insert]; |
---|
33 | Tgeneral_address_t num_reg_ra_phy [_param->_nb_inst_insert]; |
---|
34 | Tcontrol_t read_rb [_param->_nb_inst_insert]; |
---|
35 | Tgeneral_address_t num_reg_rb_log [_param->_nb_inst_insert]; |
---|
36 | Tgeneral_address_t num_reg_rb_phy [_param->_nb_inst_insert]; |
---|
37 | Tcontrol_t read_rc [_param->_nb_inst_insert]; |
---|
38 | Tspecial_address_t num_reg_rc_log [_param->_nb_inst_insert]; |
---|
39 | Tspecial_address_t num_reg_rc_phy [_param->_nb_inst_insert]; |
---|
40 | Tcontrol_t write_rd [_param->_nb_inst_insert]; |
---|
41 | Tgeneral_address_t num_reg_rd_log [_param->_nb_inst_insert]; |
---|
42 | Tgeneral_address_t num_reg_rd_phy_old [_param->_nb_inst_insert]; |
---|
43 | Tgeneral_address_t num_reg_rd_phy_new [_param->_nb_inst_insert]; |
---|
44 | Tcontrol_t write_re [_param->_nb_inst_insert]; |
---|
45 | Tspecial_address_t num_reg_re_log [_param->_nb_inst_insert]; |
---|
46 | Tspecial_address_t num_reg_re_phy_old [_param->_nb_inst_insert]; |
---|
47 | Tspecial_address_t num_reg_re_phy_new [_param->_nb_inst_insert]; |
---|
48 | |
---|
49 | // 4 dependency : |
---|
50 | // * Read after Read : it's a false dependency |
---|
51 | // * Write after Read : it's inhibt by rename process |
---|
52 | // * Write after Write : for the num_reg_old |
---|
53 | // * Read after Write : dependency |
---|
54 | for (uint32_t i=0; i<_param->_nb_inst_insert; i++) |
---|
55 | { |
---|
56 | // =====[ Input ]================================================== |
---|
57 | // val [i] = PORT_READ(in_RENAME_IN_VAL [i]); |
---|
58 | // ack [i] = PORT_READ(in_RENAME_OUT_ACK [i]); |
---|
59 | front_end_id [i] = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_IN_FRONT_END_ID [i]):0; |
---|
60 | context_id [i] = (_param->_have_port_context_id )?PORT_READ(in_RENAME_IN_CONTEXT_ID [i]):0; |
---|
61 | read_ra [i] = PORT_READ(in_RENAME_IN_READ_RA [i]); |
---|
62 | num_reg_ra_log [i] = PORT_READ(in_RENAME_IN_NUM_REG_RA_LOG [i]); |
---|
63 | num_reg_ra_phy [i] = PORT_READ(in_RENAME_IN_NUM_REG_RA_PHY [i]); |
---|
64 | read_rb [i] = PORT_READ(in_RENAME_IN_READ_RB [i]); |
---|
65 | num_reg_rb_log [i] = PORT_READ(in_RENAME_IN_NUM_REG_RB_LOG [i]); |
---|
66 | num_reg_rb_phy [i] = PORT_READ(in_RENAME_IN_NUM_REG_RB_PHY [i]); |
---|
67 | read_rc [i] = PORT_READ(in_RENAME_IN_READ_RC [i]); |
---|
68 | num_reg_rc_log [i] = PORT_READ(in_RENAME_IN_NUM_REG_RC_LOG [i]); |
---|
69 | num_reg_rc_phy [i] = PORT_READ(in_RENAME_IN_NUM_REG_RC_PHY [i]); |
---|
70 | write_rd [i] = PORT_READ(in_RENAME_IN_WRITE_RD [i]); |
---|
71 | num_reg_rd_log [i] = PORT_READ(in_RENAME_IN_NUM_REG_RD_LOG [i]); |
---|
72 | num_reg_rd_phy_old [i] = PORT_READ(in_RENAME_IN_NUM_REG_RD_PHY_OLD [i]); |
---|
73 | num_reg_rd_phy_new [i] = PORT_READ(in_RENAME_IN_NUM_REG_RD_PHY_NEW [i]); |
---|
74 | write_re [i] = PORT_READ(in_RENAME_IN_WRITE_RE [i]); |
---|
75 | num_reg_re_log [i] = PORT_READ(in_RENAME_IN_NUM_REG_RE_LOG [i]); |
---|
76 | num_reg_re_phy_old [i] = PORT_READ(in_RENAME_IN_NUM_REG_RE_PHY_OLD [i]); |
---|
77 | num_reg_re_phy_new [i] = PORT_READ(in_RENAME_IN_NUM_REG_RE_PHY_NEW [i]); |
---|
78 | |
---|
79 | // ================================================================ |
---|
80 | // =====[ Write after Write ]====================================== |
---|
81 | // ================================================================ |
---|
82 | if (write_rd [i]) |
---|
83 | // Inverse scan : with x < y, instruction x is before in the sequential order program that the instruction y |
---|
84 | for (int32_t j=i-1; j>=0; j--) |
---|
85 | if ((write_rd [j] == 1 ) and |
---|
86 | (num_reg_rd_log [j] == num_reg_rd_log [i]) and |
---|
87 | (front_end_id [j] == front_end_id [i]) and |
---|
88 | (context_id [j] == context_id [i]) ) |
---|
89 | { |
---|
90 | num_reg_rd_phy_old [i] = num_reg_rd_phy_new [j]; |
---|
91 | break; // find the most recently dependency |
---|
92 | } |
---|
93 | |
---|
94 | if (write_re [i]) |
---|
95 | // Inverse scan : with x < y, instruction x is before in the sequential order program that the instruction y |
---|
96 | for (int32_t j=i-1; j>=0; j--) |
---|
97 | if ((write_re [j] == 1 ) and |
---|
98 | (num_reg_re_log [j] == num_reg_re_log [i]) and |
---|
99 | (front_end_id [j] == front_end_id [i]) and |
---|
100 | (context_id [j] == context_id [i]) ) |
---|
101 | { |
---|
102 | num_reg_re_phy_old [i] = num_reg_re_phy_new [j]; |
---|
103 | break; // find the most recently dependency |
---|
104 | } |
---|
105 | // ================================================================ |
---|
106 | // =====[ Read after Write ]====================================== |
---|
107 | // ================================================================ |
---|
108 | if (read_ra [i]) |
---|
109 | // Inverse scan : with x < y, instruction x is before in the sequential order program that the instruction y |
---|
110 | for (int32_t j=i-1; j>=0; j--) |
---|
111 | if ((write_rd [j] == 1 ) and |
---|
112 | (num_reg_rd_log [j] == num_reg_ra_log [i]) and |
---|
113 | (front_end_id [j] == front_end_id [i]) and |
---|
114 | (context_id [j] == context_id [i]) ) |
---|
115 | { |
---|
116 | num_reg_ra_phy [i] = num_reg_rd_phy_new [j]; |
---|
117 | break; // find the most recently dependency |
---|
118 | } |
---|
119 | |
---|
120 | if (read_rb [i]) |
---|
121 | // Inverse scan : with x < y, instruction x is before in the sequential order program that the instruction y |
---|
122 | for (int32_t j=i-1; j>=0; j--) |
---|
123 | if ((write_rd [j] == 1 ) and |
---|
124 | (num_reg_rd_log [j] == num_reg_rb_log [i]) and |
---|
125 | (front_end_id [j] == front_end_id [i]) and |
---|
126 | (context_id [j] == context_id [i]) ) |
---|
127 | { |
---|
128 | num_reg_rb_phy [i] = num_reg_rd_phy_new [j]; |
---|
129 | break; // find the most recently dependency |
---|
130 | } |
---|
131 | |
---|
132 | if (read_rc [i]) |
---|
133 | // Inverse scan : with x < y, instruction x is before in the sequential order program that the instruction y |
---|
134 | for (int32_t j=i-1; j>=0; j--) |
---|
135 | if ((write_re [j] == 1 ) and |
---|
136 | (num_reg_re_log [j] == num_reg_rc_log [i]) and |
---|
137 | (front_end_id [j] == front_end_id [i]) and |
---|
138 | (context_id [j] == context_id [i]) ) |
---|
139 | { |
---|
140 | num_reg_rc_phy [i] = num_reg_re_phy_new [j]; |
---|
141 | break; // find the most recently dependency |
---|
142 | } |
---|
143 | |
---|
144 | // =====[ Output ]================================================= |
---|
145 | // PORT_WRITE(out_RENAME_OUT_VAL [i], val [i]); |
---|
146 | // PORT_WRITE(out_RENAME_IN_ACK [i], ack [i]); |
---|
147 | if (_param->_have_port_front_end_id) |
---|
148 | PORT_WRITE(out_RENAME_OUT_FRONT_END_ID [i], front_end_id [i]); |
---|
149 | if (_param->_have_port_context_id) |
---|
150 | PORT_WRITE(out_RENAME_OUT_CONTEXT_ID [i], context_id [i]); |
---|
151 | PORT_WRITE(out_RENAME_OUT_READ_RA [i], read_ra [i]); |
---|
152 | PORT_WRITE(out_RENAME_OUT_NUM_REG_RA_LOG [i], num_reg_ra_log [i]); |
---|
153 | PORT_WRITE(out_RENAME_OUT_NUM_REG_RA_PHY [i], num_reg_ra_phy [i]); |
---|
154 | PORT_WRITE(out_RENAME_OUT_READ_RB [i], read_rb [i]); |
---|
155 | PORT_WRITE(out_RENAME_OUT_NUM_REG_RB_LOG [i], num_reg_rb_log [i]); |
---|
156 | PORT_WRITE(out_RENAME_OUT_NUM_REG_RB_PHY [i], num_reg_rb_phy [i]); |
---|
157 | PORT_WRITE(out_RENAME_OUT_READ_RC [i], read_rc [i]); |
---|
158 | PORT_WRITE(out_RENAME_OUT_NUM_REG_RC_LOG [i], num_reg_rc_log [i]); |
---|
159 | PORT_WRITE(out_RENAME_OUT_NUM_REG_RC_PHY [i], num_reg_rc_phy [i]); |
---|
160 | PORT_WRITE(out_RENAME_OUT_WRITE_RD [i], write_rd [i]); |
---|
161 | PORT_WRITE(out_RENAME_OUT_NUM_REG_RD_LOG [i], num_reg_rd_log [i]); |
---|
162 | PORT_WRITE(out_RENAME_OUT_NUM_REG_RD_PHY_OLD [i], num_reg_rd_phy_old [i]); |
---|
163 | PORT_WRITE(out_RENAME_OUT_NUM_REG_RD_PHY_NEW [i], num_reg_rd_phy_new [i]); |
---|
164 | PORT_WRITE(out_RENAME_OUT_WRITE_RE [i], write_re [i]); |
---|
165 | PORT_WRITE(out_RENAME_OUT_NUM_REG_RE_LOG [i], num_reg_re_log [i]); |
---|
166 | PORT_WRITE(out_RENAME_OUT_NUM_REG_RE_PHY_OLD [i], num_reg_re_phy_old [i]); |
---|
167 | PORT_WRITE(out_RENAME_OUT_NUM_REG_RE_PHY_NEW [i], num_reg_re_phy_new [i]); |
---|
168 | } |
---|
169 | |
---|
170 | log_printf(FUNC,Dependency_checking_unit,FUNCTION,"End"); |
---|
171 | }; |
---|
172 | |
---|
173 | }; // end namespace dependency_checking_unit |
---|
174 | }; // end namespace register_translation_unit |
---|
175 | }; // end namespace rename_unit |
---|
176 | }; // end namespace ooo_engine |
---|
177 | }; // end namespace multi_ooo_engine |
---|
178 | }; // end namespace core |
---|
179 | }; // end namespace behavioural |
---|
180 | }; // end namespace morpheo |
---|
181 | #endif |
---|