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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/src/Dependency_checking_unit_genMealy.cpp @ 88

Last change on this file since 88 was 88, checked in by rosiere, 16 years ago
Almost complete design with Test and test platform
Property svn:keywords set to `Id`
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1	#ifdef SYSTEMC
2	/*
3	* $Id: Dependency_checking_unit_genMealy.cpp 88 2008-12-10 18:31:39Z rosiere $
4	*
5	* [ Description ]
6	*
7	*/
8
9	#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/include/Dependency_checking_unit.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_ooo_engine {
15	namespace ooo_engine {
16	namespace rename_unit {
17	namespace register_translation_unit {
18	namespace dependency_checking_unit {
19
20
21	#undef FUNCTION
22	#define FUNCTION "Dependency_checking_unit::genMealy"
23	void Dependency_checking_unit::genMealy (void)
24	{
25	log_begin(Dependency_checking_unit,FUNCTION);
26	log_function(Dependency_checking_unit,FUNCTION,_name.c_str());
27
28	// Tcontrol_t val [_param->_nb_inst_insert];
29	// Tcontrol_t ack [_param->_nb_inst_insert];
30	Tcontext_t front_end_id [_param->_nb_inst_insert];
31	Tcontext_t context_id [_param->_nb_inst_insert];
32	Tcontrol_t read_ra [_param->_nb_inst_insert];
33	Tgeneral_address_t num_reg_ra_log [_param->_nb_inst_insert];
34	Tgeneral_address_t num_reg_ra_phy [_param->_nb_inst_insert];
35	Tcontrol_t read_rb [_param->_nb_inst_insert];
36	Tgeneral_address_t num_reg_rb_log [_param->_nb_inst_insert];
37	Tgeneral_address_t num_reg_rb_phy [_param->_nb_inst_insert];
38	Tcontrol_t read_rc [_param->_nb_inst_insert];
39	Tspecial_address_t num_reg_rc_log [_param->_nb_inst_insert];
40	Tspecial_address_t num_reg_rc_phy [_param->_nb_inst_insert];
41	Tcontrol_t write_rd [_param->_nb_inst_insert];
42	Tgeneral_address_t num_reg_rd_log [_param->_nb_inst_insert];
43	Tgeneral_address_t num_reg_rd_phy_old [_param->_nb_inst_insert];
44	Tgeneral_address_t num_reg_rd_phy_new [_param->_nb_inst_insert];
45	Tcontrol_t write_re [_param->_nb_inst_insert];
46	Tspecial_address_t num_reg_re_log [_param->_nb_inst_insert];
47	Tspecial_address_t num_reg_re_phy_old [_param->_nb_inst_insert];
48	Tspecial_address_t num_reg_re_phy_new [_param->_nb_inst_insert];
49
50	// 4 dependency :
51	// * Read after Read : it's a false dependency
52	// * Write after Read : it's inhibt by rename process
53	// * Write after Write : for the num_reg_old
54	// * Read after Write : dependency
55	for (uint32_t i=0; i<_param->_nb_inst_insert; i++)
56	{
57	// =====[ Input ]==================================================
58	// val [i] = PORT_READ(in_RENAME_IN_VAL [i]);
59	// ack [i] = PORT_READ(in_RENAME_OUT_ACK [i]);
60	front_end_id [i] = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_IN_FRONT_END_ID [i]):0;
61	context_id [i] = (_param->_have_port_context_id )?PORT_READ(in_RENAME_IN_CONTEXT_ID [i]):0;
62	read_ra [i] = PORT_READ(in_RENAME_IN_READ_RA [i]);
63	num_reg_ra_log [i] = PORT_READ(in_RENAME_IN_NUM_REG_RA_LOG [i]);
64	num_reg_ra_phy [i] = PORT_READ(in_RENAME_IN_NUM_REG_RA_PHY [i]);
65	read_rb [i] = PORT_READ(in_RENAME_IN_READ_RB [i]);
66	num_reg_rb_log [i] = PORT_READ(in_RENAME_IN_NUM_REG_RB_LOG [i]);
67	num_reg_rb_phy [i] = PORT_READ(in_RENAME_IN_NUM_REG_RB_PHY [i]);
68	read_rc [i] = PORT_READ(in_RENAME_IN_READ_RC [i]);
69	num_reg_rc_log [i] = PORT_READ(in_RENAME_IN_NUM_REG_RC_LOG [i]);
70	num_reg_rc_phy [i] = PORT_READ(in_RENAME_IN_NUM_REG_RC_PHY [i]);
71	write_rd [i] = PORT_READ(in_RENAME_IN_WRITE_RD [i]);
72	num_reg_rd_log [i] = PORT_READ(in_RENAME_IN_NUM_REG_RD_LOG [i]);
73	num_reg_rd_phy_old [i] = PORT_READ(in_RENAME_IN_NUM_REG_RD_PHY_OLD [i]);
74	num_reg_rd_phy_new [i] = PORT_READ(in_RENAME_IN_NUM_REG_RD_PHY_NEW [i]);
75	write_re [i] = PORT_READ(in_RENAME_IN_WRITE_RE [i]);
76	num_reg_re_log [i] = PORT_READ(in_RENAME_IN_NUM_REG_RE_LOG [i]);
77	num_reg_re_phy_old [i] = PORT_READ(in_RENAME_IN_NUM_REG_RE_PHY_OLD [i]);
78	num_reg_re_phy_new [i] = PORT_READ(in_RENAME_IN_NUM_REG_RE_PHY_NEW [i]);
79
80	log_printf(TRACE,Dependency_checking_unit,FUNCTION," * (before) [%d] %.2d %.2d, %.1d %.2d %.5d, %.1d %.2d %.5d, %.1d %.2d %.5d, %.1d %.2d %.5d -> %.5d, %.1d %.2d %.5d -> %.5d",
81	i,
82	front_end_id [i],
83	context_id [i],
84	read_ra [i],
85	num_reg_ra_log [i],
86	num_reg_ra_phy [i],
87	read_rb [i],
88	num_reg_rb_log [i],
89	num_reg_rb_phy [i],
90	read_rc [i],
91	num_reg_rc_log [i],
92	num_reg_rc_phy [i],
93	write_rd [i],
94	num_reg_rd_log [i],
95	num_reg_rd_phy_old [i],
96	num_reg_rd_phy_new [i],
97	write_re [i],
98	num_reg_re_log [i],
99	num_reg_re_phy_old [i],
100	num_reg_re_phy_new [i]);
101
102	// ================================================================
103	// =====[ Write after Write ]======================================
104	// ================================================================
105	if (write_rd [i])
106	// Inverse scan : with x < y, instruction x is before in the sequential order program that the instruction y
107	for (int32_t j=i-1; j>=0; j--)
108	if ((write_rd [j] == 1 ) and
109	(num_reg_rd_log [j] == num_reg_rd_log [i]) and
110	(front_end_id [j] == front_end_id [i]) and
111	(context_id [j] == context_id [i]) )
112	{
113	log_printf(TRACE,Dependency_checking_unit,FUNCTION," * RD : WAW dependency with inst[%d].RD",j);
114	num_reg_rd_phy_old [i] = num_reg_rd_phy_new [j];
115	break; // find the most recently dependency
116	}
117
118	if (write_re [i])
119	// Inverse scan : with x < y, instruction x is before in the sequential order program that the instruction y
120	for (int32_t j=i-1; j>=0; j--)
121	if ((write_re [j] == 1 ) and
122	(num_reg_re_log [j] == num_reg_re_log [i]) and
123	(front_end_id [j] == front_end_id [i]) and
124	(context_id [j] == context_id [i]) )
125	{
126	log_printf(TRACE,Dependency_checking_unit,FUNCTION," * RE : WAW dependency with inst[%d].RE",j);
127	num_reg_re_phy_old [i] = num_reg_re_phy_new [j];
128	break; // find the most recently dependency
129	}
130	// ================================================================
131	// =====[ Read after Write ]======================================
132	// ================================================================
133	if (read_ra [i])
134	// Inverse scan : with x < y, instruction x is before in the sequential order program that the instruction y
135	for (int32_t j=i-1; j>=0; j--)
136	if ((write_rd [j] == 1 ) and
137	(num_reg_rd_log [j] == num_reg_ra_log [i]) and
138	(front_end_id [j] == front_end_id [i]) and
139	(context_id [j] == context_id [i]) )
140	{
141	log_printf(TRACE,Dependency_checking_unit,FUNCTION," * RA : RAW dependency with inst[%d].RD",j);
142	num_reg_ra_phy [i] = num_reg_rd_phy_new [j];
143	break; // find the most recently dependency
144	}
145
146	if (read_rb [i])
147	// Inverse scan : with x < y, instruction x is before in the sequential order program that the instruction y
148	for (int32_t j=i-1; j>=0; j--)
149	if ((write_rd [j] == 1 ) and
150	(num_reg_rd_log [j] == num_reg_rb_log [i]) and
151	(front_end_id [j] == front_end_id [i]) and
152	(context_id [j] == context_id [i]) )
153	{
154	log_printf(TRACE,Dependency_checking_unit,FUNCTION," * RB : RAW dependency with inst[%d].RD",j);
155	num_reg_rb_phy [i] = num_reg_rd_phy_new [j];
156	break; // find the most recently dependency
157	}
158
159	if (read_rc [i])
160	// Inverse scan : with x < y, instruction x is before in the sequential order program that the instruction y
161	for (int32_t j=i-1; j>=0; j--)
162	if ((write_re [j] == 1 ) and
163	(num_reg_re_log [j] == num_reg_rc_log [i]) and
164	(front_end_id [j] == front_end_id [i]) and
165	(context_id [j] == context_id [i]) )
166	{
167	log_printf(TRACE,Dependency_checking_unit,FUNCTION," * RC : RAW dependency with inst[%d].RE",j);
168	num_reg_rc_phy [i] = num_reg_re_phy_new [j];
169	break; // find the most recently dependency
170	}
171
172	log_printf(TRACE,Dependency_checking_unit,FUNCTION," * (after ) [%d] %.2d %.2d, %.1d %.2d %.5d, %.1d %.2d %.5d, %.1d %.2d %.5d, %.1d %.2d %.5d -> %.5d, %.1d %.2d %.5d -> %.5d",
173	i,
174	front_end_id [i],
175	context_id [i],
176	read_ra [i],
177	num_reg_ra_log [i],
178	num_reg_ra_phy [i],
179	read_rb [i],
180	num_reg_rb_log [i],
181	num_reg_rb_phy [i],
182	read_rc [i],
183	num_reg_rc_log [i],
184	num_reg_rc_phy [i],
185	write_rd [i],
186	num_reg_rd_log [i],
187	num_reg_rd_phy_old [i],
188	num_reg_rd_phy_new [i],
189	write_re [i],
190	num_reg_re_log [i],
191	num_reg_re_phy_old [i],
192	num_reg_re_phy_new [i]);
193
194	// =====[ Output ]=================================================
195	// PORT_WRITE(out_RENAME_OUT_VAL [i], val [i]);
196	// PORT_WRITE(out_RENAME_IN_ACK [i], ack [i]);
197	if (_param->_have_port_front_end_id)
198	PORT_WRITE(out_RENAME_OUT_FRONT_END_ID [i], front_end_id [i]);
199	if (_param->_have_port_context_id)
200	PORT_WRITE(out_RENAME_OUT_CONTEXT_ID [i], context_id [i]);
201	PORT_WRITE(out_RENAME_OUT_READ_RA [i], read_ra [i]);
202	PORT_WRITE(out_RENAME_OUT_NUM_REG_RA_LOG [i], num_reg_ra_log [i]);
203	PORT_WRITE(out_RENAME_OUT_NUM_REG_RA_PHY [i], num_reg_ra_phy [i]);
204	PORT_WRITE(out_RENAME_OUT_READ_RB [i], read_rb [i]);
205	PORT_WRITE(out_RENAME_OUT_NUM_REG_RB_LOG [i], num_reg_rb_log [i]);
206	PORT_WRITE(out_RENAME_OUT_NUM_REG_RB_PHY [i], num_reg_rb_phy [i]);
207	PORT_WRITE(out_RENAME_OUT_READ_RC [i], read_rc [i]);
208	PORT_WRITE(out_RENAME_OUT_NUM_REG_RC_LOG [i], num_reg_rc_log [i]);
209	PORT_WRITE(out_RENAME_OUT_NUM_REG_RC_PHY [i], num_reg_rc_phy [i]);
210	PORT_WRITE(out_RENAME_OUT_WRITE_RD [i], write_rd [i]);
211	PORT_WRITE(out_RENAME_OUT_NUM_REG_RD_LOG [i], num_reg_rd_log [i]);
212	PORT_WRITE(out_RENAME_OUT_NUM_REG_RD_PHY_OLD [i], num_reg_rd_phy_old [i]);
213	PORT_WRITE(out_RENAME_OUT_NUM_REG_RD_PHY_NEW [i], num_reg_rd_phy_new [i]);
214	PORT_WRITE(out_RENAME_OUT_WRITE_RE [i], write_re [i]);
215	PORT_WRITE(out_RENAME_OUT_NUM_REG_RE_LOG [i], num_reg_re_log [i]);
216	PORT_WRITE(out_RENAME_OUT_NUM_REG_RE_PHY_OLD [i], num_reg_re_phy_old [i]);
217	PORT_WRITE(out_RENAME_OUT_NUM_REG_RE_PHY_NEW [i], num_reg_re_phy_new [i]);
218	}
219
220	log_end(Dependency_checking_unit,FUNCTION);
221	};
222
223	}; // end namespace dependency_checking_unit
224	}; // end namespace register_translation_unit
225	}; // end namespace rename_unit
226	}; // end namespace ooo_engine
227	}; // end namespace multi_ooo_engine
228	}; // end namespace core
229	}; // end namespace behavioural
230	}; // end namespace morpheo
231	#endif

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