1 | #ifdef SYSTEMC |
---|
2 | /* |
---|
3 | * $Id: Free_List_unit_genMealy_pop.cpp 123 2009-06-08 20:43:30Z rosiere $ |
---|
4 | * |
---|
5 | * [ Description ] |
---|
6 | * |
---|
7 | */ |
---|
8 | |
---|
9 | #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/include/Free_List_unit.h" |
---|
10 | |
---|
11 | namespace morpheo { |
---|
12 | namespace behavioural { |
---|
13 | namespace core { |
---|
14 | namespace multi_ooo_engine { |
---|
15 | namespace ooo_engine { |
---|
16 | namespace rename_unit { |
---|
17 | namespace register_translation_unit { |
---|
18 | namespace free_list_unit { |
---|
19 | |
---|
20 | |
---|
21 | #undef FUNCTION |
---|
22 | #define FUNCTION "Free_List_unit::genMealy_pop" |
---|
23 | void Free_List_unit::genMealy_pop (void) |
---|
24 | { |
---|
25 | log_begin(Free_List_unit,FUNCTION); |
---|
26 | log_function(Free_List_unit,FUNCTION,_name.c_str()); |
---|
27 | |
---|
28 | if (PORT_READ(in_NRESET)) |
---|
29 | { |
---|
30 | std::list<generic::priority::select_t> * select_gpr = _priority_gpr->select(); |
---|
31 | std::list<generic::priority::select_t>::iterator it_gpr=select_gpr->begin(); |
---|
32 | |
---|
33 | std::list<generic::priority::select_t> * select_spr = _priority_spr->select(); |
---|
34 | std::list<generic::priority::select_t>::iterator it_spr=select_spr->begin(); |
---|
35 | |
---|
36 | for (uint32_t i=0; i<_param->_nb_pop; i++) |
---|
37 | { |
---|
38 | log_printf(TRACE,Free_List_unit,FUNCTION," * POP [%d]",i); |
---|
39 | |
---|
40 | // GPR |
---|
41 | bool gpr_ack = not PORT_READ(in_POP_GPR_VAL[i]); |
---|
42 | |
---|
43 | log_printf(TRACE,Free_List_unit,FUNCTION," * GPR_VAL : %d",PORT_READ(in_POP_GPR_VAL[i])); |
---|
44 | |
---|
45 | if (not gpr_ack) |
---|
46 | { |
---|
47 | // scan all bank |
---|
48 | for (; |
---|
49 | it_gpr!=select_gpr->end(); |
---|
50 | ++it_gpr) |
---|
51 | { |
---|
52 | uint32_t num_bank = it_gpr->grp; |
---|
53 | |
---|
54 | log_printf(TRACE,Free_List_unit,FUNCTION," * num_bank: %d",num_bank); |
---|
55 | |
---|
56 | if (not _gpr_list[num_bank].empty()) |
---|
57 | { |
---|
58 | // find |
---|
59 | log_printf(TRACE,Free_List_unit,FUNCTION," * find : %d",_gpr_list[num_bank].front()); |
---|
60 | |
---|
61 | gpr_ack = true; |
---|
62 | internal_POP_GPR_BANK [i] = num_bank; |
---|
63 | PORT_WRITE(out_POP_GPR_NUM_REG [i], |
---|
64 | //(num_bank << _param->_shift) | // only in VHDL |
---|
65 | _gpr_list[num_bank].front()); |
---|
66 | |
---|
67 | ++it_gpr; |
---|
68 | break; |
---|
69 | } |
---|
70 | } |
---|
71 | } |
---|
72 | |
---|
73 | // SPR |
---|
74 | bool spr_ack = not PORT_READ(in_POP_SPR_VAL[i]); |
---|
75 | |
---|
76 | log_printf(TRACE,Free_List_unit,FUNCTION," * SPR_VAL : %d",PORT_READ(in_POP_SPR_VAL[i])); |
---|
77 | |
---|
78 | if (not spr_ack) |
---|
79 | { |
---|
80 | // scan all bank |
---|
81 | for (; |
---|
82 | it_spr!=select_spr->end(); |
---|
83 | ++it_spr) |
---|
84 | { |
---|
85 | uint32_t num_bank = it_spr->grp; |
---|
86 | |
---|
87 | log_printf(TRACE,Free_List_unit,FUNCTION," * num_bank: %d",num_bank); |
---|
88 | |
---|
89 | if (not _spr_list[num_bank].empty()) |
---|
90 | { |
---|
91 | // find |
---|
92 | log_printf(TRACE,Free_List_unit,FUNCTION," * find : %d",_spr_list[num_bank].front()); |
---|
93 | |
---|
94 | spr_ack = true; |
---|
95 | internal_POP_SPR_BANK [i] = num_bank; |
---|
96 | PORT_WRITE(out_POP_SPR_NUM_REG [i], |
---|
97 | //(num_bank << _param->_shift) | // only in VHDL |
---|
98 | _spr_list[num_bank].front()); |
---|
99 | |
---|
100 | ++it_spr; |
---|
101 | break; |
---|
102 | } |
---|
103 | } |
---|
104 | } |
---|
105 | |
---|
106 | |
---|
107 | internal_POP_ACK [i] = gpr_ack and spr_ack; |
---|
108 | } |
---|
109 | |
---|
110 | // for (uint32_t i=0; i<_param->_nb_pop; i++) |
---|
111 | // { |
---|
112 | // log_printf(TRACE,Free_List_unit,FUNCTION," * POP [%d]",i); |
---|
113 | |
---|
114 | // uint32_t offset = (i*_param->_nb_bank_by_pop) + reg_BANK_PRIORITY; |
---|
115 | |
---|
116 | // // GPR |
---|
117 | // bool gpr_ack = not PORT_READ(in_POP_GPR_VAL[i]); |
---|
118 | |
---|
119 | // log_printf(TRACE,Free_List_unit,FUNCTION," * GPR_VAL : %d",PORT_READ(in_POP_GPR_VAL[i])); |
---|
120 | |
---|
121 | // if (not gpr_ack) |
---|
122 | // { |
---|
123 | // for (uint32_t j=0; j<_param->_nb_bank_by_pop; j++) |
---|
124 | // { |
---|
125 | // uint32_t bank = (offset+((j+reg_BANK_BY_POP_PRIORITY)%_param->_nb_bank_by_pop))%_param->_nb_bank; |
---|
126 | |
---|
127 | // log_printf(TRACE,Free_List_unit,FUNCTION," * bank : %d",bank); |
---|
128 | |
---|
129 | // if (not _gpr_list[bank].empty()) |
---|
130 | // { |
---|
131 | // // find |
---|
132 | // log_printf(TRACE,Free_List_unit,FUNCTION," * find : %d",_gpr_list[bank].front()); |
---|
133 | |
---|
134 | // gpr_ack = true; |
---|
135 | // internal_POP_GPR_BANK [i] = bank; |
---|
136 | // PORT_WRITE(out_POP_GPR_NUM_REG [i], |
---|
137 | // //(bank << _param->_shift) | // only in VHDL |
---|
138 | // _gpr_list[bank].front()); |
---|
139 | |
---|
140 | // break; |
---|
141 | // } |
---|
142 | // } |
---|
143 | // } |
---|
144 | |
---|
145 | // // SPR |
---|
146 | // bool spr_ack = not PORT_READ(in_POP_SPR_VAL[i]); |
---|
147 | |
---|
148 | // log_printf(TRACE,Free_List_unit,FUNCTION," * SPR_VAL : %d",PORT_READ(in_POP_SPR_VAL[i])); |
---|
149 | |
---|
150 | // if (not spr_ack) |
---|
151 | // { |
---|
152 | // uint32_t offset = (i*_param->_nb_bank_by_pop) + reg_BANK_PRIORITY; |
---|
153 | |
---|
154 | // for (uint32_t j=0; j<_param->_nb_bank_by_pop; j++) |
---|
155 | // { |
---|
156 | // uint32_t bank = (offset+((j+reg_BANK_BY_POP_PRIORITY)%_param->_nb_bank_by_pop))%_param->_nb_bank; |
---|
157 | |
---|
158 | // log_printf(TRACE,Free_List_unit,FUNCTION," * bank : %d",bank); |
---|
159 | |
---|
160 | // if (not _spr_list[bank].empty()) |
---|
161 | // { |
---|
162 | // // find |
---|
163 | // log_printf(TRACE,Free_List_unit,FUNCTION," * find : %d",_spr_list[bank].front()); |
---|
164 | |
---|
165 | // spr_ack = true; |
---|
166 | // internal_POP_SPR_BANK [i] = bank; |
---|
167 | // PORT_WRITE(out_POP_SPR_NUM_REG [i], |
---|
168 | // //(bank << _param->_shift) | // only in VHDL |
---|
169 | // _spr_list[bank].front()); |
---|
170 | |
---|
171 | // break; |
---|
172 | // } |
---|
173 | // } |
---|
174 | // } |
---|
175 | |
---|
176 | // internal_POP_ACK [i] = gpr_ack and spr_ack; |
---|
177 | |
---|
178 | // PORT_WRITE(out_POP_ACK [i], internal_POP_ACK [i]); |
---|
179 | // } |
---|
180 | } |
---|
181 | else |
---|
182 | { |
---|
183 | for (uint32_t i=0; i<_param->_nb_pop; i++) |
---|
184 | internal_POP_ACK [i] = 0; |
---|
185 | } |
---|
186 | |
---|
187 | for (uint32_t i=0; i<_param->_nb_pop; i++) |
---|
188 | PORT_WRITE(out_POP_ACK [i], internal_POP_ACK [i]); |
---|
189 | |
---|
190 | |
---|
191 | log_end(Free_List_unit,FUNCTION); |
---|
192 | }; |
---|
193 | |
---|
194 | }; // end namespace free_list_unit |
---|
195 | }; // end namespace register_translation_unit |
---|
196 | }; // end namespace rename_unit |
---|
197 | }; // end namespace ooo_engine |
---|
198 | }; // end namespace multi_ooo_engine |
---|
199 | }; // end namespace core |
---|
200 | |
---|
201 | }; // end namespace behavioural |
---|
202 | }; // end namespace morpheo |
---|
203 | #endif |
---|