[139] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id: Register_Address_Translation_unit_function_depth_save_genMealy_rename.cpp 145 2010-10-13 18:15:51Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_ooo_engine { |
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| 15 | namespace ooo_engine { |
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| 16 | namespace rename_unit { |
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| 17 | namespace register_translation_unit { |
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| 18 | namespace register_address_translation_unit { |
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| 19 | |
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| 20 | |
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| 21 | #undef FUNCTION |
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| 22 | #define FUNCTION "Register_Address_Translation_unit::function_depth_save_genMealy_rename" |
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| 23 | void Register_Address_Translation_unit::function_depth_save_genMealy_rename (void) |
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| 24 | { |
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| 25 | log_begin(Register_Address_Translation_unit,FUNCTION); |
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| 26 | log_function(Register_Address_Translation_unit,FUNCTION,_name.c_str()); |
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| 27 | |
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| 28 | if (PORT_READ(in_NRESET) != 0) |
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| 29 | { |
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[145] | 30 | bool rat_gpr_speculative_valid [_param->_nb_front_end][_param->_max_nb_context][_param->_max_nb_branch_speculated][_param->_nb_general_register_logic]; |
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| 31 | bool rat_spr_speculative_valid [_param->_nb_front_end][_param->_max_nb_context][_param->_max_nb_branch_speculated][_param->_nb_special_register_logic]; |
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| 32 | // bool reg_save_rat [_param->_nb_front_end][_param->_max_nb_context]; |
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[139] | 33 | |
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| 34 | for (uint32_t i=0; i<_param->_nb_front_end; ++i) |
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| 35 | for (uint32_t j=0; j<_param->_nb_context[i]; ++j) |
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[145] | 36 | { |
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| 37 | // reg_save_rat [i][j] = reg_SAVE_RAT [i][j]; |
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| 38 | for (uint32_t k=0; k<_param->_nb_branch_speculated[i][j]; ++k) |
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| 39 | { |
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| 40 | for (uint32_t l=0; l<_param->_nb_general_register_logic; ++l) |
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| 41 | rat_gpr_speculative_valid [i][j][k][l] = RAT_GPR_SPECULATIVE_VALID [i][j][k][l]; |
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| 42 | for (uint32_t l=0; l<_param->_nb_special_register_logic; ++l) |
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| 43 | rat_spr_speculative_valid [i][j][k][l] = RAT_SPR_SPECULATIVE_VALID [i][j][k][l]; |
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| 44 | } |
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| 45 | } |
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[139] | 46 | |
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| 47 | for (uint32_t i=0; i<_param->_nb_inst_insert; i++) |
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[145] | 48 | { |
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| 49 | if (PORT_READ(in_RENAME_VAL [i])) // not in sensitive list : it's to have valide value to array access |
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| 50 | { |
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| 51 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * RENAME [%d]",i); |
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| 52 | |
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| 53 | Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0; |
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| 54 | Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RENAME_CONTEXT_ID [i]):0; |
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| 55 | |
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| 56 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end_id : %d",front_end_id); |
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| 57 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context_id : %d",context_id); |
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[139] | 58 | |
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[145] | 59 | Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[front_end_id][context_id]):0; |
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| 60 | Tdepth_t depth_max = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[front_end_id][context_id]):0; |
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| 61 | Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL [front_end_id][context_id]); |
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[139] | 62 | |
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[145] | 63 | Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_RENAME_DEPTH [i]):0; |
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| 64 | // Tcontrol_t save_rat = PORT_READ(in_RENAME_SAVE_RAT [i]); |
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| 65 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth/min/max/full : %d - [%d:%d] - %d",depth,depth_min,depth_max,depth_full); |
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| 66 | // log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * save_rat (new) : %d",save_rat); |
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| 67 | // log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * save_rat (old) : %d",reg_save_rat [front_end_id][context_id]); |
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| 68 | |
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| 69 | // if (reg_save_rat [front_end_id][context_id]) |
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| 70 | // { |
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| 71 | // for (uint32_t num_reg_log=0; num_reg_log<_param->_nb_general_register_logic; num_reg_log++) |
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| 72 | // rat_gpr_speculative_valid [front_end_id][context_id][depth][num_reg_log] = false; |
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| 73 | // for (uint32_t num_reg_log=0; num_reg_log<_param->_nb_special_register_logic; num_reg_log++) |
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| 74 | // rat_spr_speculative_valid [front_end_id][context_id][depth][num_reg_log] = false; |
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| 75 | // } |
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| 76 | |
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| 77 | // reg_save_rat[front_end_id][context_id] = save_rat; |
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| 78 | |
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| 79 | Tgeneral_address_t num_reg_ra_log = PORT_READ(in_RENAME_NUM_REG_RA_LOG [i]); //%_param->_nb_general_register; |
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| 80 | Tgeneral_address_t num_reg_rb_log = PORT_READ(in_RENAME_NUM_REG_RB_LOG [i]); //%_param->_nb_general_register; |
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| 81 | Tspecial_address_t num_reg_rc_log = PORT_READ(in_RENAME_NUM_REG_RC_LOG [i]); //%_param->_nb_special_register; |
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| 82 | Tgeneral_address_t num_reg_rd_log = PORT_READ(in_RENAME_NUM_REG_RD_LOG [i]); //%_param->_nb_general_register; |
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| 83 | Tspecial_address_t num_reg_re_log = PORT_READ(in_RENAME_NUM_REG_RE_LOG [i]); //%_param->_nb_special_register; |
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| 84 | |
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| 85 | Tgeneral_address_t num_reg_ra_phy ; |
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| 86 | Tgeneral_address_t num_reg_rb_phy ; |
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| 87 | Tspecial_address_t num_reg_rc_phy ; |
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| 88 | Tgeneral_address_t num_reg_rd_phy_old; |
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| 89 | Tspecial_address_t num_reg_re_phy_old; |
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| 90 | |
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| 91 | bool find_ra = false; |
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| 92 | bool find_rb = false; |
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| 93 | bool find_rc = false; |
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| 94 | bool find_rd = false; |
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| 95 | bool find_re = false; |
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| 96 | |
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| 97 | for (uint32_t num_branch=0; num_branch<_param->_nb_branch_speculated[front_end_id][context_id]; ++num_branch) |
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| 98 | { |
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| 99 | uint32_t index = (depth-num_branch)%_param->_nb_branch_speculated[front_end_id][context_id]; |
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[139] | 100 | |
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[145] | 101 | if (not find_ra and rat_gpr_speculative_valid [front_end_id][context_id][index][num_reg_ra_log]) |
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| 102 | { |
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| 103 | find_ra = true; |
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| 104 | num_reg_ra_phy = RAT_GPR_SPECULATIVE[front_end_id][context_id][index][num_reg_ra_log]; |
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| 105 | } |
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| 106 | |
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| 107 | if (not find_rb and rat_gpr_speculative_valid [front_end_id][context_id][index][num_reg_rb_log]) |
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| 108 | { |
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| 109 | find_rb = true; |
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| 110 | num_reg_rb_phy = RAT_GPR_SPECULATIVE[front_end_id][context_id][index][num_reg_rb_log]; |
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| 111 | } |
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| 112 | |
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| 113 | if (not find_rc and rat_spr_speculative_valid [front_end_id][context_id][index][num_reg_rc_log]) |
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| 114 | { |
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| 115 | find_rc = true; |
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| 116 | num_reg_rc_phy = RAT_SPR_SPECULATIVE[front_end_id][context_id][index][num_reg_rc_log]; |
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| 117 | } |
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| 118 | |
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| 119 | if (not find_rd and rat_gpr_speculative_valid [front_end_id][context_id][index][num_reg_rd_log]) |
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| 120 | { |
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| 121 | find_rd = true; |
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| 122 | num_reg_rd_phy_old = RAT_GPR_SPECULATIVE[front_end_id][context_id][index][num_reg_rd_log]; |
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| 123 | } |
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| 124 | |
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| 125 | if (not find_re and rat_spr_speculative_valid [front_end_id][context_id][index][num_reg_re_log]) |
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| 126 | { |
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| 127 | find_re = true; |
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| 128 | num_reg_re_phy_old = RAT_SPR_SPECULATIVE[front_end_id][context_id][index][num_reg_re_log]; |
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| 129 | } |
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[139] | 130 | |
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[145] | 131 | // if index == depth_min, stop because depth_min is the not speculative. |
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| 132 | // if (index == depth_min) |
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| 133 | // break; |
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| 134 | } |
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| 135 | |
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| 136 | if (not find_ra) |
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| 137 | num_reg_ra_phy = RAT_GPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_ra_log]; |
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| 138 | if (not find_rb) |
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| 139 | num_reg_rb_phy = RAT_GPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_rb_log]; |
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| 140 | if (not find_rc) |
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| 141 | num_reg_rc_phy = RAT_GPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_rc_log]; |
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| 142 | if (not find_rd) |
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| 143 | num_reg_rd_phy_old = RAT_GPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_rd_log]; |
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| 144 | if (not find_re) |
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| 145 | num_reg_re_phy_old = RAT_SPR_NOT_SPECULATIVE[front_end_id][context_id][num_reg_re_log]; |
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| 146 | |
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| 147 | // if rat_SPECULATIVE is valid, |
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| 148 | // then read rat_SPECULATIVE have the most valid alias register |
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| 149 | // else, they have an previous event, the rat_NOT_SPECULATIVE have the valid register |
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| 150 | |
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| 151 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_ra : %d -> %d",num_reg_ra_log,num_reg_ra_phy ); |
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| 152 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rb : %d -> %d",num_reg_rb_log,num_reg_rb_phy ); |
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| 153 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rc : %d -> %d",num_reg_rc_log,num_reg_rc_phy ); |
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| 154 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd : %d -> %d",num_reg_rd_log,num_reg_rd_phy_old); |
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| 155 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re : %d -> %d",num_reg_re_log,num_reg_re_phy_old); |
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| 156 | |
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| 157 | PORT_WRITE(out_RENAME_NUM_REG_RA_PHY [i], num_reg_ra_phy ); |
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| 158 | PORT_WRITE(out_RENAME_NUM_REG_RB_PHY [i], num_reg_rb_phy ); |
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| 159 | PORT_WRITE(out_RENAME_NUM_REG_RC_PHY [i], num_reg_rc_phy ); |
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| 160 | PORT_WRITE(out_RENAME_NUM_REG_RD_PHY_OLD [i], num_reg_rd_phy_old); |
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| 161 | PORT_WRITE(out_RENAME_NUM_REG_RE_PHY_OLD [i], num_reg_re_phy_old); |
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| 162 | } |
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| 163 | } |
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[139] | 164 | } |
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[145] | 165 | |
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[139] | 166 | log_end(Register_Address_Translation_unit,FUNCTION); |
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| 167 | }; |
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| 168 | |
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| 169 | }; // end namespace register_address_translation_unit |
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| 170 | }; // end namespace register_translation_unit |
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| 171 | }; // end namespace rename_unit |
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| 172 | }; // end namespace ooo_engine |
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| 173 | }; // end namespace multi_ooo_engine |
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| 174 | }; // end namespace core |
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| 175 | |
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| 176 | }; // end namespace behavioural |
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| 177 | }; // end namespace morpheo |
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| 178 | #endif |
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